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EE115C Tutorial 2
Layout - Preface
For digital circuits, the design flow is roughly composed of three steps: logic design logic synthesis
physical design. Logic design is something like writing Verilog codes to implement the design and verify it
using SystemVerilog/UVM and so on. Logic synthesis is transferring your codes that describe logic functions
into codes that describe logic gates. Even though after this step, its still just codes but its one step closer to
actual chips and some design flaws can be revealed, such as race hazard. Physical design is the process of
transferring synthesis results to layouts via CAD tools.
Due to the introduction of CAD tools, standard cells and so on, design is more and more shifted to a higher
level, therefore you just need to focus on designing logic of each blocks and everything including layout can
be automatically. Only few groups in the whole world now still design by placing transistors one by one, and
usually this is for small circuits.
However, its still important to learn layout. As designers or testers we still need to know how chips actually
work, and a chip in the end is fabricated according to the layout. Some digital design requires rich knowledge
of layout, such as clock distribution. Also, sometimes we will encounter critical paths in our design, such as
pipelines for a CPU, and therefore we have to design the critical path by hand.

Layout of an inverter using Cadence Virtuoso and 45nm process

Create a new library
To do layout, we need to associate the library with a certain process, since we didnt do it in the previous
tutorial, now we need a new library. Simply give the library a name and proceed, you will encounter the
following window:

Choose Attach to an existing technology library and then select gpdk045. If its successfully attached, you
will see the following in the CDS.log window: INFO (TECH-180011): Design library 'ee115c_layout' successfully
attached to technology library 'gpdk045'.
Create a new cellview, give it a name and make it look like the following schematic:
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Note that the PMOS width is changed to 240n. The four red shapes are pins. Press p and add pins, and
change all of them to inputOutput.
The schematics for layout only contains pins and devices from the pdk library, because only things from the
pdk library can be manufactured by the foundry.
Close the schematic and create a new cellview, this time, change Type to layout and Open with to Layout
XL. So it should look like this:

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Now you will have two windows, one is the layout window and the other is the schematic window for
reference. In the layout window, on the left you will see a Layer window. well, oxide, imp, poly are for
building the gates. Metal 1 and above are metal wires used to connect gates. Normally, Metal 1 and 2 are
for local connections. Then there are up to 4 intermediate connections (metal 3 - 6) for example. In the end
there are up to 5 global connections (metal 7 - 11). The higher the metal number is, the wider the metal wire
will be. Via is used to connect different layers.
The layout window is blank now. Select Connectivity, Generate, All From Source. Then click okay. You will
see the layout as following:

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Everything is just a rectangular and PMOS is wider than an NMOS. The four blue squares are for the four pins
and to see what they are you can simply q them. To reveal the details, select options, display. Change
stop from Display Levels to 10 like the following:

Now the layout window looks like this:

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Green rectangle is poly, which is for gate connection. White squares are source and drain connections to the
metal, blue is metal. You can find all the details in the Layer section. We can utilize CAD tool again to work
for us.
Click Route, Automatic Routing, then hit Run from the new window, then you can see the layout like this:

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To add your own layout, simply select what you want to add from the Layer menu, then at the tool bar,
select Create, Shape, Rectangle. If you want to create wire, you can do it like this, or you can select
Wiring, Wire instead of Shape, Rectangle. Right now, we only need to use Metal 1 (blue) and Poly
(green). Modify the layout to make it look like the following:

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You can clearly see that the input pin is connected to both gates. One source/drain of each MOS is connected
together and also to the output. And the other one is connected to vdd or gnd respectively.
During the design process, you may need to zoom in and out, at the View you can find the operations and
shortcuts. Also, when connecting pins with wires and so on, you should avoid the following:

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DRC
Instructions for DRC are available at the complementary layout tutorial. Basically, you need to click Assura,
Run DRC. You have to manually enter the rule files as indicated in that tutorial.
However, the DRC rule files are located differently. For 45nm process, its the following:

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/w/apps2/public.2/tech/cadence/45nm/gpdk045_v_3_5/assura/assuraDRC.rul
And for 90nm process, its:
/w/apps2/public.2/tech/cadence/90nm/gpdk090_v4.6/assura/drc.rul

LVS
LVS means Layout-Versus-Schematic. This is to make sure your layout correctly reflects your schematic
design.
Instructions for running LVS are in the complementary tutorial. Same as DRC, rule files are located at a
different place.
For 90nm, the LVS Extract Rules is:
/w/apps2/public.2/tech/cadence/90nm/gpdk090_v4.6/assura/extract.rul
Compare Rules:
/w/apps2/public.2/tech/cadence/90nm/gpdk090_v4.6/assura/compare.rul

Extraction
Instructions for extraction can be found in handout Layout Extraction and Post-Layout Simulation.
The Setup Die should be:
/w/apps2/public.2/tech/cadence/90nm/gpdk090_v4.6/assura/rcx
Note that we use RC as Extraction Mode, meaning we extract both resistance and capacitance from layout.
However, for large/complex schematic sometimes we only extract R or C and do individual simulation.

Post-Layout Simulation (Some explanation)

Instructions for post-layout simulation is also in Layout Extraction and Post-Layout Simulation.
However, to do post layout simulation, you should build a test bench. A test bench as like an environment in
which you test your device under test (DUT). Your design should only include devices from a certain pdk. Vdd,
gnd!, input source and output drivers should all be in the test bench instead of DUT. As in real life you need
to put your chip to voltage source, ground it and so on.
In the beginning of design, or before layout is done, the DUT is the schematic you work on. After making the
DUT satisfy specs, you need to make the layout. Layout will introduce a lot of things, for example, wiring will
have resistance and capacitance instead of being ideal. Therefore, we need to extract these things and run
simulation again so that the actual chips can meet the specs. Therefore, now the DUT would be your design
with effects introduced by layout.

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Here is a simple testbench:

gg is the DUT.
We can check gg by descending into it. You can do so by right click or using E.
Since now its pre layout-extraction, this is what we get:

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After finishing layout, drc, lvs, extraction, and following steps from Layout Extraction and Post-Layout
Simulation, the tb remains the same and symbol for pre and post layout schematic is the same symbol.
However, now if we descend into the DUT, this is what we will have:

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