Gate Count Estimation for FPGA

1. XILINX
A. Reference Table for the gate counts in LUT, and FF.

1.1 SPARTAN 6

A single slice features above mentioned components these components and one CLB in SPARTAN 6
consists of these much slices and memory bits etc

1.2 VIRTEX 7
The CLB of VERTEX 7 or 7 series FPGAs of XILINX has the same resources as 6 series i.e same
as SPARTAN 6 (above table). The only difference is that it does not have SLICEX.
Some different resources of VETRX 7 are

Notes
1. Each 7 series slice contain four LUTs and eight flip flops; only SLICEMs can use their LUTs as
distributed RAM or SRLs
2. Number of slices corresponding to the number of LUTs and flip flops supported in the device

1.3 SPARTAN 3
The following tables contains the total system gate counts and the total number of CLBs and Slices,
memory elements etc, so from the report if no. of CLBs are found we can find the gate estimation
easily.

1.4 VIRTEX 5

The VIRTEX-5 slices include:

Four LUTs that can be configured as 6-input LUTs with 1-bit output or 5-input LUTs with 2-bit
output.
Three dedicated user-controlled multiplexers for combinational logic combine outputs of the
slice's LUTs to implement
Dedicated arithmetic logic (two 1-bit adders and a carry chain)
Four 1-bit registers that can be configured either as flip-flops or as latches.

2. ALTERA
A. Calculating Logic array Gates

Before estimating the gate count, calculate the number of gates for a simple and complex function,
simple function determines the lower bound and complex function determines the upper bound. One
LUT and one register are used to implement each function.

LUT usage yields an average of 12 gates per LE. A devices logic array gate count can be determined
by multiplying the number of gates per LE with its LE count. For example, an EP20K1000E device has
38,400 LEs; at 12 gates per LE, the EP20K1000E device has approximately 460,000 logic array
gates.

B. Calculating Embeded array Gates

The embedded array contains ESBs, which are extremely efficient for creating memory functions that
can be configured on-the-fly. APEX 20K devices can implement up to 2 K bits of memory in each ESB
most memory functions use an average of four gates per memory bit.

how to calculate the maximum embedded system gates used for memory implementations
160 ESBs X2048 bits per ESB X4 gates per bit = 1,310,720 gates

ESB Product-Term Logic Gate Count

ESB Look-Up Table Logic Gate Count

160 ESBs X128 gates per ESB(Avg gates for estimation) = 20,480 gates
A key factor in determining gate count is the amount of memory used in the design. To determine
the maximum system gate count for an EP20K1000E device, add the LE gate count to the ESB gate
count. If ESBs are being used to implement both logic and memory, the percentage of ESBs that
implement each function must figure into the gate count computation.

** Cyclone devices follow almost the same structure.