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6800InternalRegisters

6800InternalRegisters
CentralProcessingUnit(CPU)REGISTERS
Thereare6registersavailableintheMotorola6800microprocessor:TheCentralProcessing
Unit(CPU)hasthree16bitregistersandthree8bitregistersavailableforusebythe
programmer.
1.Twoaccumulators(ACCAandACCB)
2.Oneindexregister(X)
3.Oneprogramcounterregister(PC)
4.Onestackpointerregister(SP).
5.Oneconditioncoderegister(CC)
Accumulators
TheMPUcontains2accumulatorsdesignatedACCAandACCB.Eachaccumulatoris8bits
(onebyte)longandisusedtoholdoperandsanddatafromthearithmeticlogicunit.
IndexRegister
Theindexregister(X)isa16bit(2byte)registerwhichisprimarilyusedtostoreamemory
addressintheIndexedmodeofmemoryaddressing.Theindexregistermaybedecremented,
incrementedandstored.
ProgramCounter
Theprogramcounter(PC)isa16bitregisterthatcontainstheaddressofthenextbytetobe
fetchedfrommemory.Whenthecurrentvalueoftheprogramcounterisplacedontheaddress
buss,theprogramcounterwillbeincrementedautomatically.
StackPointer
TheStackPointer(SP)isa16bit(2byte)registerthatcontainsabeginningaddress,normallyin
RAM,wherethestatusoftheMPUregistersmaybestoredwhentheMPUhasotherfunctions
toperform,suchasduringaninterruptorduringaBranchtoSubroutine.Theaddressinthe
stackpointeristhestartingaddressofsequentialmemorylocationsinRAMwhereMPUstatus
registerswillbestored.Inthoseapplicationsthatrequirestorageofinformationinthestack
whenpowerislost,thestackmustbenonvolatile.
ConditionCodeRegister(CC)
Theconditioncoderegisterisan8bitregister.Eachindividualbitmaygetsetorgetcleared
fromexecutionofaninstruction.Eachinstructioneffectstheconditioncoderegisterdifferently.
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Theprimaryuseofthisregisterisexecutionoftheconditionalbranchinstruction.Bit6and7are
notusedandremainatlogic1.
BIT(07)NumberFunction:
0C(CarryBorrowTest)
1V(OverflowTest)
2Z(ZeroTest)
3N(NegativeTest)
4I(InterruptMaskTest)
5H(HalfCarryTest).MPU7
CarryBorrow:Foraddition,thecarryborrowconditioncode(C)inthezerobitposition,
representsacarry.Thisbitgetsset(C=1)toindicateacarry,andisreset(C=0)ifthereisno
carry.
Forsubtraction,theCbitisset(C=1)toindicateaborrowandisreset(C=0)toindicatethere
wasnoborrow.
Overflow:TheVbit(bit1)oftheconditioncoderegisterisset(V=1)whentwo'scomplement
overflowresultsfromanarithmeticoperation,andisreset(V=O)iftwo'scomplementoverflow
doesnotoccur.
Zero:TheZbit(bit2)oftheconditioncoderegisterisset(Z=1)iftheresultofanarithmetic
operationiszero,andisreset(Z=0)iftheresultisnotzero.
Negative:TheNbit(bit3)oftheconditioncoderegisterisset(N=1)ifbit7ofanarithmetic
operationisset(equalto1).Thisindicatesthatthetwo'scomplementnumber,representedby
thebitpatternoftheresult,isnegative.TheNbitisreset(N=0)ifbit7ofthearithmeticresultis
equalto0.
InterruptMask:IfthisIbit(bit4)isset(I=1),theMPUcannotrespondtoaninterruptrequest
fromanyperipheraldevice.
HalfCarry:ThehalfcarrybitH(bit5)oftheconditioncoderegisterisset(H=1)during
executionofanyoftheinstructionsABA,ADC,orADD,ifthereisacarryfrombitposition3tobit
position4.Thehalfcarryisreset(H=0)duringtheseoperations,ifthereisnocarryfrombit
position4.

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InternalBlockDiagramofthe6800CentralProcessingUnit(CPU)

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