EXPmnt1to 5

Experiment No.
1(A)
Roll No. : 03
Aim :
Plot current voltage characteristics of NMOS transistor using 0.5 micron

technology.
Circuit
Diagram :
Stick
Diagram :
11/22/2015 11:15:08 PM
Page 1 of 4
Layout :
T-Spice Parameter :
S-Edit
* Cell:
Cell0
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Users\USER\Desktop\\NMOS2
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Users\USER\Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_2 N_1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VV1 N_2 Gnd DC 5
VV2 N_1 Gnd DC 5
.print dc i(MNMOS_1,GND)
********* Simulation Settings - Analysis section *********
.dc lin VV1 0 5 0.1 lin VV2 0 5 1
********* Simulation Settings - Additional SPICE commands *********
11/22/2015 11:15:08 PM
Page 2 of 4
.end
L-Edit
* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: C:\Users\USER\Desktop\Renu\nmosLayoutnew.tdb
* Cell: Cell0 Version 1.05
* Extract Definition File: ..\..\Documents\Tanner EDA\Tanner Tools v13.0\Supporting
Files\New folder\MORBN20mod.EXT
* Extract Date and Time: 10/30/2015 - 22:54
.include "C:\Users\USER\Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Supporting Files1\MD\ml2_125.md"
* Warning: Layers with Unassigned FRINGE Capacitance.

* <Pad Comment>
* <Poly1-Poly2 Capacitor>
M1 vdd in vss 3 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u

10)
vgs in vss 0
vds vdd vss 0
.dc ids 0 250e-6 50e-6
.dc vds 0 5 0.05 sweep vgs 0 5 1
.plot ids(M1)
* Total Nodes: 4
* Total Elements: 1
* Total Number of Shorted Elements not written to the SPICE file: 0
* Output Generation Elapsed Time: 0.000 sec
* Total Extract Elapsed Time: 1.047 sec
.END
Simulation Result :
S-Edit
$ (42 4 44
Cell0
iD(MNMOS_2)
3.5
3.0
Current (mA)
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VV1 (V)
11/22/2015 11:15:08 PM
Page 3 of 4
L-Edit
Result /
Conclusion
:
Thus the current voltage characteristics of NMOS transistor using 0.5 micron
technology are plotted.
Roll No. :
03
Sem/Br :
VLSI-1
Marks out
of 10
Signature :
Name of Lecturer :Y.A.Gaidhani
11/22/2015 11:15:08 PM
Page 4 of 4
Experiment No. 1(B)

Roll No. : 03
Aim :
To plot the current voltage characteristics of PMOS transistor using 0.5

micron technology.
Circuit
Diagram
:
Stick
Diagram
:
11/22/2015 11:15:43 PM
Page 1 of 4
Layout :
T-Spice Parameter :
S-Edit
* SPICE export by: SEDIT 13.00

* Export time:
Fri Oct 30 21:26:05 2015
* Design:
pmos1
* Cell:
Cell0
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
E:\DID PRACT\New folder\pmos1
*-------- Devices: SPICE.ORDER > 0 -------MPMOS_1 Gnd N_2 N_1 N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VV1 N_2 Gnd DC 5
VV2 N_1 Gnd DC 5
.print dc i(MPMOS_1,GND)
11/22/2015 11:15:43 PM
Page 2 of 4

.dc lin VV2 0 5 0.1 lin VV1 0 5 1
L-Edit
.end
* TDB File: C:\Users\USER\Documents\Tanner EDA\did1\pmosLayoutnew.tdb
* Extract Definition File: ..\Tanner Tools v13.0\Supporting Files\New
folder\MORBN20mod.EXT

* <Pad Comment>
.include "C:\Users\USER\Documents\Tanner EDA\Tanner Tools v13.0\Supporting
Files\MD\ml2_20md"
M1 vout in vdd 3 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
vgs in vdd 5
vds vout vdd 5
.dc vds 0 -4 -0.05 sweep vgs 0 -4 -1
.dc ids 0 250e-6 50e-6
.plot i(M1)
* Total Nodes: 4
* Total Elements: 1
.END
Simulation Result :
$ (46 3 48 9)
S-Edit
11/22/2015 11:15:43 PM
Page 3 of 4
L-Edit
Result/
Conclusio
n:
Roll No.
Thus the current voltage characteristics of PMOS transistor using 1 micron technology are
plotted.
03
Marks out
of 10
Signature :
Sem/Br : VLSI-1
Name of Lecturer :Y.A. Gaidhani
11/22/2015 11:15:43 PM
Page 4 of 4
Experiment No. 2
Roll No. : 03
Aim :
Design CMOS INVERTER using 0.5 micron technology.
Circuit
Diagram :
Stick
Diagram :
11/22/2015 11:25:56 PM
Page 1 of 4
Layout :
T-Spice Parameter :
S-Edit
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
E:\DID PRACT\New folder\inverternew
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out In N_1 N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VV1 N_1 Gnd DC 5
VV2 In Gnd BIT({0100101111} )
.tran 10n 100n
.print tran v(Out,Gnd) v(In,Gnd)

.dc lin VV1 5 0 0.1 lin VV2 0 5 1
.end
11/22/2015 11:25:56 PM
Page 2 of 4
L-Edit
* TDB File: C:\Users\USER\Desktop\Renu\inverterLayout.tdb
* Extract Definition File: E:\DID PRACT\Tanner Supporting Files\MORBN20mod.EXT
.include "E:\DID PRACT\Tanner Supporting Files\Supporting Files\MD\ml2_20.md"

* <Pad Comment>
M1 vout in vdd 5 PMOS L=2u W=8u AD=48p PD=28u AS=48p PS=28u $ (43 8 45
16)
M2 vout in vss 4 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u $ (43 -17 45 11)
Vdd Vdd Vss 5
Vin in Vss BIT ({11100011} on=5 off=0)
.print tran v(in,Vss) v(vout,Vss)
.tran 10n 100n
* Total Nodes: 6
* Total Elements: 2
.END
11/22/2015 11:25:56 PM
Page 3 of 4
Simulation Result :
S-Edit
L-Edit
Result/Conclu
sion:
Thus, cmos inverter is designed.
Roll No. :
03
Sem/Br :
VLSI-1
Marks out
of 10
Signature :
Name of Lecturer:Y.A.Gaidhani
11/22/2015 11:25:56 PM
Page 4 of 4
Experiment No. 3
Roll No. : 03
Aim :
To plot transfer characteristic of Pseudo NMOS inverter with w/l for PMOS is
equal to twice w/l of NMOS.
Circuit
Diagram :
Stick Diagram :
11/22/2015 11:26:38 PM
Page 1 of 4
Layout :
T-Spice Parameter :
S-Edit
* SPICE export by: SEDIT 13.00

* Export time: Wed Nov 04 21:44:32 2015
* Design:
pseudon
* Cell:
Cell0
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
E:\diiii\sagar\mtech renu\RENU\SEDIT\pseudon
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MPMOS_1 Out Gnd Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
VV1 gnd dc 5 BIT ({010010111} on=5 off=0)
11/22/2015 11:26:38 PM
Page 2 of 4
VV2 Vdd Gnd DC 5

.print tran v(In,gnd) v(Out,gnd)
.tran 10n 100n
.end
L-Edit
* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version
13.00 ;
* TDB File: D:\psuedo nmos\psuedo.tdb
* Extract Definition File: C:\Documents and Settings\eestud1\Desktop\Tanner
Supporting Files\MORBN20mod.EXT
.lib "C:\Documents and Settings\eestud1\Desktop\Tanner Supporting

Files\Supporting Files\MD\ml2_125.md"

* <Pad Comment>
M1 out vssvdd 6 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u $ (29 16
31 22)
M2 out in vss 4 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u $ (29 -6
31 0)
VDD vddvss 5
vin in vss BIT ({010010111} on=5 off=0)
.tran 10n 100n
.print tran v(out,vss) v(in,vss)
* Total Nodes: 6
* Total Elements: 2
.END
11/22/2015 11:26:38 PM
Page 3 of 4
S-Edit
L-Edit
Result /
Conclusion :
Thus transfer characteristic of Pseudo NMOS inverter with w/l for PMOS is equal
to twice w/l of NMOS is plotted and verified
Roll No. :
03
Sem/Br :
VLSI-1
Marks
out of
10
Signature :
Name of Lecturer : Y.A. Gaidhani
11/22/2015 11:26:38 PM
Page 4 of 4
Experiment No. 4
Roll No. : 03
Aim :
To design and simulate CMOS NAND gate using 0.5 micron technology.
Circuit
Diagram :
Stick
Diagram :
11/22/2015 11:27:27 PM
Page 1 of 5
Layout :
T-Spice Parameter :
S-Edit
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
E:\DID PRACT\New folder\NAND
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out A N_2 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_2 B Gnd N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out A Vdd N_4 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out B Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VV3 Vdd Gnd DC 5
11/22/2015 11:27:27 PM
Page 2 of 5
VV1 A gnd dc 5 BIT ({11001100} on=5 off=0)

VV2 B gnd dc 5 BIT ({11101110} on=5 off=0)
.print tran v(A,gnd) v(B,gnd) v(Out,gnd)
.tran 10n 100n
.dc lin VV3 0 5 0.01 lin VV1 0 5 1 lin VV2 0 5 1
L-Edit
.end
* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00
;
* TDB File: D:\nand\Layout2.tdb
* Extract Date and Time: 30/10/2015 5.27
.lib "C:\Documents and Settings\eestud1\Desktop\Tanner Supporting Files\Supporting
Files\MD\ml2_125.md"

* <Pad Comment>
11/22/2015 11:27:27 PM
Page 3 of 5
M1 out in2 vdd 7 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u $ (-18 22 16 28)
M2 vdd in1 out 7 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u $ (-26 22 24 28)
M3 out in2 5 4 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u $ (-18 2 -16
8)
M4 5 in1 gnd 4 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u $ (-26 2 -24
8)
VDD vdd gnd 5
vin1 in1 gnd dc 5 BIT ({11001100} on=5 off=0)
.tran 10n 100n
.print tran v(in1,gnd) v(in2,gnd) v(out,gnd)
* Total Nodes: 8
* Total Elements: 4
.END
S-Edit
11/22/2015 11:27:27 PM
Page 4 of 5
L-Edit
Result /
Thus, We have designed and simulated CMOS NAND gate using 0.5 micron
Conclusion/ technology.
Observation:
Roll No. :
03
Sem/Br :
VLSI-1
Marks out
of 10
Signature :
11/22/2015 11:27:27 PM
Page 5 of 5
Experiment No. 5
Roll No. : 03
Aim :
To design and simulate CMOS NOR gate using 0.5 micron technology.
Circuit
Diagram :
Stick
Diagram :
11/22/2015 11:28:21 PM
Page 1 of 5
Layout :
T-Spice Parameter :
S-Edit
* Cell:
Cell0
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
E:\DID PRACT\New folder\nor
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out A Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_1 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out B N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
vin1 A GND dc 5 BIT ({11001100} on=5 off=0)
vin2 B GND dc 5 BIT ({11101110} on=5 off=0)
.tran 10n 100n
11/22/2015 11:28:21 PM
Page 2 of 5
.print tran v(A,GND) v(B,GND) v(Out,GND)

L-Edit
.end
* TDB File: D:\NOR\Layout3.tdb
* Extract Date and Time: 11/03/2015 8:48
.lib "C:\Documents and Settings\eestud1\Desktop\Tanner Supporting Files\Supporting
Files\MD\ml2_125.md"
* <Pad Comment>
M1 out in2 8 6 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u $ (24 10 26 16)
M2 8 in1 Vdd 6 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u $ (16 10 18
16)
M3 out in2 gnd 4 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u $ (24 -14 26
-8)
M4 gnd in1 out 4 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u $ (16 -14 18
-8)
VDD vddgnd 5
.tran 10n 100n

.print tran v(out,gnd) v(in1,gnd) v(in2,gnd)
* Total Nodes: 8
* Total Elements: 4
.END
11/22/2015 11:28:21 PM
Page 3 of 5
Simulation Result :
S-Edit
L-Edit
11/22/2015 11:28:21 PM
Page 4 of 5
Result /
Thus, We have designed and simulated CMOS NOR gate using 0.5 micron
Conclusion technology.
/
Obervastio
n:
Roll No. : 03
Marks out of
10
Signature :
Sem/Br : VLSI-1
11/22/2015 11:28:21 PM
Page 5 of 5

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Experiment No.

Plot current voltage characteristics of NMOS transistor using 0.5 micron

* Warning: Layers with Unassigned FRINGE Capacitance.

M1 vdd in vss 3 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u

Experiment No. 1(B)

To plot the current voltage characteristics of PMOS transistor using 0.5

* SPICE export by: SEDIT 13.00

* Simulation Settings - Analysis section *

* Warning: Layers with Unassigned FRINGE Capacitance.

Design CMOS INVERTER using 0.5 micron technology.

* Simulation Settings - Analysis section *

* Warning: Layers with Unassigned FRINGE Capacitance.

Thus, cmos inverter is designed.

* SPICE export by: SEDIT 13.00

VV2 Vdd Gnd DC 5

.lib "C:\Documents and Settings\eestud1\Desktop\Tanner Supporting

* Warning: Layers with Unassigned FRINGE Capacitance.

VV1 A gnd dc 5 BIT ({11001100} on=5 off=0)

* Warning: Layers with Unassigned FRINGE Capacitance.

.print tran v(A,GND) v(B,GND) v(Out,GND)

.tran 10n 100n

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