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CAN TRANSCEIVER
FEATURES
APPLICATIONS
DESCRIPTION
The SN65HVD251 is intended for use in applications employing the Controller Area Network (CAN) serial
communication physical layer in accordance with the ISO 11898 Standard. The SN65HVD251 provides
differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1
megabits per second (Mbps).
Designed for operation in harsh environments, the device features cross-wire, over-voltage and loss of ground
protection to 36 V. Also featured are over-temperature protection as well as -7 V to 12 V common-mode range,
and tolerance to transients of 200 V. The transceiver interfaces the single-ended CAN controller with the
differential CAN bus found in industrial, building automation, and automotive applications.
Rs, pin 8, provides for three different modes of operation: high-speed, slope control, or low-power mode. The
high-speed mode of operation is selected by connecting pin 8 to ground, allowing the transmitter output
transistors to switch as fast as possible with no limitation on the rise and fall slope. The rise and fall slope can be
adjusted by connecting a resistor to ground at pin 8; the slope is proportional to the pin's output current. Slope
control with an external resistor value of 10 k gives ~ 15 V/us slew rate; 100 k gives ~ 2 V/us slew rate.
If a high logic level is applied to the Rs pin 8, the device enters a low-current standby mode during which the
driver is switched off and the receiver remains active . The local protocol controller reverses this low-current
standby mode when it needs to transmit to the bus.
The SN65HVD251 may be used in CAN, DeviceNet or SDS applications with the Texas Instruments'
TMS320F241 and TMS320F243 DSPs with CAN 2.0B controllers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Allen-Bradley.
SDS is a trademark of Honeywell.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD251
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function diagram
(positive logic)
VCC
D
GND
Rs
Vcc
3
4
6
5
CANH
CANL
Vref
(1)
(1)The
5 V
ref
1
D
RS 8
R
(1)
7
CANH
6 CANL
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKED AS
SN65HVD251D
VP251
SN65HVD251DR
VP251
SN65HVD251P
8-pin DIP
65HVD251
signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
-0.3 V to 7V
-36 V to 36 V
200 V
CANH, CANL
Electrostatic discharge
(3)
Charged-Device Model
(4)
14 kV
All pins
6 kV
All pins
1 kV
-65C to 150C
260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
CIRCUIT BOARD
MODEL
TA = 25C
POWER RATING
Low-K (2)
600 mW
High-K (3)
963 mW
DERATING FACTOR
ABOVE TA = 25C
(1)
TA = 85C POWER
RATING
TA = 125C POWER
RATING
4.4 mW/C
312 mW
120 mW
7.7 mW/C
501 mW
193 mW
Low-K (2)
984 mW
7.8 mW/C
512 mW
197 mW
High-K (3)
1344 mW
10.8 mW/C
699 mW
269 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
MIN
JB
TYP
78.7
56.5
UNITS
MAX
C/W
SN65HVD251
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TEST CONDITIONS
VALUE
MIN
JC
PD
TSD
UNITS
TYP
44.6
54.5
MAX
C/W
VCC = 5 V, Tj = 27 C, RL = 60,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
97.7
mW
142
mW
165
MIN
D input
D input
NOM
-7 (1)
12
0.7 VCC
0.3 VCC
VCC
0.75 VCC
VCC
100
Rs wave-shaping resistance
Driver
-50
Receiver
mA
-4
Driver
50
Receiver
4
-40
Junction temperature, Tj
(1)
-6
UNIT
5.5
MAX
4.5
125
PDIP Package
145
SOIC Package
150
mA
C
C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
TEST CONDITIONS
CANH
TYP (1)
MIN
2.75
3.5
MAX
UNIT
4.5
VO(D)
VO(R)
VOD(D)
Figure 1 , D at 0 V, Rs at 0 V
VOD(D)
1.2
VOD(R)
-120
VOD(R)
-0.5
VOC(pp)
Figure 9, Rs at 0 V
IIH
D at 0.7 VCC
-40
IIL
D at 0.3 VCC
-60
(1)
CANL
CANH
CANL
0.5
2.5
2.5
1.5
3.1
12
mV
0.05
600
V
mV
SN65HVD251
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TEST CONDITIONS
Figure 11, VCANH at -7 V,
CANL Open
IOS(SS)
TYP (1)
MIN
MAX
2.5
mA
-2
200
CO
Output capacitance
IOZ
IIRs(s)
Rs at 0.75 VCC
IIRs(f)
ICC
Supply current
UNIT
-200
-10
Rs at 0 V
-550
275
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60 load, Rs at 0 V
65
Recessive
D at VCC, no load, Rs at 0 V
14
mA
TEST CONDITIONS
TYP
MAX
Figure 4, Rs at 0 V
MIN
40
70
90
125
500
800
85
125
200
260
1150
1450
Figure 4, Rs at 0 V
tpHL
Figure 4, Rs at 0 V
tsk(p)
tr
tf
tr
tf
tr
tf
ten
45
85
110
180
650
900
35
100
35
100
100
250
100
250
600
1550
600
1550
Figure 8
0.5
UNIT
ns
TEST CONDITIONS
VIT+
VIT-
Vhys
VOH
Figure 6, IO = -4mA
VOL
Figure 6, IO = 4mA
Rs at 0 V, (See Table 1)
MIN
500
TYP
MAX
750
900
650
UNIT
mV
100
0.8 Vcc
V
0.2 Vcc
SN65HVD251
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TEST CONDITIONS
MIN
TYP
MAX
CANH or CANL at 12
V
II
CANH or CANL at 12
V, VCC at 0 V
CANH or CANL at -7
V, VCC at 0 V
715
-340
20
CID
10
RID
D at 0.7 VCC, Rs at 0 V
40
RIN
D at 0.7 VCC, Rs at 0 V
20
Supply current
-460
CI
ICC
UNIT
600
pF
pF
100
50
275
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60 Load, Rs at 0 V
65
Recessive
D at VCC, No Load, Rs at 0 V
14
mA
TEST CONDITIONS
tpLH
tpHL
tsk(p)
tr
tf
tp(sb)
MIN
TYP
MAX
35
50
35
50
Figure 6
20
2
2
UNIT
ns
4
500
VREF-PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
VO
TEST CONDITIONS
-5 A < IO < 5 A
-50 A < IO < 50 A
MIN
TYP
MAX
0.45 VCC
0.55 VCC
0.4 VCC
0.6 VCC
UNIT
V
SN65HVD251
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TEST CONDITIONS
MIN
TYP
Figure 10, Rs at 0 V
tloop1
tloop2
tloop2
60
100
100
150
440
800
Figure 10, Rs at 0 V
115
150
235
290
1070
1450
105
145
VO(CANH)
D
VOD
II
60 1%
IIRs
Rs
VI
VO(CANH) + VO(CANL)
2
VOC
IO(CANL)
VI(Rs)
_
VO(CANL)
Recessive
3.5 V
VO(CANH)
2.5 V
1.5 V
VO(CANL)
VI
VOD
330 1%
60 1%
+
_
RS
CANL
330 1%
MAX
7 V VTEST 12 V
UNIT
ns
ns
ns
SN65HVD251
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D
VI
RL =
60 1%
+
VI(Rs)
_
Rs
(see Note A)
CL =
50 pF 20%
(see Note B)
VO
CANH
VCC
VCC/2
VI
VCC/2
0V
tPHL
tPLH
0.9V
VO
90%
10%
tr
VO(D)
0.5V
VO(R)
tf
VI(CANH)
VI(CANH) + VI(CANL)
VIC =
2
VI(CANL)
IO
VID
VO
CANL
CANL
(see Note A)
1.5 V
IO
CL = 15 pF
20% (see Note B)
VO
3.5 V
VI
2.4 V
2V
1.5 V
tPLH
VO
tPHL
0.7 VCC
10%
90%
tr
VOH
0.3 VCC
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, tr
6ns, tf 6ns, ZO = 50.
B.
SN65HVD251
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D at 0 V
or VCC
RS at 0 V or VCC
A.
This test is conducted to test survivability only. Data stability at the R output is not specified.
MEASURED
OUTPUT
VCANH
VCANL
|VID|
12 V
11.1 V
900 mV
-6.1 V
-7 V
900 mV
-1 V
-7 V
6V
12 V
6V
6V
-6.5 V
-7 V
500 mV
12 V
11.5 V
500 mV
-7 V
-1 V
6V
6V
12 V
6V
open
open
DUT
CANH
0V
VI
D
60 1%
Rs
CANL
R
+
VO
_
15 pF 20%
VCC
0.7 VCC
VI
0V
VOH
0.3 VCC
VO
ten
0.3 VCC
VOL
VOL
VOH
SN65HVD251
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CANH
27 1%
D
VI
CANL
27 1%
RS
VOC
50 pF 20%
VOC(PP)
VOC
A.
The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, tr
6ns, tf 6ns, ZO = 50.
60 1%
10 k or 100 k 5%
_
RS
CANL
VRs +
R
+
VO
_
15 pF 20%
VCC
50%
D Input
0V
tLoop2
tLoop1
VOH
0.7 Vcc
R Output
0.3 Vcc
VOL
SN65HVD251
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IOS
CANH
0 V or VCC
CANL
Rs
Vin 7 V or 12 V
IOS(SS)
IOS(P)
15 s
0V
12 V
Vin
0V
10 s
or
0V
Vin
7 V
CANL
CL = 15 pF
1.5 V
VO
(see Note B)
3.5 V
2.4 V
VI
1.5 V
tp(sb)
VOH
VO
0.3 VCC
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, tr
6ns, tf 6ns, ZO = 50.
B.
Figure 12. Receiver Propagation Delay in Standby Test Circuit and Waveform
10
SN65HVD251
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DEVICE INFORMATION
5V
R21%
R11%
CANH
VID
CANL
Vac
R11%
VI
R21%
VID
R1
R2
500 mV
50
450
900 mV
50
227
12 V
VI
7 V
A.
All input pulses are supplied by a generator having the following characteristics: f < 1.5 MHz, TA = 25oC, VCC = 5.0 V.
FUNCTION TABLES
Table 2. DRIVER
INPUTS
D
OUTPUTS
CANH
BUS STATE
CANL
Dominant
Recessive
Open
Recessive
Recessive
Table 3. RECEIVER
(1)
OUTPUT R (1)
VID 0.9 V
VID 0.5 V
Open
11
SN65HVD251
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D Input
R Output
VCC
VCC
100 k
5
1 k
Input
Output
9V
9V
CANH Input
CANL Input
VCC
VCC
110 k
110 k
9 k
45 k
9 k
45 k
Input
Input
40 V
40 V
9 k
9 k
Rs Input
VCC
VCC
Output
40 V
+_
Input
12
SN65HVD251
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TYPICAL CHARACTERISTICS
tLOOP1-LOOP TIME
vs
FREE-AIR TEMPERATURE
tLOOP2-LOOP TIME
vs
FREE-AIR TEMPERATURE
150
33
72
VCC = 4.5 V
VCC = 5 V
70
68
66
VCC = 5.5 V
VCC = 5.5 V
VCC = 5 V
140
135
130
VCC = 4.5 V
64
125
62
40 25 10 5
120
40 25 10 5
20 35 50 65 80 95 110 125
32
31
30
29
28
27
26
25
0
35 50 65 80 95 110 125
VCC = 5 V,
TA = 25C,
RS = 0 V,
RL = 60 ,
CL = 50 pF
TA Free-Air Temperature C
Figure 15.
Figure 16.
Figure 17.
DOMINANT DIFFERENTIAL
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
140
TA Free-Air Temperature C
20
VCC = 5 V,
TA = 25C,
RS = 0 V,
D at 0V
120
100
80
60
40
20
0
80
VCC = 5 V,
TA = 25C,
RS = 0 V,
D at 0V
70
60
50
40
30
20
10
0
0
145
RS = 0 V
RS = 0 V
74
3
VCC = 5.5 V
2.5
2
VCC = 4.5 V
VCC = 5 V
1.5
1
RS = 0 V,
D at 0V,
RL = 60
0.5
0
55
40
25
70
85
125
TA Free-Air Temperature C
Figure 18.
Figure 19.
Figure 20.
13
SN65HVD251
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DIFFERENTIAL OUTPUT
FALL TIME
vs
SLOPE RESISTANCE (Rs)
50
40
30
20
10
0
TA = 25C
900
800
VCC = 5.5 V
VCC = 5 V
700
600
VCC = 4.5 V
500
400
300
200
Figure 21.
0.50
VCC = 5.5 V
1
1.50
VCC = 5 V
2
VCC = 4.5 V
2.50
100
3
0
1
TA = 25C,
RS = 0 V,
D at 0V,
RL = 60
1000
60
14
10 20 30 40 50 60 70 80 90 100
RS - Slope Resistance - k
Figure 22.
50
50
100
TA Free-Air Temperature C
Figure 23.
150
SN65HVD251
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APPLICATION INFORMATION
The basics of arbitration require that the receiver at
the sending node designate the first bit as dominant
or recessive after the initial wave of the first bit of a
message travels to the most remote node on a
network and back again. Typically, this sample is
made at 75% of the bit width, and within this
limitation, the maximum allowable signal distortion in
a CAN network is determined by network electrical
parameters.
Factors to be considered in network design include
the 5 ns/m propagation delay of typical twisted-pair
bus cable; signal amplitude loss due to the loss
mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under
strict analysis, variations among the different oscil-
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A large
number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the Standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the Standard's 2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The HVD251 enhances the Standard's insurance of data
integrity with an extended 7-V to 12-V range of common-mode operation.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
ALLOWABLE JITTER
SN65HVD251
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An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all of the
effects of systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC & ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most all sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help insure data integrity.
Typical Application
Bus Lines 40 m max
CANH
120
120
VCC
5V
SN65HVD251
0.1 F
Vref
RS
VCC
CANTX
CANRX
0.1 F
SN65HVD251
GND
D
5V
RS
VCC
SN65HVD230
GND
D
CANTX
CANRX
GND
D
CANTX
CANRX
TMS320F243
TMS320F243
TMS320LF2407A
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
16
Vref
3.3 V
0.1 F
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Lead/Ball Finish
SN65HVD251D
ACTIVE
SOIC
75
None
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD251DR
ACTIVE
SOIC
2500
None
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD251DRG4
PREVIEW
SOIC
2500
None
Call TI
SN65HVD251P
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
Call TI
Level-NC-NC-NC
(1)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
0.260 (6,60)
0.240 (6,10)
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.015 (0,38)
Gage Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
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