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or
What are Programs Doing Most of the Time?
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Aspects of interest:
1. The frequency of operations performed.
2. The types of operands and their frequency of
use.
3. Execution sequencing (frequency of jumps,
loops, subprogram calls).
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int x, y; float z;
void proc3(int a, int b, int c) {
- - - - - - - - - - - - - -- - }
--------------------void proc2(int k) {
int j, q;
----------------proc3(j, 5, q);
}
--------------------void proc1() {
int i;
----------------proc2(i);
}
--------------------main () {
proc1();
}
Some statistics concerning procedure calls:
Only 1.25% of called procedures have more than
six parameters.
Only 6.7% of called procedures have more than six
local variables.
Chains of nested procedure calls are usually short
and only very seldom longer than 6.
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Assume:
- we have a program with 80% of executed
instructions being simple and 20% complex;
- on a CISC machine simple instructions take 4
cycles, complex instructions take 8 cycles;
cycle time is 100 ns (10-7 s);
- on a RISC machine simple instructions are
executed in one cycle; complex operations are
implemented as a sequence of instructions; we
consider on average 14 instructions (14 cycles)
for a complex operation; cycle time is 75 ns
(0.75 * 10-7 s).
FI DI CA TR
Load-and-store architecture
- Only LOAD and STORE instructions reference
data in memory; all other instructions operate
only with registers (are register-to-register instructions); thus, only the few instructions accessing memory need more than one cycle to
execute (after fetched and decoded).
Pipeline operation with memory reference:
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FI DI CA TR
ADD R2,R1
FI DI
ADD R4,R3
FI
stall
EI
DI EI
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R1,X
R2,R1
R4,R3
R2,R4
The value in R1 is
not yet available!
LOAD R1,X
FI DI CA TR
ADD R2,R1
FI DI EI
ADD R4,R3
SUB R2,R4
FI DI EI
FI DI EI
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FI DI CA TR
ADD R4,R3
FI DI EI
ADD R2,R1
SUB R2,R4
FI DI EI
FI DI EI
ADD R4,R2
STORE R4,X
FI DI CA TR
NOP
ADD R2,R1
FI DI EI
FI DI EI
FI DI CA TR
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Summary
Both RISCs and CISCs try to solve the same problem: to cover the semantic gap. They do it in different ways. CISCs are going the traditional way of
implementing more and more complex instructions.
RISCs try to simplify the instruction set.
Innovations in RISC architectures are based on a
close analysis of a large set of widely used
programs.
The main features of RISC architectures are:
reduced number of simple instructions, few
addressing modes, load-store architecture,
instructions are of fixed length and format, a large
number of registers is available.
One of the main concerns of RISC designers was
to maximise the efficiency of pipelining.
Present architectures often include both RISC and
CISC features.