M.

Tech VLSI
IEEE 2015 Projects on Advanced VLSI Design
Code Project Title
15V01

Year Downloads Downloads Reversible

Design of priority encoding based reversible comparators

IEEE 2015

15V02

On the Analysis of Reversible Booths Multiplier

15V03
IEEE 2015

Berger check and fault tolerant reversible arithmetic component design

15V04

Parity Preserving Adder/Subtractor Using a Novel Reversible Gate

15V05

Online Testing for Three Fault Models in Reversible Circuits

15V06
2015

A New Gate for Low Cost Design of All-optical Reversible Logic Circuit

15V07

15V08

15V09
2015

IEEE 2015

IEEE 2015

IEEE 2015

Implementation of Testable Reversible Sequential Circuit on FPGA

Cryptography

Synthesis of Balanced Quaternary Reversible Logic Circuit

IEEE

IEEE 2015

IEEE 2015

A Novel Realization of Reversible LFSR for its Application in Cryptography

IEEE

15V10

Z-TCAM: An SRAM-based Architecture for TCAM

IEEE 2015

15V11

IC Layout Design of Decoder Using Electric VLSI Design

IEEE 2015

15V12

Low-Complexity Tree Architecture for Finding the First Two Minima

15V13
Circuits

Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated

IEEE 2015

15V14

Synthesis of Balanced Quaternary Reversible Logic Circuit

IEEE 2015

IEEE 2015

15V15
Low-Power and Area-Efficient Shift Register Using Pulsed Latches
2015 Cryptography

IEEE

15V16
Circuits

A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential

IEEE 2015

15V17
Applications

A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight

IEEE 2015

15V18
Memory

A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack
IEEE 2015

15V19
Low power Multiplier Architectures using Vedic Mathematics in 45 nm Technology for
High Speed Computing
IEEE 2015

15V20

Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer
IEEE 2015

15V21
2015

Design of a Power Optimal Reversible FIR Filter for Speech Signal Processing

15V22

Low-Power Programmable PRPG With Test Compression Capabilities

15V23

IEEE

IEEE 2015

Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder
IEEE 2015

15V26
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
2015
Cryptography

IEEE

15V27 Design and Analysis of Approximate Compressors for Multiplication

IEEE 2015

15V28 Recursive Approach to the Design of a Parallel Self-Timed Adder

IEEE 2015

15V29 High-Speed and Energy-Efficient Carry Skip Adder

Operating Under a Wide Range of Supply Voltage Levels

IEEE 2015

15V30 High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter

IEEE 2015

15V31 Implementation of high performance SRAM Cell Using Transmission Gate

IEEE 2015

15V32 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
IEEE 2015

Cryptography

15V33 Ultralow-Energy Variation-Aware Design: Adder Architecture Study

IEEE 2015

15V34 All Optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential

Counters
IEEE 2015

Cryptography
15V35 Design of Full Adder circuit using Double Gate MOSFET

IEEE 2015

15V36 Design of Optimized Reversible Binary and BCD Adders

IEEE 2015

15V37 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell

IEEE 2015

15V38 Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital
Logic Circuits IEEE 2015

15V39 Modeling CMOS Gates Using Equivalent Inverters

IEEE 2015

15V40 Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm

2015

15V41 A Linear Comparator-based Fully Digital Delay Element

IEEE

IEEE 2015

15V42 Variable Latency Speculative Han-Carlson Adder

IEEE 2015

15V43 Index-based Round-Robin Arbiter for NOC Routers

IEEE 2015

Cryptography
15V44 An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC

IEEE

2015

15V45 A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic IEEE
2015

15V46 A novel design of reversible 2:4 decoder

IEEE 2015

15V47 Design and Implementation of a Reversible Central Processing Unit

IEEE 2015

15V48 Performance Comparison of Pass Transistor and CMOS Logic Configuration based DeMultiplexers IEEE 2015

15V49 Quaternary Logic Lookup Table in Standard CMOS

IEEE 2015

15V50 Logic Debugging of Arithmetic Circuits IEEE 2015

15V51 Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression
IEEE 2015

15V52 A 32 BIT MAC Unit Design Using Vedic Multiplier and Reversible Logic Gate IEEE 2015

Cryptography
15V53 Towards reversible QCA computers: reversible gates and ALU

IEEE 2015

15V54 Design And Development of Efficient Reversible Floating Point Arithmetic unit IEEE 2015

15V55 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic IEEE 2015

15V56 Parallel Prefix Modulo Adder via Double Representation of Residues in [0, 2]

IEEE 2015

15V57 Design And Implementation Of Field Programmable Gate Array Based Error Tolerant Adder For
Image Processing Application IEEE 2015

15V58 Design and Implementation of Arithmetic Logic Unit (ALU) using Modified Novel Bit Adder in
QCA IEEE 2015

15V59 Quantum Cost Realization of New Reversible Gates with Transformation Based Synthesis
Technique
IEEE 2015

15V60 Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming
IEEE 2015

IEEE 2014 VLSI Projects

Code

Project Title

Year

Downloads

Downloads

WYV62
2014

Design and Estimation of delay, power and area for Parallel prefix adders

WYV63

Detection of Hardware Trojan in SEA Using Path Delay IEEE 2014

IEEE

WYV64
parallel multiplier accumulator Based on radix-2 Modified Booth Algorithm by using a
VLSI architecture
IEEE 2014

WYV65

AreaDelayPower Efficient Carry-Select Adder

IEEE 2014

WYV51

Realization of 2:4 reversible decoder and its applications

WYV52

All Optical Reversible Multiplexer Design using Mach-Zehnder interferometer

IEEE 2014

IEEE

2014

WYV53
2014

Design of Dedicated Reversible Quantum Circuitry for Square Computation

IEEE

WYV54

A High Speed Binary Floating Point Multiplier Using Dadda Algorithm IEEE 2013

WYV55

A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor IEEE 2013

WYV56

Design of high speed hybrid carry select adder

WYV57
2013

Optimized Reversible Vedic Multipliers for High Speed Low Power operations

WYV58

Energy Efficient Code Converters using Reversible Logic Gates IEEE 2013

WYV59
2013

Design of Low Logical Cost Conservative Reversible Adders using Novel PCTG IEEE

WYV60
Logic Gates

Contemplation of Synchronous Gray Code Counter and its Variants using Reversible
IEEE 2013

WYV61

Low power and area efficient carry select adder 2014

IEEE 2013

IEEE

WYV 1
An on-chip AHB bus tracer with real time compression and dynamic multi-resolution
supports for SOC
2014

WYV2 Radix-8 booth encoded modulo multipliers with adoptive delay for high dynamic range Residue
Number System.
2014

WYV3 High throughput DA-based DCT with high accuracy Error compensated Adder Tree.

WYV4 Design of characterization of parallel pre-fix adders using FPGA.

2014

2014

WYV5 Self-immunity technique to improve register file integrity against soft errors.

2014

WYV6 Design and simulation of UART serial communication module based on VHDL. 2014

WYV7 Reducing the computation time in (short bit-width) twos complement multipliers.

WYV8 FPGA Implementation of scalable encryption algorithm. 2014

WYV9 Based on radix-2 modified booth algorithm a new VLSI architecture of parallel multiplier
accumulator
2014

WYV10

LUT optimization for memory-based computation.

2014

WYV11

Hardware implementation of RFID mutual authentication protocol.

2014

WYV12

FPGA implementation of the hummingbird cryptographic Algorithm

2014

WYV13

Implementation of WI-FI MAC layer for transmitter

WYV14
specifications

FPGA implementation of USB transceiver macrocell interface with USB2.0

2014

2014

2014

WYV15

FPGA implementation of SHA-1 algorithm

2014

WYV32

A novel analysis of sequential circuits design using reversible logic

WYV33

Optimized implementation of FFT processor for OFDM systems 2014

WYV34

Finite state machine based vending machine controller with auto-billing 2014

WYV35

Cyclic redundancy check generation using multiple lookup table algorithms

WYV36

The design of high performance barrel integer adder

WYV37

Architectural level power optimization techniques for multipliers

WYV38
2014

Design and minimization of reversible circuits for a data acquisition and storage system

WYV39

Arithmetic & logic unit (ALU) design using reversible control unit

WYV40

A distinguish between reversible and conventional logic gates

2014

WYV41

Design & implementation of MAC unit using reversible logic

2014

2014

2014

2014

2014

WYV42
Modified toffoli gate and its applications in designing components of reversible
arithmetic and logic unit
2014

WYV43

A new reversible design of BCD adder 2014

2014

WYV44

An efficient implementation of floating point multiplier 2014

WYV45

Fault tolerant variable block carry skip logic (VBCSL) using parity Reserving

WYV46

Design of a nanometric reversible 4-bit binary counter with parallel load 2014

WYV47

Introduction to reversible logic gates & its application

WYV48

Design and implementation of APB bridge based on AMBA 4.0 2014

WYV49

A table-based algorithm for pipelined CRC calculation

WYV50

Applying CDMA technique to network-on-chip 2014

2014

2014

2014

Another recent trend in VLSI projects for BE, B Tech and even more suited for ME, M Tech projects are
projects based on soft core processors like NIOS II or Xilinx Microblaze and similar soft core processors.
We at Ingens highly recommend such projects, because they allow the implementation of complex digital
systems with relative ease and hence make for excellent choices for final year projects.