Documente Academic
Documente Profesional
Documente Cultură
Faculty of Engineering
Department of Electrical Communication & Electronic Systems
Engineering
VLSI Design
ECE445
Lab Manual
Table of Contents
Lab#1: Introduction to Xilinx and Modelsim .......................................... 3
Lab#2: Designing a 2x1 Multiplexer in VHDL ..................................... 10
Lab#3: Designing a 2x4 Decoder in VHDL .......................................... 11
Lab#4: Designing a structural Design connecting an ALU to an Encoder
in VHDL .................................................................................................. 12
Lab#5: Designing a 4-bit shift register with parallel load in VHDL ..... 13
Lab#6: Signed Mathematical Block ....................................................... 14
Lab#7: Frequency Divider block as part of a Hierarchal Design .......... 16
Lab#8: 1 Second Count 0-9 Asynchronous Counter on 7-Segment
Display ..................................................................................................... 17
Lab#9: 4*4 Matrix Keypad Interface via MM74C922 Keypad Encoder
................................................................................................................. 18
Page |2
Page |3
Step 3: Name your project a descriptive name, save it into your directory (avoid C:) & click Next
Page |4
Step4: In the wizard shown below, make sure the Family, Device, & Simulator fields are as
shown below:
Page |5
Page |6
Select VHDL Module and choose a descriptive file name i.e. related to your design. The file
name must be the same as the entity of your design. Make sure that the Add to project box is
ticked.
Click Next then choose a suitable Architecture Name then Next then Finish.
Page |7
Proceed with your coding and then follow the below instructions to compile and simulate
your design.
Step1: Select you VHDL file from the top left box in the IDE as shown
Make sure that implementation in the View tab is chosen as seen above.
To compile and synthesize your design, double click on Synthesize XST and wait to see this
sign.
To simulate choose Simulation from the View tab shown in the previous image, the following
will then appear.
Page |8
Select the VHDL file that you want to simulate, expand the Modelsim Simulator shown at the
end of the previous image and double click on Simulate Behavioral Model.
You will then be taken to your simulator that you chose in your project settings at the very
beginning, to start your simulation.
Page |9
P a g e | 10
DEC_IN2
DEC_O3
DEC_O2
DEC_O1
DEC_O0
P a g e | 11
S1 S0
0
0
0
1
1
0
1
1
Others
ALU_O
ALU_IN1 + ALU_IN2
ALU_IN1 - ALU_IN2
ALU_IN1 AND ALU_IN2
ALU_IN1 OR ALU_IN2
XXXXX
P a g e | 12
P a g e | 13
S (SEL)
00
01
10
11
Operation
ALU_IN1 + ALU_IN2
ALU_IN1 - ALU_IN2
ALU_IN2 / 4
ALU_IN1 NOR ALU_IN2
OTHERS
No Operation
P a g e | 14
P a g e | 15
P a g e | 16
P a g e | 17
Suggest an improvement to the design that would make it more reliable and secure.
P a g e | 18