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Features
Flexible Logic Architecture
Three High Current Drivers used for three different LEDs or one RGB LED
LP384
LP640
LP1K
LP4K
LP8K
HX1K
HX4K
HX8K
384
640
1,280
3,520
7,680
1,280
3,520
7,680
16
20
32
16
20
32
32K
64K
80K
128K
64K
80K
128K
11
22
22
11
63
25
95
167
178
95
95
206
12
20
23
11
12
26
Package
16 WLCSP
(1.40 mm x 1.48 mm, 0.35
mm)
Code
SWG16
10(0)1
32 QFN
(5 mm x 5 mm, 0.5 mm)
SG32
21(3)
36 ucBGA
(2.5 mm x 2.5 mm, 0.4 mm)
CM36
25(3)
25(3)1
49 ucBGA
(3 mm x 3 mm, 0.4 mm)
CM49
37(6)
35(5)1
81 ucBGA
(4 mm x 4 mm, 0.4 mm)
CM81
63(8)
81 csBGA
(5 mm x 5 mm, 0.5 mm)
CB81
62(9)1
63(9)2
63(9)2
2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1040 Introduction_01.6
Introduction
iCE40 LP/HX Family Data Sheet
Table 1-1. iCE40 Family Selection Guide (continued)
84 QFN
(7 mm x 7 mm, 0.5 mm)
QN84
100 VQFP
(14 mm x 14 mm, 0.5 mm)
VQ100
121 ucBGA
(5 mm x 5 mm, 0.4 mm)
CM121
95(12)
121 csBGA
(6 mm x 6 mm, 0.5 mm)
CB121
92(12)
132 csBGA
(8 mm x 8 mm, 0.5 mm)
CB132
95(11)
95(12)
144 TQFP
(20 mm x 20 mm, 0.5 mm)
TQ144
96(12)
107(14)
225 ucBGA
(7 mm x 7 mm, 0.4 mm)
CM225
256-ball caBGA
(14 mm x 14 mm, 0.8 mm)
CT256
67(7)1
72(9)1
93(13)
178(23)
93(13)
178(23)
95(12)
178(23)
206(26)
1. No PLL available on the 16 WLCSP, 36 ucBGA, 81 csBGA, 84 QFN and 100 VQFP packages.
2. Only one PLL available on the 81 ucBGA package.
3. High Current I/Os only available on the 16 WLCSP package.
Introduction
The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680
Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded
Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features
allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer
High-Current drivers that are ideal to drive three white LEDs, or one RGB LED.
The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These
features help manage static and dynamic power consumption, resulting in low static power for all members of the
family. The iCE40 devices are available in two versions ultra low power (LP) and high performance (HX) devices.
The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space
saving 1.40x1.48 mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, package
and I/O options, along with other key parameters.
The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a
per-pin basis.
The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can
also configure themselves from external SPI Flash or be configured by an external master such as a CPU.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40
family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use
the synthesis tool output along with the user-specified preferences and constraints to place and route the design in
the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,
licensed free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores as
standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.
1-2
Architecture Overview
The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK PLLs, Nonvolatile Programmable Configuration Memory (NVCM) and blocks of sysMEM Embedded Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 2-1 shows the block diagram of the iCE40LP/HX1K device.
Figure 2-1. iCE40LP/HX1K Device, Top View
Programmable
Logic Block (PLB)
I/O Bank 0
I/O Bank 1
PLB
PLB
PLB
PLB
Programmable Interconnect
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
4 kbit RAM
4 kbit RAM
PLB
PLB
PLB
PLB
PLB
Programmable Interconnect
PLB
I/O Bank 3
Programmable Interconnect
PLL
NVCM
SPI
Bank
I/O Bank 2
Non-volatile
Configuration Memory
(NVCM)
Phase-Locked
Loop
Carry Logic
4-Input Look-up
Table (LUT4)
The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional
grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the
periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register
functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of
interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The
place and route software tool automatically allocates these routing resources.
In the iCE40 family, there are up to four independent sysIO banks. Note on some packages VCCIO banks are tied
together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this
document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as
RAM, ROM or FIFO.
The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the
clocks.
Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40
includes on-chip, Nonvolatile Configuration Memory (NVCM).
2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1040 Architecture_01.3
Architecture
iCE40 LP/HX Family Data Sheet
PLB Blocks
The core of the iCE40 device consists of Programmable Logic Blocks (PLB) which can be programmed to perform
logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 2-2.
Each LC contains one LUT and one register.
Figure 2-2. PLB Block Diagram
Shared Block-Level Controls
Clock
Programmable Logic
Block (PLB)
Enable
FCOUT
1
Set/Reset
0
Logic Cell
Carry Logic
DFF
8 Logic Cells (LCs)
I0
O
Q
EN
I1
LUT4
I2
SR
I3
FCIN
Four-input
Look-Up Table
(LUT4)
Flip-flop with
optional enable and
set or reset controls
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 2-2.
A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, requiring up to
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUT4s to create wider logic functions.
A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following
device configuration.
Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,
comparators, binary counters and some wide, cascaded logic functions.
Table 2-1. Logic Cell Signal Descriptions
Function
Type
Input
Data signal
Input
Control signal
Signal Names
I0, I1, I2, I3
Enable
Description
Inputs to LUT4
Clock enable shared by all LCs in the PLB
Input
Control signal
Set/Reset1
Input
Control signal
Clock
Input
Inter-PLB signal
FCIN
Fast carry in
Output
Data signals
Output
Inter-PFU signal
O
FCOUT
1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
2-2
Architecture
iCE40 LP/HX Family Data Sheet
Routing
There are many resources provided in the iCE40 devices to route signals individually with related control signals.
The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4
(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient
connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
Clock
Clock Enable
GBUF0
Yes
Yes
GBUF1
Yes
GBUF2
Yes
GBUF3
Yes
GBUF4
LUT Inputs
Yes, any 4 of 8
GBUF Inputs
Yes
GBUF5
Yes
GBUF6
Yes
GBUF7
Yes
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
The maximum frequency for the global buffers are shown in the iCE40 External Switching Characteristics tables
later in this document.
Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 device. This GHIZ signal is
automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance
state.
2-3
Architecture
iCE40 LP/HX Family Data Sheet
Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 device. The global reset signal is
automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For
PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.
REFERENCECLK
DIVR
Phase
Detector
Input
Divider
RANGE
Low-Pass
Filter
DIVQ
Voltage
Controlled
Oscillator
(VCO)
VCO
Divider
SIMPLE
DIVF
PLLOUTCORE
Feedback
Divider
Fine Delay
Adjustment
Feedback
Phase
Shifter
Fine Delay
Adjustment
Output Port
PLLOUTGLOBAL
Feedback_Path
LOCK
DYNAMICDELAY[7:0]
EXTFEEDBACK
LATCHINPUTVALUE
EXTERNAL
Low Power mode
(iCEgate enabled)
2-4
Architecture
iCE40 LP/HX Family Data Sheet
Table 2-3. PLL Signal Descriptions
Signal Name
REFERENCECLK
Direction
Input
Description
Input reference clock
When FEEDBACK_PATH is set to SIMPLE, the BYPASS control selects which clock signal connects to the PLLOUT output.
BYPASS
Input
EXTFEEDBACK
Input
External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set to
EXTERNAL.
DYNAMICDELAY[3:0]
Input
LATCHINPUTVALUE
Input
When enabled, forces the PLL into low-power mode; PLL output is held static at the last
input clock value. Set ENABLE ICEGATE_PORTA and PORTB to 1 to enable.
PLLOUTGLOBAL
Output
Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA.
The port has optimal connections to global clock buffers GBUF4 and GBUF5.
PLLOUTCORE
Output
Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the
PLLOUTLGOBAL port.
LOCK
Output
When High, indicates that the PLL output is phase aligned or locked to the input reference clock.
RESET
Input
WADDR Port
Size (Bits)
WDATA Port
Size (Bits)
RADDR Port
Size (Bits)
RDATA Port
Size (Bits)
MASK Port
Size (Bits)
SB_RAM256x16
SB_RAM256x16NR
SB_RAM256x16NW
SB_RAM256x16NRNW
256x16 (4K)
8 [7:0]
16 [15:0]
8 [7:0]
16 [15:0]
16 [15:0]
SB_RAM512x8
SB_RAM512x8NR
SB_RAM512x8NW
SB_RAM512x8NRNW
512x8 (4K)
9 [8:0]
8 [7:0]
9 [8:0]
8 [7:0]
No Mask Port
SB_RAM1024x4
SB_RAM1024x4NR
SB_RAM1024x4NW
SB_RAM1024x4NRNW
1024x4 (4K)
10 [9:0]
4 [3:0]
10 [9:0]
4 [3:0]
No Mask Port
SB_RAM2048x2
SB_RAM2048x2NR
SB_RAM2048x2NW
SB_RAM2048x2NRNW
2048x2 (4K)
11 [10:0]
2 [1:0]
11 [10:0]
2 [1:0]
No Mask Port
Block RAM
Configuration
1. For iCE40 EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a N and a R or W
depending on the clock that is affected.
2-5
Architecture
iCE40 LP/HX Family Data Sheet
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Note the sysMEM Embedded Block RAM Memory address 0 cannot be initialized.
Memory Cascading
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
RAM4k Block
Figure 2-4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array.
Figure 2-4. sysMEM Memory Primitives
Write Port
Read Port
WDATA[15:0]
RDATA[15:0]
MASK[15:0]
RADDR[7:0]
WADDR[7:0]
WE
RAM4K
RAM Block
(256x16)
RE
WCLKE
RCLKE
WCLK
RCLK
Direction
Description
WDATA[15:0]
Input
MASK[15:0]
Input
WADDR[7:0]
Input
WE
Input
WCLKE
Input
WCLK
Input
RDATA[15:0]
Output
RADDR[7:0]
Input
RE
Input
RCLKE
Input
RCLK
Input
For further information on the sysMEM EBR block, please refer to TN1250, Memory Usage Guide for iCE40 Devices.
2-6
Architecture
iCE40 LP/HX Family Data Sheet
sysIO
Buffer Banks
iCE40 devices have up to four I/O banks with independent VCCIO rails with an additional configuration bank
VCC_SPI for the SPI I/Os.
Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysIO buffers and pads. The PIOs are placed on all four sides of the device.
Figure 2-5. I/O Bank and Programmable I/O Cell
VCCIO
I/O Bank 0, 1, 2, or 3
Voltage Supply
Enabled 1
Disabled 0
VCC
Internal Core
0 = Hi-Z
1 = Output
Enabled
Pull-up
OE
VCCIO_0
Pull-up
Enable
OUTCLK
I/O Bank 0
General-Purpose I/O
I/O Bank 2
General-Purpose I/O
VCCIO_2
OUT
PAD
OUTCLK
VCCIO_1
I/O Bank 1
General-Purpose I/O
I/O Bank 3
Special/LVDS I/O
VCCIO_3
PIO
iCEGATE
HOLD
HD
Latch inhibits
switching for
lowest power
IN
IN
INCLK
SPI
Bank
Programmable Input/Output
VCC_SPI
The PIO contains three blocks: an input register block, output register block iCEgate and tri-state register block.
To save power, the optional iCEgateTM latch can selectively freeze the state of individual, non-registered inputs
within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of
modes along with the necessary clock and selection logic.
Input Register Block
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the
data on the positive and negative edges of the system clock signal, creating two data streams.
Output Register Block
The output register block can optionally register signals from the core of the device before they are passed to the
sysIO buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge
of the system clock and then muxed creating one data stream.
Figure 2-6 shows the input/output register block for the PIOs.
2-7
Architecture
iCE40 LP/HX Family Data Sheet
Figure 2-6. iCE I/O Register Block Diagram
PIO Pair
CLOCK_ENABLE
OUTPUT_CLK
INPUT_CLK
(1,0)
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
Pad
D_OUT_1
D_OUT_0
(1,0)
0
1
OUTPUT_ENABLE
(1,0)
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
Pad
D_OUT_1
D_OUT_0
(1,0)
0
1
OUTPUT_ENABLE
I/O Type
Input
Description
Output register clock
CLOCK_ENABLE
Input
Clock enable
INPUT_CLK
Input
OUTPUT_ENABLE
Input
Output enable
D_OUT_0/1
Input
D_IN_0/1
LATCH_INPUT_VALUE
Output
Input
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of
standards that are found in todays systems including LVCMOS and LVDS25.
High Current LED Drivers combine three sysIO buffers together. This allows for programmable drive strength. This
also allows for high current drivers that are ideal to drive three white LEDs, or one RGB LED. Each bank is capable
of supporting multiple I/O standards including single-ended LVCMOS buffers and differential LVDS25E output buf2-8
Architecture
iCE40 LP/HX Family Data Sheet
fers. Bank 3 additionally supports differential LVDS25 input buffers. Each sysIO bank has its own dedicated power
supply.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO_2, VPP_2V5, and VCC_SPI have reached
the level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data
sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the users responsibility to
ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all
the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins will maintain the pre-configuration state until VCC and
VCCIO (for I/O banks containing configuration I/Os) have reached levels, at which time the I/Os will take on the software user-configured settings only after a proper download/configuration. Unused IOs are automatically blocked
and the pullup termination is disabled.
Supported Standards
The iCE40 sysIO buffer supports both single-ended and differential input standards. The single-ended standard
supported is LVCMOS. The buffer supports the LVCMOS 1.8, 2.5, and 3.3 V standards. The buffer has individually
configurable options for bus maintenance (weak pull-up or none). The High Current output buffer have individually
configurable options for drive strength.
Table 2-7 and Table 2-8 show the I/O standards (together with their supply and reference voltages) supported by
the iCE40 devices.
Table 2-7. Supported Input Standards
Input Standard
VCCIO (Typical)
3.3 V
2.5 V
1.8 V
Single-Ended Interfaces
LVCMOS33
Yes
LVCMOS25
Yes
LVCMOS18
Yes
Differential Interfaces
LVDS251
Yes
subLVDS1
Yes
1. Bank 3 only.
VCCIO (Typical)
Single-Ended Interfaces
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
Differential Interfaces
LVDS25E1
2.5
subLVDSE1
1.8
Architecture
iCE40 LP/HX Family Data Sheet
Power On Reset
iCE40 devices have power-on reset circuitry to monitor VCC, VCCIO_2, VPP_2V5, and VCC_SPI voltage levels during
power-up and operation. At power-up, the POR circuitry monitors VCC, VCCIO_2, VPP_2V5, and VCC_SPI (controls
configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after
reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to
user functionality once the device has finished configuration.
Feature Description
PLL
When LATCHINPUTVALUE is enabled, forces the PLL into low-power mode; PLL output held static
at last input clock value.
iCEGate
To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or
clock-enable control.
2-10
VPP_2V5
Parameter
Core Supply Voltage
VPP_2V5 NVCM Programming and
Operating Supply Voltage
Min.
Max.
Units
1.14
1.26
1.71
3.46
2.30
3.46
2.30
3.46
NVCM Programming
2.30
3.00
VPP_FAST4
N/A
N/A
VCCPLL5, 6
1.14
1.26
VCCIO1, 2, 3
VCCIO0-3
1.71
3.46
VCC_SPI
1.71
3.46
tJIND
40
100
tPROG
10
30
1. Like power supplies must be tied together. For example, if VCCIO and VCC_SPI are both the same voltage, they must also be the same supply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
5. No PLL available on the iCE40LP384 and iCE40LP640 device.
6. VCCPLL is tied to VCC internally in packages without PLLs pins.
2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
3-1
tRAMP
Parameter
Min.
Max.
Units
0.40
10
V/ms
0.01
10
V/ms
0.01
10
V/ms
0.01
10
V/ms
Device
iCE40LP384
iCE40LP640,
iCE40LP/HX1K,
iCE40LP/HX4K,
iCE40LP/HX8K
VPORDN
iCE40LP384
iCE40LP640,
iCE40LP/HX1K,
iCE40LP/HX4K,
iCE40LP/HX8K
Parameter
Min.
Max.
Units
0.67
0.99
0.70
1.59
0.70
1.59
0.70
1.59
0.55
0.75
0.86
1.29
0.86
1.29
0.86
1.33
0.64
1.59
1.59
1.59
0.75
1.29
1.29
1.33
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
ESD Performance
Please refer to the iCE40 Product Family Qualification Summary for complete qualification data, including ESD performance.
3-2
DC Electrical Characteristics
Over Recommended Operating Conditions
Parameter
Condition
Min.
Typ.
Max.
Units
Symbol
+/10
I/O Capacitance2
pf
C26, 7
pf
VHYST
Input Hysteresis
200
mV
IPU6, 7
3
8
11
31
72
128
C1
6, 7
A
A
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Internal pull-up resistors are disabled.
2. TJ 25C, f = 1.0 MHz.
3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
4. Only applies to IOs in the SPI bank following configuration.
5. Some products are clamped to a diode when VIN is larger than VCCIO.
6. High current IOs has three sysIO buffers connected together.
7. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysIO buffer are connected together.
Parameter
Device
iCE40LP384
ICC
Typ. VCC4
Units
21
iCE40LP640
100
iCE40LP1K
100
iCE40LP4K
250
iCE40LP8K
250
ICCPLL5, 6
All devices
0.5
IPP_2V5
All devices
1.0
ICCIO, ICC_SPI
All devices
3.5
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO
or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 C, power supplies at nominal voltage.
4. Does not include pull-up.
5. No PLL available on the iCE40LP384 and iCE40LP640 device.
6. VCCPLL is tied to VCC internally in packages without PLLs pins.
3-3
Parameter
Device
iCE40HX1K
ICC
Typ. VCC4
Units
296
iCE40HX4K
1140
iCE40HX8K
1140
ICCPLL5
All devices
0.5
IPP_2V5
All devices
1.0
ICCIO, ICC_SPI
All devices
3.5
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO
or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 C, power supplies at nominal voltage.
4. Does not include pull-up.
5. VCCPLL is tied to VCC internally in packages without PLLs pins.
ICC
ICCPLL
6, 7
Typ. VCC5
Units
iCE40LP384
60
iCE40LP640
120
iCE40LP1K
120
iCE40LP4K
350
iCE40LP8K
350
All devices
0.5
Parameter
Device
IPP_2V5
All devices
2.5
mA
ICCIO8, ICC_SPI
All devices
3.5
mA
1.
2.
3.
4.
5.
6.
7.
8.
Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
Typical user pattern.
SPI programming is at 8 MHz.
TJ = 25 C, power supplies at nominal voltage.
Per bank. VCCIO = 2.5 V. Does not include pull-up.
No PLL available on the iCE40-LP384 and iCE40-LP640 device.
VCCPLL is tied to VCC internally in packages without PLLs pins.
VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
3-4
Units
iCE40HX1K
278
iCE40HX4K
1174
iCE40HX8K
1174
Device
Typ. VCC5
Parameter
All devices
0.5
IPP_2V5
All devices
2.5
mA
ICCIO7, ICC_SPI
All devices
3.5
mA
1.
2.
3.
4.
5.
6.
7.
Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
Typical user pattern.
SPI programming is at 8 MHz.
TJ = 25 C, power supplies at nominal voltage.
Per bank. VCCIO = 2.5 V. Does not include pull-up.
VCCPLL is tied to VCC internally in packages without PLLs pins.
VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications.
ICCPEAK
ICCPLLPEAK1, 2, 4
IPP_2V5PEAK
IPP_FASTPEAK3
ICCIOPEAK5, ICC_SPIPEAK
Parameter
Device
Max
Units
iCE40LP384
7.7
mA
mA
iCELP640
6.4
iCE40LP1K
6.4
mA
iCE40LP4K
15.7
mA
iCE40LP8K
15.7
mA
iCE40LP1K
1.5
mA
iCELP640
1.5
mA
iCE40LP4K
8.0
mA
iCE40LP8K
8.0
mA
iCE40LP384
3.0
mA
iCELP640
7.7
mA
iCE40LP1K
7.7
mA
iCE40LP4K
4.2
mA
iCE40LP8K
4.2
mA
iCE40LP384
5.7
mA
iCELP640
8.1
mA
iCE40LP1K
8.1
mA
iCE40LP384
8.4
mA
iCELP640
3.3
mA
iCE40LP1K
3.3
mA
iCE40LP4K
8.2
mA
iCE40LP8K
8.2
mA
3-5
Parameter
ICCPEAK
ICCPLLPEAK1
IPP_2V5PEAK
ICCIOPEAK, ICC_SPIPEAK
Device
Max
Units
iCE40HX1K
6.9
mA
iCE40HX4K
22.3
mA
iCE40HX8K
22.3
mA
iCE40HX1K
1.8
mA
iCE40HX4K
6.4
mA
iCE40HX8K
6.4
mA
iCE40HX1K
2.8
mA
iCE40HX4K
4.1
mA
iCE40HX8K
4.1
mA
iCE40HX1K
6.8
mA
iCE40HX4K
6.8
mA
iCE40HX8K
6.8
mA
Standard
Typ.
Max.
LVCMOS 3.3
3.14
3.3
3.46
LVCMOS 2.5
2.37
2.5
2.62
LVCMOS 1.8
1.71
1.8
1.89
LVDS25E
2.37
2.5
2.62
subLVDSE1, 2
1.71
1.8
1.89
1, 2
1. Inputs on-chip. Outputs are implemented with the addition of external resistors.
2. Does not apply to Configuration Bank VCC_SPI.
VIH1
VIL
Min. (V)
Max. (V)
Min. (V)
Max. (V)
0.3
0.8
2.0
VCCIO + 0.2 V
0.3
0.3
0.7
0.35VCCIO
1.7
0.65VCCIO
VCCIO + 0.2 V
VCCIO + 0.2 V
1. Some products are clamped to a diode when VIN is larger than VCCIO.
2. Only for High Drive LED outputs.
3-6
VOL Max.
(V)
VOH Min.
(V)
IOL Max.
(mA)
IOH Max. (mA)
0.4
0.2
VCCIO 0.2
0.4
0.1
0.2
VCCIO 0.2
0.1
0.4
VCCIO 0.4
4, 82, 122
0.2
VCCIO 0.2
0.1
0.1
0.1
4, 82, 122
0.1
LVDS25
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
VINP, VINM
Input Voltage
Min.
Typ.
Max.
Units
VCCIO1 = 2.5
Test Conditions
2.5
250
350
450
mV
(VCCIO/2) - 0.3
VCCIO/2
(VCCIO/2) + 0.3
10
Min.
Typ.
Max.
Units
1.8
100
150
200
mV
VTHD
VCM
VCCIO1 = 2.5
IIN
Input Current
Power on
1. Typical.
subLVDS
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
VINP, VINM
Input Voltage
Test Conditions
VCCIO1 = 1.8
VTHD
VCM
VCCIO1 = 1.8
IIN
Input Current
Power on
10
1. Typical.
3-7
V
A
LVDS25E Emulation
iCE40 devices can support LVDSE outputs via emulation on all banks. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in
Figure 3-1 is one possible solution for LVDS25E standard implementation. Resistor values in Figure 3-1 are industry standard values for 1% resistors.
Figure 3-1. LVDS25E Using External Resistors
VCCIO
Rs 1%
Rs
Rp
Differential
output voltage
V OD
50%
V OUT_A
V OCM
Differential
Output Pair
GND
Description
Typ.
Units
ZOUT
Output impedance
20
Ohms
RS
150
Ohms
RP
140
Ohms
RT
Receiver termination
100
Ohms
VOH
1.43
VOL
1.07
VOD
0.30
VCM
1.25
ZBACK
Back impedance
100.5
Ohms
IDC
DC output current
6.03
mA
3-8
SubLVDS Emulation
The iCE40 family supports the differential subLVDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The subLVDS input standard is supported by the LVDS25 differential input buffer. The scheme shown in Figure 3-2 is one
possible solution for subLVDSE output standard implementation. Use LVDS25E mode with suggested resistors for
subLVDSE operation. Resistor values in Figure 3-2 are industry standard values for 1% resistors.
Figure 3-2. subLVDSE
VCCIO
Rs 1%
Rp
Rs
Differential
output voltage
V OD
50%
V OUT_A
V OCM
Differential
Output Pair
GND
Description
Typ.
Units
20
Ohms
270
Ohms
120
Ohms
Receiver termination
100
Ohms
1.43
ZOUT
Output impedance
RS
RP
RT
VOH
VOL
1.07
VOD
0.35
VCM
0.9
ZBACK
Back impedance
100.5
Ohms
IDC
DC output current
2.8
mA
3-9
Timing
Units
16-bit decoder
11.0
ns
4:1 MUX
12.0
ns
16:1 MUX
13.0
ns
Timing
Units
Basic Functions
Register-to-Register Performance
Function
Basic Functions
16:1 MUX
190
MHz
16-bit adder
160
MHz
16-bit counter
175
MHz
64-bit counter
65
MHz
240
MHz
1. The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with
device and tool version. The tool uses internal parameters that have been characterized but are not tested on
every device.
2. Using a VCC of 1.14 V at Junction Temp 85 C.
Timing
Units
16-bit decoder
10.0
ns
4:1 MUX
9.0
ns
16:1 MUX
9.5
ns
Timing
Units
Basic Functions
Register-to-Register Performance
Function
Basic Functions
16:1 MUX
305
MHz
16-bit adder
220
MHz
16-bit counter
255
MHz
64-bit counter
105
MHz
403
MHz
1. The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with
device and tool version. The tool uses internal parameters that have been characterized but are not tested on
every device.
2. Using a VCC of 1.14 V at Junction Temp 85 C.
3-10
Max. Speed
Units
Inputs
LVDS251
400
1
MHz
subLVDS18
400
MHz
LVCMOS33
250
MHz
LVCMOS25
250
MHz
LVCMOS18
250
MHz
LVDS25E
250
MHz
subLVDS18E
155
MHz
LVCMOS33
250
MHz
LVCMOS25
250
MHz
LVCMOS18
155
MHz
Outputs
Description
Timing
Units
Input Adjusters
LVDS25
0.18
ns
subLVDS
0.82
ns
LVCMOS33
0.18
ns
LVCMOS25
0.00
ns
LVCMOS18
0.19
ns
Output Adjusters
LVDS25E
0.00
ns
subLVDSE
1.32
ns
LVCMOS33
0.12
ns
LVCMOS25
0.00
ns
LVCMOS18
1.32
ns
1.
2.
3.
4.
5.
Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
LVCMOS timing measured with the load specified in Switching Test Condition table.
All other standards tested according to the appropriate specifications.
Commercial timing numbers are shown.
Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
3-11
Description
Timing
Units
Input Adjusters
LVDS25
0.13
ns
subLVDS
1.03
ns
LVCMOS33
0.16
ns
LVCMOS25
0.00
ns
LVCMOS18
0.23
ns
ns
Output Adjusters
LVDS25E
0.00
subLVDSE
1.76
ns
LVCMOS33
0.17
ns
LVCMOS25
0.00
ns
LVCMOS18
1.76
ns
1.
2.
3.
4.
5.
Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
LVCMOS timing measured with the load specified in Switching Test Condition table.
All other standards tested according to the appropriate specifications.
Commercial timing numbers are shown.
Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
3-12
Description
Device
Min.
Max.
Units
275
MHz
Clocks
Global Clocks
fMAX_GBUF
tW_GBUF
tSKEW_GBUF
0.92
ns
iCE40LP384
370
ps
iCE40LP640
230
ps
iCE40LP1K
230
ps
iCE40LP4K
340
ps
iCE40LP8K
340
ps
9.36
ns
iCE40LP384
300
ps
iCE40LP640
200
ps
iCE40LP1K
200
ps
iCE40LP4K
280
ps
General I/O Pin Parameters (Using Global Buffer Clock without PLL)
tSKEW_IO
tCO
iCE40LP8K
280
ps
iCE40LP384
6.33
ns
iCE40LP640
5.91
ns
iCE40LP1K
5.91
ns
iCE40LP4K
6.58
ns
iCE40LP8K
6.58
ns
iCE40LP384
ns
ns
ns
ns
iCE40LP8K
0.08
0.33
0.33
0.63
0.63
ns
iCE40LP384
1.99
ns
iCE40LP640
2.81
ns
iCE40LP1K
2.81
ns
iCE40LP4K
3.48
ns
iCE40LP8K
3.48
ns
iCE40LP1K
2.20
ns
iCE40LP4K
2.30
ns
iCE40LP8K
2.30
ns
iCE40LP1K
5.23
ns
iCE40LP4K
6.13
ns
iCE40LP8K
6.13
ns
iCE40LP640
tSU
iCE40LP1K
iCE40LP4K
tH
General I/O Pin Parameters (Using Global Buffer Clock with PLL)
tCOPLL
tSUPLL
3-13
Description
Device
iCE40LP1K
tHPLL
iCE40LP4K
iCE40LP8K
Min.
Max.
Units
0.90
0.80
0.80
ns
ns
ns
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 C and 1.14 V. Other
operating conditions can be extracted from the iCECube2 software.
2. General I/O timing numbers based on LVCMOS 2.5, 0pf load.
3. Supported on devices with a PLL.
3-14
Description
Device
Min.
Max.
Units
275
MHz
Clocks
Primary Clocks
fMAX_GBUF
tW_GBUF
tSKEW_GBUF
0.88
ns
iCE40HX1K
727
ps
300
ps
iCE40HX8K
300
ps
7.30
ns
iCE40HX1K
696
ps
iCE40HX4K
290
ps
General I/O Pin Parameters (Using Global Buffer Clock without PLL)
tSKEW_IO
tCO
tSU
tH
iCE40HX8K
290
ps
iCE40HX1K
5.00
ns
iCE40HX4K
5.41
ns
iCE40HX8K
5.41
ns
iCE40HX1K
ns
ns
iCE40HX8K
0.23
0.43
0.43
ns
iCE40HX1K
1.92
ns
iCE40HX4K
2.38
ns
iCE40HX8K
2.38
ns
iCE40HX1K
2.96
ns
iCE40HX4K
2.51
ns
iCE40HX8K
2.51
ns
iCE40HX1K
3.10
ns
iCE40HX4K
4.16
ns
iCE40HX8K
4.16
ns
iCE40HX1K
0.60
0.53
0.53
ns
ns
ns
iCE40HX4K
General I/O Pin Parameters (Using Global Buffer Clock with PLL)
tCOPLL
tSUPLL
tHPLL
iCE40HX4K
iCE40HX8K
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 C and 1.14 V. Other
operating conditions, including industrial, can be extracted from the iCECube2 software.
2. General I/O timing numbers based on LVCMOS 2.5, 0pf load.
3. Supported on devices with a PLL.
3-15
Min.
Max.
Units
fIN
Descriptions
Conditions
10
133
MHz
fOUT
16
275
MHz
fVCO
533
1066
MHz
fPFD
10
133
MHz
AC Characteristics
tDT
tPH
tOPJIT1, 5
40
50
35
65
"%
+/12
deg
ps p-p
450
0.05
UIPP
750
ps p-p
0.10
UIPP
275
ps p-p
0.05
UIPP
At 90% or 10%
1.3
ns
tW
tLOCK2, 3
50
us
tUNLOCK
50
ns
tIPJIT4
fPFD 20 MHz
1000
ps p-p
0.02
UIPP
tFDTAP
147
195
ps
500
ns
tSTABLE
tSTABLE_PW3
100
ns
tRST
10
ns
tRSTREC
10
us
VCO
Cycles
tDYNAMIC_WD
tPDBYPASS
100
iCE40LP
1.18
4.68
ns
iCE40HX
1.73
4.07
ns
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over
1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table.
5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise.
3-16
tCONFIG
Parameter
POR/CRESET_B to
Device I/O Active
Typ.
Units
Conditions
25
ms
15
ms
11
ms
53
ms
25
ms
13
ms
53
ms
25
ms
13
ms
230
ms
110
ms
70
ms
230
ms
110
ms
70
ms
1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.
2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.
3-17
Parameter
Min.
Typ.
Max.
Units
200
ns
tCRESET_B
49
tDONE_IO
Clock
Cycles
iCE40LP384
600
800
us
iCE40LP640,
iCE40LP/HX1K
iCE40LP/HX4K
1200
us
iCE40LP/HX8K
Slave SPI
tCR_SCK
us
1200
Write
25
MHz
Read iCE40LP3842
15
MHz
Read iCE40LP640,
iCE40LP/HX1K2
15
MHz
Read iCE40LP/
HX4K2
15
MHz
Read iCE40LP/
HX8K2
15
MHz
20
ns
tCCLKL
20
12
tSTH
12
tSTCO
13
ns
tSTSU
MHz
MHz
fMAX
tCCLKH
us
ns
ns
ns
Master SPI
Off
fMCLK
Low Frequency
(Default)
Medium Frequency3
High Frequency3
3-18
0
7.5
24
40
MHz
MHz
tMCLK
Parameter
Min.
Typ.
Max.
Units
iCE40LP384 - Low
Frequency (Default)
600
us
600
us
iCE40LP384 - High
Frequency
600
us
iCE40LP640,
iCE40LP/HX1K Low Frequency
(Default)
800
us
iCE40LP640,
iCE40LP/HX1K Medium Frequency
800
us
iCE40LP640,
iCE40LP/HX1K High Frequency
800
us
iCE40LP/HX1K -Low
Frequency (Default)
800
us
800
us
800
us
1200
us
1200
us
1200
us
1200
us
1200
us
1200
us
3-19
VT
R1
DUT
Test Poi nt
CL
R1
CL
0 pF
Timing Reference
VT
1.5
VOL
1.5
VOH
188
0 pF
VCCIO/2
VOL
VCCIO/2
VOH
LVCMOS (H -> Z)
VOH - 0.15
VOL
LVCMOS (L -> Z)
VOL - 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-20
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
IO[Bank]_[Row/Column
Number][A/B]
I/O
[Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number on the device.
IO[Bank]_[Row/Column
Number][A/B]
I/O
[Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number on the device.
[A/B] indicates the differential I/O. 'A' = negative input. 'B' = positive input.
HCIO[Bank]_[Number]
I/O
High Current IO. [Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number.
NC
No connect
GND
GND Ground. Dedicated pins. It is recommended that all GNDs are tied together.
VCC
VCC The power supply pins for core logic. Dedicated pins. It is recommended that
all VCCs are tied to the same supply.
VCCIO_x
VCCIO The power supply pins for I/O Bank x. Dedicated pins. All VCCIOs located
in the same bank are tied to the same supply.
PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
VCCPLLx
PLL VCC Power. Dedicated pins. The PLL requires a separate power and ground
that is quiet and stable to reduce the output clock jitter of the PLL.
GNDPLLx
PLL GND Ground. Dedicated pins. The sysCLOCK PLL has the DC ground connection made on the FPGA, so the external PLL ground connection (GNDPLL) must
NOT be connected to the boards ground.
GBINx
I/O
Dual function pins. I/Os when not used as CBSEL. Optional ColdBoot configuration
SELect input, if ColdBoot mode is enabled.
CRESET_B
Configuration Reset, active Low. Dedicated input. No internal pull-up resistor. Either
actively drive externally or connect a 10 KOhm pull-up resistor to VCCIO_2.
CDONE
I/O
Configuration Done. Includes a permanent weak pull-up resistor to VCCIO_2. If driving external devices with CDONE output, an external pull-up resistor to VCCIO_2
may be required. Refer to the TN1248, iCE40 Programming and Configuration for
more details. Following device configuration the iCE40LP640 and iCE40LP1K in the
SWG16 package CDONE pin can be used as a user output.
VCC_SPI
SPI interface voltage supply input. Must have a valid voltage even if configuring from
NVCM.
SPI_SCK
I/O
Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration Clock for configuring an FPGA configuration modes.
SPI_SS_B
I/O
SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to VCC_SPI
during configuration. During configuration, the logic level sampled on this pin determines the configuration mode used by the iCE40 device. An input when sampled at
the start of configuration. An input when in SPI Peripheral configuration mode
(SPI_SS_B = Low). An output when in Master SPI Flash configuration mode.
SPI_SI
I/O
Slave SPI serial data input and master SPI serial data output
SPI_SO
I/O
Slave SPI serial data output and master SPI serial data input
2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
Pinout Information
iCE40 LP/HX Family Data Sheet
I/O
Descriptions
VPP_FAST
Optional fast NVCM programming supply. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and
CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
VPP_2V5
4-2
Pinout Information
iCE40 LP/HX Family Data Sheet
iCE40LP640
iCE40LP1K
SG32
CM362
CM492
SWG16
Bank 0
10
Bank 1
Bank 2
CM81
CB81
QN84
CM121
CB121
10
17
17
17
24
24
15
16
17
25
21
11
11
18
19
12
10
16
17
18
24
24
Configuration
Bank 3
21
25
37
10
10
25
35
63
62
67
95
92
Bank 0
Bank 1
Bank 2
Bank 3
Bank 0
Bank 1
Bank 2
Bank 3
12
12
12
12
Bank 0
Bank 1
Bank 2
Bank 3
Configuration
Bank 0
Bank 1
Bank 2
Bank 3
Vccio Pins
VCC
VCC_SPI
VPP_2V5
VPP_FAST3
VCCPLL
GND
11
NC
32
36
49
16
16
36
49
81
81
84
121
121
4-3
Pinout Information
iCE40 LP/HX Family Data Sheet
iCE40LP8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
CM121
CM225
CM81
CM121
CM225
VQ100
CB132
TQ144
CB132
TQ144
CB132
CM225
CT256
52
17
23
46
17
23
46
19
24
23
24
27
24
46
Bank 1
15
21
42
15
21
42
19
25
25
25
29
25
42
52
Bank 2
19
40
19
40
12
20
20
18
19
18
40
46
Bank 3
18
26
46
18
26
46
18
22
24
24
28
24
46
52
Configuration
63
93
178
63
93
178
72
95
96
95
107
95
178
206
Bank 1
Bank 2
Bank 3
Bank 0
Bank 1
Bank 2
Bank 3
13
23
13
23
11
12
12
14
12
23
26
13
23
13
23
11
12
12
14
12
23
26
Bank 0
Bank 1
Bank 2
Bank 3
Configuration
Bank 0
Bank 1
Bank 2
Bank 3
VCC
VCC_SPI
VPP_2V5
VPP_FAST1
VCCPLL
GND
12
18
12
18
10
14
10
15
11
15
18
20
NC
19
81
121
225
81
121
225
100
132
144
132
144
132
225
256
Vccio Pins
1. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications.
4-4
Shipping Method
TR = Tape and Reel
TR50 = Tape and Reel 50 units
TR1K = Tape and Reel 1,000 units
iCE40 FPGA
Series
LP = Low Power Series
Package
Logic Cells
Package
iCE40 mobileFPGA
CB132
CM225
CT256
TQ144
VQ100
Series
HX = High-Performance Series
Logic Cells
1K = 1,280 Logic Cells
4K = 3,520 Logic Cells
8K = 7,680 Logic Cells
Ordering Information
iCE40 devices have top-side markings as shown below:
Industrial
iCE40HX8K
CM225
Datecode
2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
5-1
Ordering Information
iCE40 LP/HX Family Data Sheet
Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging
LUTs
Supply Voltage
Leads
Temp.
ICE40LP384-CM36
Part Number
384
1.2 V
Halogen-Free ucBGA
Package
36
IND
ICE40LP384-CM36TR
384
1.2 V
Halogen-Free ucBGA
36
IND
ICE40LP384-CM36TR1K
384
1.2 V
Halogen-Free ucBGA
36
IND
ICE40LP384-CM49
384
1.2 V
Halogen-Free ucBGA
49
IND
ICE40LP384-CM49TR
384
1.2 V
Halogen-Free ucBGA
49
IND
ICE40LP384-CM49TR1K
384
1.2 V
Halogen-Free ucBGA
49
IND
ICE40LP384-SG32
384
1.2 V
Halogen-Free QFN
32
IND
ICE40LP384-SG32TR
384
1.2 V
Halogen-Free QFN
32
IND
ICE40LP384-SG32TR1K
384
1.2 V
Halogen-Free QFN
32
IND
ICE40LP640-SWG16TR
640
1.2 V
Halogen-Free WLCSP
16
IND
ICE40LP640-SWG16TR50
640
1.2 V
Halogen-Free WLCSP
16
IND
ICE40LP640-SWG16TR1K
640
1.2 V
Halogen-Free WLCSP
16
IND
ICE40LP1K-SWG16TR
1280
1.2 V
Halogen-Free WLCSP
16
IND
ICE40LP1K-SWG16TR50
1280
1.2 V
Halogen-Free WLCSP
16
IND
ICE40LP1K-SWG16TR1K
1280
1.2 V
Halogen-Free WLCSP
16
IND
ICE40LP1K-CM36
1280
1.2 V
Halogen-Free ucBGA
36
IND
ICE40LP1K-CM36TR
1280
1.2 V
Halogen-Free ucBGA
36
IND
ICE40LP1K-CM36TR1K
1280
1.2 V
Halogen-Free ucBGA
36
IND
ICE40LP1K-CM49
1280
1.2 V
Halogen-Free ucBGA
49
IND
ICE40LP1K-CM49TR
1280
1.2 V
Halogen-Free ucBGA
49
IND
ICE40LP1K-CM49TR1K
1280
1.2 V
Halogen-Free ucBGA
49
IND
ICE40LP1K-CM81
1280
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP1K-CM81TR
1280
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP1K-CM81TR1K
1280
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP1K-CB81
1280
1.2 V
Halogen-Free csBGA
81
IND
ICE40LP1K-CB81TR
1280
1.2 V
Halogen-Free csBGA
81
IND
ICE40LP1K-CB81TR1K
1280
1.2 V
Halogen-Free csBGA
81
IND
ICE40LP1K-CM121
1280
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP1K-CM121TR
1280
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP1K-CM121TR1K
1280
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP1K-CB121
1280
1.2 V
Halogen-Free csBGA
121
IND
ICE40LP1K-QN84
1280
1.2 V
Halogen-Free QFN
84
IND
ICE40LP4K-CM81
3520
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP4K-CM81TR
3520
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP4K-CM81TR1K
3520
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP4K-CM121
3520
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP4K-CM121TR
3520
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP4K-CM121TR1K
3520
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP4K-CM225
3520
1.2 V
Halogen-Free ucBGA
225
IND
ICE40LP8K-CM81
7680
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP8K-CM81TR
7680
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP8K-CM81TR1K
7680
1.2 V
Halogen-Free ucBGA
81
IND
ICE40LP8K-CM121
7680
1.2 V
Halogen-Free ucBGA
121
IND
ICE40LP8K-CM121TR
7680
1.2 V
Halogen-Free ucBGA
121
IND
5-2
Ordering Information
iCE40 LP/HX Family Data Sheet
LUTs
Supply Voltage
Leads
Temp.
ICE40LP8K-CM121TR1K
Part Number
7680
1.2 V
Halogen-Free ucBGA
Package
121
IND
ICE40LP8K-CM225
7680
1.2 V
Halogen-Free ucBGA
225
IND
LUTs
Supply Voltage
ICE40HX1K-CB132
1280
1.2 V
ICE40HX1K-VQ100
1280
1.2 V
Package
Leads
Temp.
Halogen-Free csBGA
132
IND
Halogen-Free VQFP
100
IND
ICE40HX1K-TQ144
1280
1.2 V
Halogen-Free TQFP
144
IND
ICE40HX4K-CB132
3520
1.2 V
Halogen-Free csBGA
132
IND
ICE40HX4K-TQ144
3520
1.2 V
Halogen-Free TQFP
144
IND
ICE40HX8K-CB132
7680
1.2 V
Halogen-Free csBGA
132
IND
ICE40HX8K-CM225
7680
1.2 V
Halogen-Free ucBGA
225
IND
ICE40HX8K-CT256
7680
1.2 V
Halogen-Free caBGA
256
IND
5-3
2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
Date
Version
Section
October 2015
3.2
Introduction
DC and Switching
Characteristics
Change Summary
Updated Features section. Added footnote to 16 WLCSP Programmable I/O: Max Inputs (LVDS25) in Table 1-1, iCE40 Family Selection
Guide.
Updated sysCLOCK PLL Timing section. Changed tDT conditions.
Updated Programming NVCM Supply Current LP Devices
section. Changed IPP_2V5 and ICCIO, ICC_SPI units.
March 2015
3.1
DC and Switching
Characteristics
July 2014
3.0
DC and Switching
Characteristics
Pinout Information
Ordering Information
April 2014
02.9
Added part numbers to the Ultra Low Power Industrial Grade Devices,
Halogen Free (RoHS) Packaging table.
February 2014
02.8
Introduction
Updated Supported Standards section. Added information on High Current LED drivers.
Corrected typos.
Added footnote to the Peak Startup Supply Current LP Devices table.
Updated part number description in the Ultra Low Power (LP) Devices
section.
Added part numbers to the Ultra Low Power Industrial Grade Devices,
Halogen Free (RoHS) Packaging table.
October 2013
September 2013
02.7
02.6
Introduction
Architecture
DC and Switching
Characteristics
Pinout Information
Ordering Information
DC and Switching
Characteristics
Pinout Information
2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
7-1
Revision History
iCE40 LP/HX Family Data Sheet
Date
Version
Section
August 2013
02.5
Introduction
July 2013
02.4
Change Summary
Updated the iCE40 Family Selection Guide table.
DC and Switching
Characteristics
Pinout Information
Introduction
DC and Switching
Characteristics
Pinout Information
Ordering Information
May 2013
02.3
April 2013
02.2
DC and Switching
Characteristics
Introduction
Architecture
Corrected typos.
DC and Switching
Characteristics
Corrected typos.
Added 7:1 LVDS waveforms.
Pinout Information
Ordering Information
March 2013
02.1
DC and Switching
Characteristics
Ordering Information
September 2012
02.0
01.31
Updated Table 1.
01.3
Production release.
Updated notes on Table 3: Recommended Operating Conditions.
Updated values in Table 4, Table 5, Table 12, Table 13 and Table 17.
Aug 2012
01.21
01.2
7-2
Revision History
iCE40 LP/HX Family Data Sheet
Date
Version
Section
July 2011
01.1
Change Summary
Moved package specifications to iCE40 pinout Excel files.
Updated Table 1 maximum I/Os.
01.01
01.0
Initial release.
7-3