Volume 4, Issue 2, March-April 2014

Available Online at www.gpublication.com/jcer

ISSN No.: 2250-2637
Genxcellence Publication 2011, All Rights Reserved

REVIEW ARTICLE

A Survey On High Throughput, Low Power Aes Algorithm

M.P.Gomathi1, M.Tamilselvi2, N.Jayapal3
*1,2

PG Scholor, ECE Department, Kongunadu College of Engineering and Technology, Trichy, India
gomathimp@gmail.com
2
147tamil@gmail.com
3
Asst.Professor, ECE Department, Kongunadu College of Engineering and Technology, Trichy, India
jayapal385@gmail.com
1

Abstract
Secure communication is necessary in transmitting data especially in the field of military, government and private Institutions.
Security is also necessary to store the information in addition to transmission. For this secure communication encryption is
used. It is also used in network security. This paper surveys about different techniques involved in the AES algorithm. It also
explains various methods involved to decrease area, increase speed and applications in different fields.
Key words
AES, Low Power, Encryption and Decryption

as cipher text. Decryption algorithm is used to convert

the unreadable one into original text that is known as
plain text. This decryption algorithm is mainly done
only by the authorized person. There are three methods
in the decryption algorithm. First method is to use
symmetric cryptography in which a single key is used
both in encryption and decryption. Second method is
asymmetric cryptography where two different keys are
used, one for encryption and the other for decryption.
Third method is cryptographic hash functions where no
separate keys are used; instead it is mixed with the
data.Data Encryption Standard(DES), Advanced
Encryption Standard(AES), Triple DES, Blowfish are
some of the symmetric algorithms.

INTRODUCTION
Cryptography is used for keeping information secure
from unauthorized people. The history of cryptography
stretches from the times of ancient Egypt to today and
its importance is increasing day by day. People are
interested in protecting their information for different
reasons. The ancient Chinese used the ideographic
nature of their character-based language to hide the
trade secrets of silk manufacturing. While Germans
used Enigma machine during Second World War to
protect their military secrets from the enemies. In recent
years, with the explosive advancement of computers,
Internet and interconnectivity the dependence of both
organizations and individuals on the information stored
and communicated using these systems has increased.
This, in turn, has led to a heightened awareness of the
need to secure data and resources from hacking and
intrusion. Many lessons were learnt with the ignorance
of security measures over Internet. Now cryptography
has become mandatory and it is considered as a basic
building block for the security of any computer system
or network.

The Data Encryption Standard (DES) may be cracked

quickly and inexpensively. Blowfish is a generalpurpose algorithm, an alternative to the DES and free of
the problems and constraints associated with other
algorithms. Schneier has stated that, "Blowfish is
unpatented, and will remain so in all countries. The
algorithm is hereby placed in the public domain, and
can be freely used by anyone."The Advanced
Encryption Standard (AES) replaced the DES to fulfill
the ever-increasing needs for security. Table 1
compares the different symmetric algorithms.

Data protection is mainly done by means of Encryption,

so that it cannot be read by hackers. Algorithm is used
to encrypt the data into unreadable one which is known
Algorithm

Network

Round of
operation

Block
size(bits)

Key size(bits)

Created by

Year

Triple DES

Feistel Network

48

64

112 or 168

IBM

1978

Blowfish

Feistel Network

16

128

Bruce Schneier

1993

Joan Daemen&
Vincent Rijmen

1998

Substitution10,12 or 14
Permutation Network
Table I: Comparison of different encryption algorithm
AES

128

128,192 or
256
128,192 or
256

Please Cite this Article at: M.P.Gomathi et al, Journal of Current Engineering Research, 4 (2), March-April 2014, 7-10

and J. V. McCanny[12], which utilizes look-up tables to

implement the entire Rijndael Round function.

AES ALGORITHM
AES is a byte-oriented, symmetric block cipher. It
consists of data blocks of 128 bits (4 words) and keys
with 128, 192, and 256 bits. AES is capable of
processing additional block sizes (160, 192, and 244
bits) and key lengths (160 and 244 bits). Figure 1 shows
the AES encryption process.

Figure 2: S-box using LUT

Figure 1: AES algorithm

Hardware implementations of encryption algorithms

prove much faster than equivalent software
implementations and since there is a need to perform
encryption on data in real time, speed is very important.
In particular, field programmable gate arrays (FPGAs)
are well suited to encryption implementations due to
their flexibility and an architecture, which can be
exploited to accommodate typical encryption
transformations. A look-up table based Rijndael design
achieves a speed of 12 Gbits/sec.
In [4], S-box design was done using composite field
arithmetic which is applied to all the transformations in
the AES algorithm. The optimum construction scheme
is selected based on minimizing the total gate count in
the implementation of all transformations. However, it
is more efficient to apply composite field arithmetic
only in the computation of the multiplicative inversion
in the Sub Bytes and Inverse Sub Bytes
transformations.

AES has four rounds of operation: SubByte, ShiftRow,

MixColumn and AddRoundKey. The final round does
not perform MixColumn step. SubBytes transformation
is implemented using S-Box.

In [6], composite field arithmetic is employed that

reduces the complexity and also enables deep subpipelining for achieving higher speed. Composite fields
can be constructed by using different irreducible
polynomials. For each construction, there exist eight
isomorphic mappings that map the elements in GF(28)
to those in composite fields. The complexities of these
mappings vary. Based on the complexities of both the
subfield operations and the isomorphic mappings, the
optimum constructions of the composite field for the
AES algorithm are selected to minimize gate count and
critical path.

DIFFERENT
TECHNIQUES
FOR
THE
HARDWARE IMPLEMENTATION OF S-BOX
One of the most common and straight forward
implementation of the S-Box for the SubByte operation
which was done in previous work was to have the precomputed values stored in a ROM based lookup table.
In [5], 128-bit AES encryption and decryption was
designed using Rijndael Algorithm and synthesized
using verilog code which can be easily implemented
with the help of FPGA. In this implementation, all 128
values are stored in a ROM and the input byte would be
wired to the ROMs address bus. However, this method
suffers from an unbreakable delay since ROMs have a
fixed access time for its read and write operation. This
implementation is expensive in terms of hardware.
Figure 2 shows the implementation of S-box using
Look Up Table(LUT).

Nowadays, S-Box design is based on the Galois Field

(GF). GF(28) is constructed by performing two
transformations such as multiplicative inverse and
affine transformation. In [3], the s-box design was
mainly based on Galois field. Here the S-box and
inverse S-box of the AES is divided in to five blocks.
First three blocks perform multiplicative inversion and
the next two blocks perform the transformation and
affine matrices, based on Galois field operation. Figure
3 shows the S-box implementation using GF operation.
Figure 3: S-box using gf operation

A Rijndael encryption design and its FPGA

implementation are presented in 2001 by M. McLoone

Please Cite this Article at: M.P.Gomathi et al, Journal of Current Engineering Research, 4 (2), March-April 2014, 7-10

AES FOR IMAGE ENCRYPTION:

The modifications in each round of the AES algorithm
are done by PriyankaPimpale, RohanRayarikar,
SanketUpadhyay in 2011[11]. They improved the
complexity of the encryption method and making it
complicated for the attacker to predict a pattern in the
algorithm. In each transformation of the modified
architecture, the 8-bit values are separated in to 4-bits
and they are grouped and then perform the
transformation process. The modifications have
provided the algorithm with strong diffusion and
confusion.

In [7], two approaches of compression-encryption are

presented based on the Faber-Schauder Multi-scale
Transformation. The comparison of FMT-AES method
is done with other methods like FMT-DES, QuadtreeAES, DCT-partial encryption and DCT-RSA. Mixed
scale visualization is done.
In [8], AES is implemented with low power and high
speed to encrypt an image. Here symmetric key
encryption algorithm is choosen. Four stage pipeline
technique is used to increase the throughput. Power is
reduced by means of signal gating, resource sharing and
pipelining.Implementation is done on FPGA of Altera
company and achieves 475 MHz frequency. 301mw
power is achieved in 100MHz clock frequency. Time
used for encrypting an image is 1.25ms for 32*32 size.

AES TO ACHIEVE LOW POWER AND HIGH

THROUGHPUT
A. Satoh, S. Morioka, K. Takano and S. Munetoh in
2001[13] described the Compact and high-speed
hardware architectures and logic optimization methods
for the AES algorithm. S-box structure is optimized by
introducing a new composite field. An extremely small
size of 5.4 K gates is obtained for a 128-bit key
Rijndael circuit using a 0.11-m CMOS standard cell
library. The throughput achieved is about 2.6 Gbps by
making effective use of the parallel feature.

In [9], image encryption is done using AES by adding a

key stream generator which is composed of three linear
feedback shift registers. This method is characterized
for an image with reduced entropy. It produce more
security and easy to implement in hardware and
software.
In [10], 128-bit AES standard is used for image
encryption. It was developed with VHDL code and
performance is analyzed with the help of timing
analyzer in XILINX ISE 9.2i software.

In [1], three composite field arithmetic(CFA) Advanced

Encryption Standard (AES) S-boxes are derived.
Among the three constructions the best one is selected.
Here, eight possible isomorphic mappings exist for each
composite field constructions. New common
subexpression elimination algorithm is implemented in
order to achieve minimum area. It achieves a
throughput 3.49 Gbps on a Cyclone II EP2C5T144C6
field-programmablegate array.

CONCLUSION
In this paper, various techniques used to implement Sbox in AES algorithm are analyzed. These various
techniques are implemented to achieve high throughput,
low power. AES algorithm is also used in image
encryption. It plays a vital role in security.

In [2], explores the area-throughput trade-off for an

ASIC implementation of the Advanced Encryption
Standard (AES). Pipelined architecture is involved for
area optimizations and high throughput. It achieves 30
Gbits/s to 70 Gbits/s throughputs in a 0.18nm CMOS
technology with loop unrolling in addition to pipelined
architecture. The area is reduced to 35 percent by means
of inner-round pipelining. Further it is reduced up to 28
percent by designing offline key scheduling unit.
Totally it results in 48 percent of area reduction. In
figure 4, the pipelined technique for S-box is shown.

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Figure 4: S-box using pipelining

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