Single-Stage DC-AC Converter for Photovoltaic Systems

Hugo Ribeiro1,3
Andr Pinto1,2

Beatriz Borges1,2
Senior Member

Instituto de Telecomunicaes, 2Instituto Superior Tcnico, Av. Rovisco Pais, 1049-001 Lisboa, Portugal
3
Instituto Politcnico de Tomar, Escola Superior de Tecnologia, Estrada da Serra, 2300 Tomar, Portugal
hugo@ipt.pt, bborges@lx.it.pt, coelho_pinto@hotmail.com

Abstract - This paper presents a DC-AC converter that merges a

DC-DC converter and an inverter in a single-stage topology to
be used as an interface converter between photovoltaic systems
and the electrical AC grid. This topology is based on a full
bridge converter with three levels output voltage, where two
diodes and one inductor have been added in order to create a
Boost converter. The control system of the proposed converter is
based on two hysteretic controllers: one for the grid injected
current and the other for controlling the panel current. A
prototype of the proposed converter including power and
control circuits was developed. The MPPT algorithm is not yet
implemented and, therefore, to obtain experimental results an
additional power supply is used to emulate the PV panel.
Theoretical analysis and design criteria are presented together
with simulated results to validate the proposed concepts.
Experimental results are obtained in a lab prototype to evidence
the feasibility and performance of the converter.
Keywords: Photovoltaic system, single-stage DC-AC converter,
full bridge Inverter, boost converter, hysteretic control.

I.

INTRODUCTION

The Photovoltaic (PV) energy is a renewable energy source,

which has gained importance in the last few years. However,
the ratio price/efficiency of PV systems is currently still too
high [1] calling therefore, for the necessity of having a high
performance power electronic converter in order to keep the
global system efficiency within acceptable values. The
typical PV converter is based on a two stages converter [2-3].
Normally, the first stage is a DC-DC boost type converter
needed to extract the maximum power from the panel and to
boost the PV DC voltage to a higher value than the peak of
the grid voltage, to enable the supply of the second stage. The
second stage is a DC-AC inverter that generates a sinusoidal
current to be injected in the grid, Fig.1. The association of the
two converters results in a two stages power inverter with the
inherent drawbacks: high cost and the necessity of having
very high efficiency in each stage to obtain an acceptable
global efficiency.
Due to the necessity of reducing the cost and to increase the
efficiency of the systems simultaneously, the interest in
single stage topologies has grown during the last years [4-9].
The single stage PV topologies must carry out two functions
as arises in two stages solutions: the extraction of the
maximum power from the panel and the injection of a
sinusoidal current waveform into the grid. To realize the two
functions in a single stage topology it is necessary that these
functions share the power transistors.

978-1-4244-5287-3/10/$26.00 2010 IEEE

Fig.1. Power Grid connection of a PV array by means of a two stages

converter.

This condition results in interdependency between both

conversion processes, and introduces an additional
complexity of the converter dynamic behaviour, imposing
several restrictions and limitations to the circuit parameters.
Some converters are denominated single stage converters,
but they only realize one of the two tasks referred, the
injection of the sinusoidal current in the grid, which is made
by the direct inversion of the PV voltage, [4-7]. These
solutions present some drawbacks, namely: the PV voltage
needs to be higher than the peak of the grid voltage to
guarantee the grid current injection or alternatively a step up
transformer must be used.
The paper introduces a new single stage topology based on
a full-bridge DC-AC inverter together with two additional
diodes and one input inductor to implement two boost
converters that share the same input inductor, Fig.2.

Fig.2. Proposed converter: single-stage DC-AC converter for PV systems.

II.

TOPOLOGY OPERATING PRINCIPLES

As any other full-bridge converter, the proposed circuit

presented in Fig.2 has four possible states, S00, S10, S01 and
S11, according to the conduction states of the two pairs of
switches, from different legs.

604

In order to simplify the analysis of each conversion process,

Fig.3 shows the different boost and bridge modes obtained
considering the above defined states and only the respective
transistors and diodes involved in each process.

VCP VCF
State S11

diLP LP
=
dt
VCP
States S10 , S01 , S00
LP

+ VCF vR

LR

diLR VCF vR
=
dt
LR

vR

LR

State S10
State S01
State S00

or

(1)

S11

(2)

By considering table I and (1) and (2) is possible to verify

that the only state that allows reducing the current in the input
inductance is S11. This fact eliminates the possibility of
controlling the injected current in the grid, iLR, by using only
the two states S01 and S10 because the option for these two
states increases the input current. This way, the control of iLR
is made in three levels: +VCF and zero when the mains
voltage is positive (vR>0), and -VCF and zero when the mains
voltage is negative (vR<0).
From the inspection of the table I, it is possible to verify
that to obtain voltage vAB null, the converter can use one of
the two states S11 or S00. From the viewpoint of the grid
current regulation, the choice of any of those states has the
same effect.

(a)

(b)
Fig.3. Proposed circuit operating modes considering the different states: (a)
boost modes; (b) bridge modes.

Table I summarizes the switching states of the power

transistors. The influence of the converter states into the state
variables slope is also referred in Table I.
TABLE I
POWER TRANSISTORS SWITCHING STATES
T1 / T3

T2 / T4

vAB

States

di LP
dt

di LR
; vR > 0
dt

di LR
;vR < 0
dt

on/off
on/off
off/on
off/on

on/off
off/on
off/on
on/off

0
+VCF
0
-VCF

S00
S01
S11
S10

>0
>0
<0
>0

<0
>0
<0
<0

>0
>0
>0
<0

Fig.4. Voltage vAB and current iLR time diagrams for the different transistor
states evidencing the iLP control time intervals.

On the contrary, from the viewpoint of the current iLP

control, the option for S00 or S11 results in an increase or
decrease of iLP current, respectively. Thus, the control
strategy for the SS converter depends on the selection of the
state S11 or S00 during the time interval where vAB=0, in order
to decrease or increase iLP current. Fig.4 shows the waveform
of vAB voltage for different transistor states together with the
control states adopted during the time interval where vAB=0.
III. TOPOLOGY CONTROL

Based on the operating modes presented in Fig.3 the

equations that define the slopes of the currents iLP and iLR,
diLP/dt, diLR/dt can be established as follows:

The proposed topology requires the control of three

variables: the current injected on the grid, iLR, which must
follow the sinusoidal reference, iLREF; the voltage on the DC
bus, VCF, and at last the current in the LP inductor, iLP, which
corresponds in steady state to the panel current. Fig.5
presents a simplified building block diagram of the control
circuit.

605

Considering the three logic variables defined before, a

controllability table with eight vectors representing the
transistor gate signals is obtained.

vR<0

0
0
0
0

TABLE II
CONTROL POWER TRANSISTORS SWITCHING STATES
State Control action T1 T2 T3
Variables states

iLP K I < iLPREF 2
S00
1 1 0
0 0
iLP iLR
iLR K I < iLREF 1
iLP K I < iLPREF 2
iLP iLR
S01
0 1
1 0 0
iLR K I > iLREF + 1
iLP K I > i LPREF + 2
iLP iLR
0 0 1
S11
1 0
iLR K I < i LREF 1
iLP K I > i LPREF + 2
iLP iLR
1 1
S01
1 0 0
iLR K I > i LREF + 1

1 0 0

The control of iLR and iLP, is achieved by using two

hysteretic comparators that generate two digital signals:
related with the error in iLR and related with the error in iLP.
This control method results in a variable frequency and non
linear control. An additional digital variable, , is needed to
define the polarity of the mains voltage. Fig.6 shows the
simplified schematic of the non linear control.

vR>0

Fig.5. Simplified building block diagram of the control circuit.

1 0 1
1 1 0
1 1 1

iLP K I < iLPREF 2

iLR K I < iLREF 1
iLP K I < iLPREF 2
iLR K I > iLREF + 1
iLP K I > i LPREF + 2
iLR K I < i LREF 1
iLP K I > i LPREF + 2
iLR K I > i LREF + 1

T4
0
1
1
1

S10

iLP iLR

0 1 1 0

S00

iLP iLR

1 1 0 0

S10

iLP iLR

0 1 1 0

S11

iLP iLR

0 0 1 1

There are two vectors, (0,1,1) and (1,1,0) (marked with gray
in the table) where is impossible to obtain the ideal transistor
gate vector, which means that it is only possible to control
one of the two variables. For these vectors, it was adopted to
control iLR instead the iLP to avoid perturbations on the grid
current which results in a significant harmonic distortion
increase. In the other hand, as will be demonstrated further,
the iLP perturbations are very small and do not compromise
the converter operation.
The design of the linear control for the VCF voltage is based
in the average model, presented in Fig.7. In the model the
100Hz voltage ripple is not considered because the controller
is designed to present a reduced gain at 100Hz, < -30db.

Fig.6. Simplified schematic of the non linear control.

The two hysteretic comparators have the hysteretic

windows of 2.1 and 2.2 to control iLR and iLP respectively.
These hysteretic windows will define the ripple that involves
the variables regulation and the frequency range of operation.
The logic equations defined by the comparators are given by:

i LR K I > i LREF + 1 = 1
i LR K I < i LREF 1 = 0
i LP K I > i LPREF + 2 = 1
i LP K I < i LPREF 2 = 0
vR > 0 = 1
vR < 0 = 0

(3)

Fig.7. Average model of the VCF controller.

The variables, IFB (the average full-bridge current delivered

by CF), IB (the average boost current that charges CF) and the
gain KG are given by:

(4)

I FB VCF =

VI I LR
V I
I FB = I LREF vCTR
2
2 K VCF
 I 

(6)

KG

(5)

606

VCP ILP =VCF IB IB =

VCP
ILP
VCF

(7)

Fig.8 shows the block diagram of the system in the Laplace

domain.

The last simulation was obtained with the average model

presented in Fig.7 b), where the referred power variation
corresponds to an IB variation of 0.1 to 0.5A.
IV. DESIGN CRITERIA

Fig.8. Block diagram of the system in the Laplace domain.

Considering the parameter values used in the experimental

and simulation results (KG=0.25 and CF=660F) the
controller was designed to assure a phase margin greater than
30 degrees, maximizing the gain at low frequency and
presenting an open loop gain minor than -30db at 100Hz. To
achieve the above considerations, the following parameters
values were adopted for the controllers: KP=20; P=100rad/s
(fP=16Hz); z=31rad/s (fZ=5Hz).
Fig.9 (a) shows the Bode diagrams of the open loop gain
and phase of the system. Fig.9 (b) presents the dynamic
response of the VCF voltage controller for a boost power
variation of 30W to 150W.

The first parameter to be designed is the minimum voltage

on the CF capacitor. According to the VCF voltage and to the
range of variation for VCP and VR the maximum and minimum
values for the switching frequency will be obtained. At last
the LP and LR values will be determined.
A ) Minimum VCF voltage
As referred before the switching frequency involved in
both conversion processes will be variable. Independent of
this fact, each conversion process imposes one duty ratio: DFB
for the full-bridge and DB for the boost:

v AB = VCF DFB
VCF =

VCP
1 DB

(8)
(9)

The minimum value of the capacitor voltage, VCFmin is than

established considering the following conditions: the
minimum boost duty ratio, DBmin, will be equal to the
maximum full-bridge duty ratio DFBmax (worst case); the vAB
average voltage, v AB , must be higher than the maximum
value of the mains amplitude, VRmax, to assure the evolution of
the iLR current in continuous conduction mode, CCM.

v AB > VR max VCF min DFB max > VR max

VCF min =

VCP max
1 DB min

(10)
(11)

Considering DFBmax=DBmin the VCF value is given by:

a)

VCF VR max + VP max

(12)

The capacitor CF is designed considering its voltage ripple,

VCF , the mains frequency, fR and the system efficiency, :

CF >

PO max
2 VCF VCF f R

(13)

B ) Maximum and minimum switching frequencies

b)
Fig.9. (a) Open loop gain and phase of the VCF voltage controller; (b)
dynamic response for a boost power variation of 30W to 150W and vice
versa.

Related with the two conversion processes, two switching

frequencies must be defined: fSR related with the full-bridge
operation and fSP related with the boost operation.
The maximum values of fSR and fSP are established based
on Fig.10 which can represent simultaneously the current
evolution in LR or LP. The time intervals t1 and t2 are used to
define the duration of each slope.

607

The maximum duration, tPmax, of S01 or S10 is obtained by

(14) when the mains amplitude voltage is maximum:

t P max =

VCF VR max

(18)

The LP current maximum perturbation, iLPP, is obtained

considering (15) and (18):

Fig.10.Tipical current evolution in inductors LR or LP.

Considering Fig.10 and the different slopes of iLR and iLP

during the time intervals t1 and t2 are obtained:

i LR =

VCF VR
V
t1 = R t 2
LR
LR

(14)

i LP =

V VP
VP
t1 = CF
t2
LP
LP

(15)

i LPP =

VP
VP i LR LR
t P max i LPP =
LP
LP (VCF VR max )

(19)

D ) Design of LP and LR

The two operating periods, TSR and TSP, are obtained

considering the sum of the time intervals t1 and t2:

1
1
TSR = iLR LR
+
VCF VR VR

iLR LR

f SR =

1
1

TSP = iLP LP
+

VCF VP VP

f SP =

1
TSR

(16)

1
TSP

(17)

The first variable established is the VCF voltage which

depends of the maximum value of the mains voltage, VRmax,
and the panel voltage, VP. Considering VRmax=180V
correspondent to ( VR max = 1.1 2 115Vef ) and VPmax=70V
the VCF value is defined:

VCF VR max + VP max VCF 180 + 70 250V

(12)

VCF = 300V was adopted

The maximum values of fSR and fSP are obtained when VR

and VP are equal to VCF/2 if VR and VP surpass VCF/2.
Otherwise, the maximum values of fSR and fSP are obtained
when VR and VP are maximum.
C ) Panel current perturbations
As stated above the current in LP may present perturbations
during the time intervals correspondent to the occurrence of
vectors (0,1,1) and (1,1,0). In the worst case the iLP current can
be perturbed during a complete state S01 or S10, as presented
in Fig.11.

Fig.11. Typical LP and LR current evolution with the presentation of an iLP

perturbation.

The inductors LR and LP are designed considering their

maximum frequency fSRmax and fSPmax and their respective
current ripples. In the prototype the following parameters
were considered: fSRmax=25kHz - iLR=0.15.ILRmax=0.3A,
fSPmax=10kHz - iLP=0.3.ILPmax=0.6A. Using (18) and (19) the
following inductors values were adopted: LR=7.5mH and
LP=10mH. For the iLP current were considered a greater
ripple and a minor switching frequency in order to reduce the
amplitude of the perturbations.
In the present the
perturbations will be lower than 0.17A.
V.

SIMULATION AND EXPERIMENTAL RESULTS

The initial experimental results of the proposed topology

were obtained in a 200W prototype, with the following
specifications: VGrid =115Vef 10%; VCF=300V; VCP= 70V;
CF=660F, LR=7.5mH and LP=10mH. These preliminary
tests have the objective of demonstrating the concepts
introduced in the paper, testing the topology and the control
functionality.
Fig.12 shows experimental results of the most important
current and voltage waveforms that allow to demonstrate the
correct operation of the topology and its respective control.
Fig.13 shows the simulation results of the iLR and iLP in
order to verify the switching frequency of these variables and
the current perturbations obtained in iLP.
Inspection of the experimental and simulation results
allows verifying the correct operation of the converter with
the current ripples magnitudes and switching frequencies
adopted in the design. It is also possible to verify that the iLP
current perturbations are very small.

608

iLP
iLR

a)

a)

vgrid

b)

b)

vCF
iLR

c)

c)

Fig.12. Experimental results: a) iLR (blue trace) with a gain of 1A/div, iLP
(green trace) with a gain of 1A/div; b) grid voltage (magenta trace) with a
gain of 50 V/div; c) vCF voltage (red trace) with a gain of 100V/div and iLR
(blue trace) with a gain of 1A/div.

VI. ACKNOWLEDGMENT
This work was supported in part by Instituto de
Telecomunicaes and by the Fundao para a Cincia e para
a Tecnologia, FCT, under the Grant SFRH/BD/40220/2007.
VII.

CONCLUSIONS

The new contribution of this paper consisted in the

proposal of a new DC-AC converter for PV systems that
includes two Boost converters and a full-bridge inverter in a
single-stage topology. The unique restriction imposed by the

Fig.13. Simulation results: a) iLR (blue trace) with a gain of 1A/div, iLP (green
trace) with a gain of 1A/div; b) Obsetvation of iLP perturbations; c)
verification of the maximum iLR switching frequency value, fSRmax.

converter is the minimum VCF voltage which must be greater

than the sum of the maximum values of the panel and the grid
voltage. Due to the high voltage gain given by the two input
boosts, the topology is suitable to operate with low panel
voltages. The theoretical concepts introduced in the paper
were proved by the preliminary results obtained in the
experimental tests of the converter prototype that is still in
development. A converter efficiency of 90.5% was achieved.
The prototype used to obtain the preliminary experimental
results presented in the paper is not yet optimized in terms of
layout and power density. It is expected that, in what
concerns circuit layout, the reduction of the leakage

609

inductances will result in a significant reduction of the

dissipated power which will end up in efficiency increase.
VIII.
[1]

[2]
[3]

[4]

[5]

[6]
[7]
[8]
[9]

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