MULTI-VOLTAGE DESIGN FLOW WITH

OLYMPUS-SOC

W H I T E P A P E R

MENTOR GRAPHICS
DECEMBER 2013

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Multi-Voltage Design Flow with Olympus-SoC

INTRODUCTION TO LOW POWER DESIGN FLOWS

One of the biggest challenges in IC design at advanced nodes is the complexity inherent in effective power
management. Whether the goal is to reduce on-chip power dissipation to reduce temperature and minimize
cooling requirements, or to provide longer battery life to mobile and handheld devices, power is taking its
place along side timing as a critical dimension to be optimized during physical design.
The complexity problem is exacerbated by an explosion in the number of corner, mode, and power state
scenarios that could have conflicting power, timing, and signal integrity (SI) closure requirements. The basic
low-power design techniques, such as clock gating for reducing dynamic power and multiple voltage
thresholds (multi-Vt) to decrease leakage current, are well-established and supported by existing tools for a
single mode/corner combination. However, designers are running into difficulty with more advanced
techniques such as designing for power in a multi-corner multi-mode context, multi-voltage flows, and
designing power-efficient clock trees.
With a multi-voltage supply (also called multi-Vdd) approach, some blocks use lower supply voltages than
others, creating voltage islands. This flow gets even more complex when dynamic voltage and frequency
scaling is used to change the supply voltage level and clock frequency during operation. In a multi-corner
multi-mode (MCMM) scenario, clock power consumption depends on various factors such as the circuit design
style, architectural choice, clock distribution wiring, clock driver sizing, and the capability to disable part of
the clocking network using optimal clock gate placement.
Designers need new low-power capabilities across the entire design flow that enable them to clearly see and
understand the impact of power on their design. Fortunately, innovative design techniques focused on
minimizing power dissipationfrom high-level power-aware design and verification to back-end physical
design optimizationare now emerging, enabling design teams to assess and optimize their designs.
Olympus-SoC low power platform supports all the advanced low-power implementation techniques in a
comprehensive variability-aware place-and-route environment.

MULTI-VOLTAGE DESIGN CHALLENGES AND MCMM

An increasingly common technique to reduce power is the use of multiple voltage islands (domains), which
allows some blocks to use lower supply voltages than others, or to be completely shut off for certain modes of
operation. Multi-voltage designs are difficult to implement because of the different voltage levels used for
different blocks, and also because of the need to handle special cells such as level shifters and isolation cells.
These design styles also cause the number of modes and corners to increase significantly when min/max
voltage combinations from all the power domains are considered.
Because each different voltage supply and operational mode implies different timing and power constraints
on the design, multi-voltage methodologies cause the number of design corners to increase exponentially
with addition of each domain or voltage island. Additionally, the worst case power corners dont necessarily
correspond to the worst case timing, so its virtually impossible to know how to pick a set of corners that will
result in true optimization across all design objectives without excessive design margins. Figure 1 shows how
the corners and power states proliferate for even a simple multi-Voltage design. The core operates at 1.2V or
1.8V. One power island operates at 0.9-1.2V and can switch on and off. The second power island operates at
0.9-1.5V.

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Multi-Voltage Design Flow with Olympus-SoC

Figure 1: Each additional power domain adds to the number of corners under which the design
must be analyzed, optimized, and verified.

In order to close the design across all modes, corners, and power states, the setup and hold times must be
analyzed simultaneously for different combinations of library models, voltages, and interconnect (RC) corners.
Incumbent implementation flows are designed to handle one or two scenarios and are not well suited for
solving power and timing constraints concurrently. Each timing and optimization iteration would require
multiple RC extractions, timing analysis runs and power analysis runs, which increases the engineering effort
during the final stages of the chip implementation. This leads to unpredictability in sign-off ECO loops and
added margins that reduce designs performance, increase area and power dissipation, and lower yields.
This approach offers no guarantee of convergence because optimizations in one scenario could create a new
violation in a different scenario. Not surprisingly, taking this limited approach, coupled with late-stage
unpredictability, results in less than acceptable power performance, higher chip failures and overall delayed
schedules. The best solution is to analyze and optimize the design for all corners and modes concurrently. In
other words, low power design inherently requires true MCMM optimization for both power and timing.

LOW-POWER IMPLEMENTATION WITH OLYMPUS-SOC

The Olympus-SoC low power platform comprehensively handles the requirements of low-power design, while
ensuring optimization of the overall solution without excessive design iterations, enabling engineers to
rapidly deliver fully optimized, power efficient designs. The Olympus-SoC low power platform has a number
of capabilities to manage both design intent, total power optimization and to make intelligent trade-offs
between power, area, and timing across all the corners and modes throughout the design flow. Olympus-SoC
is well suited for low-power designs because its MCMM analysis drives closure for all design modes, process

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Multi-Voltage Design Flow with Olympus-SoC

corners, and power constraints simultaneously. The Olympus-SoC low-power platform includes the following
key technologies to address low power challenges and deliver best quality of results:
Completely automated multi-voltage flow with support for dynamic voltage and frequency scaling
(DVFS) to handle varying supply voltages and clock frequencies, and the capability to handle special cells
such as level shifters, isolation cells, and MTCMOS switches.
Power aware CTS with smart clock gate placement, slew shaping, register clumping and concurrent
MCMM optimization that ensures a balanced clock tree with the minimum number of clock buffers.
Unique architecture that provides seamless concurrent optimization for both power and timing, covering
all operating modes and corners through all stages of the flow.
Comprehensice Unified Power Format (UPF) based netlist-to-GDSII flow.
Additionally Olympus-SoC offers techniques such as concurrent multi-voltage threshold (Vt) optimization,
power gating, gas station methodology, and power aware buffering and sizing. Olympus-SoC customers are
experiencing 2-3X faster design closure times and up to 30% power savings versus traditional tools.

MULTI-VOLTAGE FLOW WITH OLYMPUS-SOC

Multi-voltage design, a popular technique to reduce total power, is a complex, time-consuming task because
many blocks are operating at different voltages, or intermittently shut off. Level shifter and isolation cells
need to be used on nets that cross domain boundaries if the supply voltages are different or if one of the
blocks is being shut down. DVFS is another technique where the supply voltage and frequency can vary
dynamically to save power.
Power gating using multi-threshold CMOS (MTCMOS) switches involves switching off certain portions of an IC
when that functionality is not required, then restoring power when that functionality is needed. Designers
also use retention memory elements to retain key state data during the sleep mode so that it can be correctly
restored upon power up.
Olympus-SoC is UPF compliant, so the power intent
for multi-voltage captured in the UPF file is carried
through the physical design flow. Each step of the
flow offers opportunities for power savings through
clever implementation techniques, some of which are
described in the following sections. Figure 2
illustrates the netlist-to-GDSII multi-voltage flow in
Olympus-SoC.

Figure 2. The physical design flow for multi-voltage designs

includes the ability to define power domains in Unified Power
Format (UPF), advanced features for placing and routing across
domains, and optimizing clock tress for all operating modes.

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A little extra time spent in capturing the power intent

in UPF can pay off by avoiding implementation and
verification problems later in the flow. After reading
in the power specification, users can analyze domains
and power connectivity with queries to the OlympusSoC database. Users can trace connectivity on power
pins just like on signal pins, verify the power applied
to a given pin, and check isolation cells, level shifters,
switches, and retention cells. The UPF file includes the
power state table (PST), which defines the
combinations of voltages and power states, which are
essentially treated as operational modes in the
Olympus-SoC MCMM environment.

Multi-Voltage Design Flow with Olympus-SoC

The design flow for multi-voltage designs consists of several distinct sections:
Design import - ASCII import for library and design data
Power domain setup - Based on UPF
Timing setup - Timing environment setup for differnt modes and corners
Placement related constraints - Power domain regions, blockages and placement constraints for special
multi-voltage cells
Power intent verification - Verifying power intent and design setup analysis
Pre-CTS - Respecting multi-voltage constraints during optimization
CTS - Support for equivalent class for clock gates
Routing Domain-aware routing and secondary VDD connections
MTCMOS switches Handling switching cells during floorplanning for domains that are shut off
Multi-voltage GUI

DESIGN IMPORT
The design import step is the same as for non- multi-voltage design flows in that the user will start with the
same ASCII input files: LEF, lib, SDC, Verilog, and DEF. The main differences in the data and properties that are
relevant to the multi-voltage design flow are summarized below.

LIBRARY DEFINITION
Loading the timing libraries into Olympus-SoC for multi-voltage designs is essentially identical to the standard
flow with the exception that multi-voltage designs may have multiple timing libraries for each cell. OlympusSoC is capable of reading multiple timing libraries for each cell type and accessing the proper timing
information for any cell based upon the cells power supply values in a particular power state.
There are several new cell and pin properties contained in timing libraries intended for multi-voltage designs.
The following list includes some of the most commonly encountered properties introduced for multi-voltage
designs:
always_on lib cell property that marks the always-on repeaters in the library
is_isolation_cell lib cell property that marks the isolation cells in the library
is_isolation_enable lib cell pin property that identifies control signal for isolation cells
is_level_shifter lib cell property marks the level shifter cells in the library

CORNER DEFINITION
In multi-voltage designs the user may need to define corners with multiple logical libraries for the same
analysis corner. For example, a design may have a voltage domain operating at 0.9 volts while the rest of the
chip operates at 1.1 volts. For concurrent timing analysis, the user can define one corner with both the 0.9 and
1.1 volt libraries and Olympus-SoC will select the proper logical library for timing analysis based on the power
supply connected to the leaf cells and the characterized voltage level of the library.

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Multi-Voltage Design Flow with Olympus-SoC

MODE DEFINITION
Users can define unique modes for all the different voltage combinations that are valid in a given design. It is
important to note that if designers want concurrent timing analysis for each power state in a design, there
must be at least one design mode defined for each power state in the PST.

FLOORPLAN UPDATES
The floorplan data for multi-voltage designs is similar to non- multi-voltage designs. The most important data
from the floorplan are the regions that map to the power domains in the design. The region constraints
define the physical boundaries for the power domains.

POWER DOMAIN SETUP

Domain definition and supply net information from the UPF file is used during the floorplanning stage, the
first step in the flow. During floorplanning, physical domains are created and the corresponding power
structure is created for each individual supply net defined in the UPF file. Domain specific hierarchy mapping
and library association is defined by the user based on the architecture. The power domain data is read into
Olympus-SoC by sourcing a UPF file. Olympus-SoC also extends concurrent design analysis across modes and
corners to now include a third component in design analysis; voltage. After reading a complete UPF file, the
following items will be defined in the current design:
Power domains with default power and ground nets
Power state table to define all possible power state combinations
Level shifter and isolation rules for the different voltage domains
During floorplanning, the native row-cutter
identifies legal rows in different voltage islands,
and places IO pads to provide the initial guides for
cell placement. The Olympus-SoC numerical
prototyping placer then groups cells into
partitions, and assigns partition pins. Users can
control the placement of isolation cells and level
shifters by specifying regions and net weights.

Figure 3. Multi-voltage layout shown in Olympus-SoC. Power

domains are easy to work with. Each shaded area is a separate
power domain. Cells assigned to each domain are highlighted to
show at a glance that placeent restrictions were honored.

Even with no specific UPF directives, Olympus-SoC

places cells on the most active nets closer to
minimize switching power. To verify the power
domain setup, Olympus-SoC analyzes level shifters
and isolation cells to ensure they are correctly
placed before proceeding with routing. It will also
check always-on connections to ensure that the
signal is not lost due to OFF state voltage islands.
Figure 3 illustrates a placed floorplan with two
power domains.

POWER INTENT VERIFICATION

Power intent verification and design checks are automatically performed for general design and UPF setup,
verification of level shifters and isolation cells, and analysis of always-on connections. Olympus-SoC does a
general check for common setup issues or missing data after loading a design and defining the power intent.
The purpose is to help you find any missing UPF or power setup data that could lead to sub-optimal results.
The following table (Figure 4) shows a sample report:
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Multi-Voltage Design Flow with Olympus-SoC

Figure 4. Olympus-SoC generates power domain verification reports for easy and early debugging of
the power setup.

Olympus-SoC also supports full insertion of level shifters and isolation cells, and has the ability to repair an
existing netlist for level shifter or isolation connections. Olympus-SoC recognizes the existing level shifters or
isolation cells in the netlist and preserves connections between these special cells and the power domain
boundaries. The reporting commands are useful for analyzing the existing netlist for a given power domain
and a set of isolation or level shifter rules. Olympus-SoC can also insert level shifter/isolation cells or repair
their connections on user-specified power domains based on the existing isolation and level shifter rules.
Isolation and level shifter cells are assigned to a particular power domain based upon their main power supply
pins and the default power supplies of the power domains. This assignment determines where these special
cells will be physically placed. The multi-voltage GUI can be used to visualize the special cells domain
association.

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Multi-Voltage Design Flow with Olympus-SoC

PRE-CTS FLOW
During the pre-clock tree synthesis (CTS) flow, Olympus-SoC will ensure that no port punching occurs on
power domain interfaces and will also enable route channels to guide routing around power domain
boundaries. The optimization engine uses the PST when buffering nets in a multi-voltage design to
automatically choose always-on-buffers. This simplifies the flow for users while providing more optimal multivoltage results.
Olympus-SoC has the ability to use feedthrough buffering within a multi-voltage design flow. If feedthrough
buffering is enabled and a net between two domains requires a buffer, but the buffer physically needs to be
placed outside of the domains the net connects, Olympus-SoC will place the buffer physically outside of the
two domains but will add it logically to the hierarchy of the driving cell. This will prevent logical port punching
but still allow an optimal buffering solution. The power supplies for the new buffer will be determined based
upon the PST buffering algorithm explained above. An example PST table, as reported in Olympus-SoC, is
shown in Figure 5.

Figure 5. The PST associates design modes with voltage domains.

CTS AND CLOCK ROUTING

The CTS engine prevents any port punching on the power domains when the multi-voltage flow is enabled.
Like the optimizer, the clock tree engine also uses a PST-based buffering algorithm to determine the type of
buffers to use while expanding the clock tree networks. Some clock tree synthesis flows require special clock
gate classes to be recognized in order to restrict sizing operations during CTS to equivalent class types.
Olympus-SoC reads the power_gating_cell attribute from .lib and sets an internal property to track
equivalent classes among clock gates
The routing flow remains relatively unchanged for multi-voltage designs and by default the routing engine
honors the domain boundaries and contains the routes within them. Routing constraints are automatically
generated for the routing engines to control route topology around and over the power domains. Secondary
power pin connections for special cells such as always-on buffers and level shifters are handled automatically
by Olympus-SoC using special properties set on the power pins. Many design flows also require double vias
and non-default width wires for routing of the secondary power connections, which Olympus-SoC will honor.

MTCMOS SWITCHES
Power gating to shut down certain blocks using multi-threshold CMOS (MTCMOS) switches to minimize
leakage power is done using the multi-voltage infrastructure. Domains that need to be powered down can be
captured in the UPF file along with the switch and enable line
definition. The switch is connected between the constant and
the variable supply and is controlled using the switch enable
line. Olympus-SoC uses several different approaches for
switch cell insertion including peripheral and distributed
insertion to facilitate implementation for different design
styles. Figure 6 illustrates the distributed style switch cell
methodology.

Figure 6. Distributed POS switch cell insertion methodology.

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Multi-Voltage Design Flow with Olympus-SoC

Domains that are powered down using switch cells should also have isolation cells for any nets that cross the
domain to eliminate floating nets. Olympus-SoC automatically handles both level shifters and isolation cells
when there is a difference in supply voltage. Special sequential elements are also needed to retain state when
the block is powered down. Hooking up retention flops is done automatically by Olympus-SoC if the flops are
present in the incoming netlist.
Care must be taken for stitching the enable lines for the switches to minimize rush currents when the block is
powered on. Olympus-SoC provides a flexible API that allows designers to customize enable line stitching to
minimize switching transients. Always-on buffer insertion is also supported for the enable line buffering of
switch cells.

MULTI-VOLTAGE GUI
Multi-Voltage GUI window helps you visualize the multi-voltage setup of a design. It can be accessed through
the multi-voltage selection on the View menu of the main menu bar of Olympus-SoC. The multi-voltage GUI
provides a means of visualizing various multi-voltage items such as level shifter and isolation cell locations
and associations, always-on buffer locations, etc. Olympus-SoC also includes several reporting commands to
help analyze the multi-voltage setup of a design.

SUMMARY
Reducing power consumption has become a key design challenge at advanced technology nodes. For many
IC designs, optimizing for power is as important as timing due to the need to reduce package cost and extend
battery life. Olympus-SoC offers comprehensive power closure capabilities with three key technologies:
MCMM optimization, support for multi-voltage designs, and advanced low-power CTS.
Olympus-SoC is the only place-and-route system to offer true concurrent MCMM power and timing closure for
optimal QoR and fast turnaround time. With full support of UPF commands, Olympus-SoC handles multivoltage design requirements through the entire place-and-route flow. It automates the placement of level
shifters, isolation cells, and MTCMOS switches and provides complete graphical analysis, optimization and
verification of power domain cells and connectivity. Finally, the advanced CTS and clock optimization
techniques are extremely effective at lowering clock power. These capabilities remove the unpredictability
from the physical implementation process, which affect the cost, performance, and time-to-market of low
power ICs.

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