Documente Academic
Documente Profesional
Documente Cultură
August 2014
Altera Stratix IV FPGA Interface for LTM9011 ADC
with LVDS Outputs
Gary Yu
Summary
This document shows how to interface a Linear Technology LTM9011 8-channel, simultaneous sampling 14-bit
analog-to-digital converter (ADC) with high speed serial
low voltage differential signaling (LVDS) to Altera Stratix
IV FPGAs utilizing the dedicated I/O functions of the FPGA
family.
Introduction
This document details the interface of an Altera Stratix
IV FPGA to a high speed LTM9011 ADC from Linear
Technology. Implementation is demonstrated via the
LTM9011 demo board DC1884A and a Stratix IV GX FPGA
development board contained in the Stratix IV GX FPGA
development kits.
To learn more detailed information regarding the Stratix
IV GX FPGA development kits and Linear Technology
DC1884A, refer to:
www.altera.com/products/devkits/altera/kit-siv-gx.html
http://www.linear.com/demo/DC1884A
1.8V
VDD
1.8V
OVDD
S/H
14-BIT
ADC CORE
OUT1A
CHANNEL 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
OUT2A
CHANNEL 8
ANALOG
INPUT
ENCODE
INPUT
S/H
OUT1B
OUT2B
DATA
SERIALIZER
CHANNEL 1
ANALOG
INPUT
SERIALIZED
LVDS
OUTPUTS
OUT8A
14-BIT
ADC CORE
OUT8B
DATA
CLOCK
OUT
PLL
FRAME
GND
GND
AN147 F01
AN147-1
N+1
N
tENCH
ENC
tENCL
ENC+
tSER
DCO
DCO+
tFRAME
FR
FR+
OUT#A
OUT#A+
OUT#B
OUT#B+
tDATA
tSER
tPD
tSER
D5
D3
D1
D13 D11 D9
D7
D5
D3
D1
D13 D11 D9
D4
D2
D0
D12 D10 D8
D6
D4
D2
D0
D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
AN147 F02
tAP
ns
tENCL
100
ns
tENCH
100
ns
tSER
tDATA
0.35
1
0.5
0.65
ns
ns
tFRAME
FR to DCO Delay
0.35
0.5
0.65
ns
tPD
Propagation Delay
2.7
3.1
3.5
ns
AN147-2
USB HOST
DC590B SPI
CONTROLLER
FPGA
SYSCLK
50MHz
OSCILLATOR
dco_d_p/n
fr_d_p/n
out4a_p/n
out4b_p/n
out5a_p/n
out5b_p/n
out6a_p/n
out6b_p/n
out7a_p/n
out7b_p/n
cllclk
cllctrl
clldata
SPI INTERFACE
SEAF CONNECTOR
LCD
INTERFACE
dco_u_p/n
fr_u_p/n
out0a_p/n
out0b_p/n
out1a_p/n
out1b_p/n
out2a_p/n
out2b_p/n
out3a_p/n
out3b_p/n
JTAG
INTERFACE
HSMC CONNECTOR
LCD MODULE
DCOA
FRA
OUT1A
OUT1B
OUT4A
OUT4B
OUT5A
OUT5B
OUT8A
OUT8B
DCOB
FRB
OUT2A
OUT2B
OUT3A
OUT3B
OUT6A
OUT6B
OUT7A
OUT7B
ENC
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
125MHz
CLOCK
SOURCE
8 CHANNELS
ANALOG
SOURCE
LTM9011
HSMC CONNECTOR
EMBEDDED
USB BLASTER
AN147 F03
Transmitter serializer
Receiver deserializer
Data realignment
The direction of true differential I/O buffers is not configurable. The specific pin only supports one direction
of data flow.
an147f
AN147-3
DESERIALIZER
SERIAL
DATA
BIT SLIP
MUX
SERIAL
DATA
SYNCHRONIZER
SERIAL
DATA
MUX
DPA_rx_inclock
FPGA FABRIC
DPA_rx_enable
LVDS_rx_enable
LVDS_rx_inclock
DATA INPUT
BUFFER
DPA CIRCUITRY
8 SERIAL LVDS
CLOCK PHASES
PLL
CLOCK INPUT
BUFFER
rx_syncclock
P PAD
N PAD
P PAD
N PAD
AN147 F04
AN147-4
D0
D1
D2
D3
D4
Dn
0
45
90
135
180
225
270
315
0.125tVCO
AN147 F05
tVCO
Figure 5. DPA Clock Phase to Serial Data Timing Relationship tVCO Equal to tSER
The ALTLVDS MegaWizard Plug-In Manager software allows the user to choose whether to implement the LVDS
interface via an external PLL or automatically provide the
PLL. With the Use External PLL option disabled (Figure6),
the tool automatically creates an LVDS receiver with a
PLL. The advantage of this solution is that the clock tree
implementation and timing constraints are relatively easy.
The disadvantage is that this PLL cant be customized
an additional PLL may be required to divide an external
clock source from the LTM9011 by 8 and generate other
necessary clock sources for FPGA logic usage.
With the Use External PLL option enabled (Figure 7), the
tool generates an LVDS receiver without a PLL. A dedicated
PLL must be configured to generate all clock sources for
the LVDS receiver to exactly meet its timing requirements
and those for other FPGA logic. The advantage of this
method is that we have control over the PLL settings, such
as dynamically reconfiguring the PLL to support different
data rates, dynamic phase shift, and other settings.
Multiple LTM9011 Concept
Figure 8 shows a solution for multiple LTM9011s. To
implement the LVDS receivers for LTM9011 A and B in
this application, several components on the Stratix IV GX
FPGA development board come into play, including HSMC
an147f
AN147-5
16 BITS CHANNEL 2
DATA BUS
16 BITS CHANNEL 3
DATA BUS
2 FRAME STREAMS
16 BITS CHANNEL 4
DATA BUS
P PAD
P PAD
P PAD
P PAD
N PAD
N PAD
16 BITS CHANNEL 5
DATA BUS
16 BITS CHANNEL 6
DATA BUS
DIFFERENTIAL
RECEIVER
16 BITS CHANNEL 7
DATA BUS
16 BITS CHANNEL 8
DATA BUS
DCOA
EXTERNAL
PLL
1/8
INTERNAL
PLL
MUX
FPGA FABRIC
DCOB
N PAD
N PAD
AN147 F06
16 BITS CHANNEL 1
DATA BUS
16 BITS CHANNEL 2
DATA BUS
16 BITS CHANNEL 3
DATA BUS
2 FRAME STREAMS
16 BITS CHANNEL 4
DATA BUS
P PAD
P PAD
P PAD
P PAD
N PAD
N PAD
16 BITS CHANNEL 5
DATA BUS
16 BITS CHANNEL 6
DATA BUS
DIFFERENTIAL
RECEIVER
16 BITS CHANNEL 7
DATA BUS
16 BITS CHANNEL 8
DATA BUS
rx_inclock
rx_enable
8 BITS FRAME A BUS
rx_syncclock
DCOA
EXTERNAL
PLL
MUX
FPGA FABRIC
DCOB
N PAD
N PAD
AN147 F07
an147f
AN147-6
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
N PAD
DCOA
MUX
EXTERNAL
PLL
DCOB
N PAD
LTM9011
N PAD
N PAD
N PAD
DCOA
MUX
EXTERNAL
PLL
LTM9011
N PAD
N PAD
N PAD
DCOA
MUX
EXTERNAL
PLL
DCOB
N PAD
LTM9011
N PAD
N PAD
N PAD
DCOA
EXTERNAL
PLL
MUX
FPGA FABRIC
DCOB
N PAD
DCOB
N PAD
LTM9011
N PAD
N PAD
AN147 F08
AN147-7
Figure 9 shows an alternative multiple-LTM9011 application, this one designed to maximize resource usage.
Generating a super receiver that collects all data and
frame streams from four LTM9011s driven by one PLL,
+-------------------------------------------------------------------------------+
; Fitter Summary;
+-----------------------------------+-------------------------------------------+
; Fitter Status ; Successful - Tue Sep 11 17:01:59 2012
;
; Quartus II Version
; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name ; top_FPGA ;
; Top-level Entity Name ; top_FPGA ;
; Family ; Stratix IV ;
; Device ; EP4SGX230KF40C2 ;
; Timing Models ; Final ;
; 3 %
;
; Logic utilization
; Combinational ALUTs
; 4,153 / 182,400 ( 2 % )
;
; Memory ALUTs
; 0 / 91,200 ( 0 % )
;
; Dedicated logic registers
; 4,466 / 182,400 ( 2 % )
;
; Total registers
; 4466
;
; Total pins
; 190 / 888 ( 21 % )
;
; Total virtual pins
; 0
;
; Total block memory bits
; 8,388,864 / 14,625,792 ( 57 % )
;
; DSP block 18-bit elements
; 0 / 1,288 ( 0 % )
;
; Total GXB Receiver Channel PCS
; 0 / 24 ( 0 % )
;
; Total GXB Receiver Channel PMA
; 0 / 36 ( 0 % )
;
; Total GXB Transmitter Channel PCS ; 0 / 24 ( 0 % )
;
; Total GXB Transmitter Channel PMA ; 0 / 36 ( 0 % )
;
; Total PLLs
; 5 / 8 ( 63 % )
;
; Total DLLs
; 0 / 4 ( 0 % )
;
+-----------------------------------+-------------------------------------------+
an147f
AN147-8
P PAD
P PAD
P PAD
P PAD
P PAD
P PAD
N PAD
DCOA
MUX
EXTERNAL
PLL
FPGA FABRIC
DCOB
N PAD
LTM9011
N PAD
N PAD
N PAD
N PAD
P PAD
P PAD
P PAD
P PAD
LTM9011
LOW
SKEW
CLOCK
BUFFER
N PAD
N PAD
LTM9011
N PAD
N PAD
LTM9011
AN147 F09
AN147-9
SYSCLK
altpll_source2
sclk
configuration
decoder
altcnfig
lcd_d_cn
lcd_wen
lcd_csn
lcd_data
lcdrw_ctrl
lcdfl_ctrl
altbram_addr
bram_clk
clldata
clldata
altmem_ram2
cllctrl
cllclk
altbram_ctrl
altclkctrll
test_long
128 BITS
DATA BUS
altlvds_rx1
P PAD
P PAD
P PAD
P PAD
N PAD
test_longf
2 FRAME STREAMS
16 BITS
FRAME BUS
rx_locked
gtp_rst
bitslip-gen
INTERNAL
PLL
rx_inclk
altpll_source4
dco_u_gen
rx_reset
othclk
pre_clk
pll4_locked
clldclk
1/8
MUX
cllclk
dco_d_gen
N PAD
N PAD
N PAD
AN147 F10
areset
AN147-10
CLOCK
NAME
LOADING
FREQUENCY RATE
UP TO
altpll_source4
rx_inclk
altlvds_rx1
125MHz
altpll_source2
cllclk
output pin
125MHz
othclk
bitslip_gen,
rx_reset
125MHz
pre_clk
test_longf,
test_long, altclkctrl,
altbram_ctrl
125MHz
clldclk
Altclkctrl, clldata
125MHz
sclk
lcdrw_ctrl, lcdfl_
ctrl, altcnfig
500KHz
an147f
AN147-11
6
CH6
5
CH5
4
3
CH4 CH3
Read
0x00
2
CH2
1
CH1
0
CH0
an147f
AN147-12
BIT
Bit Name
MEMSIZE
CHSEL
BIT
RSV
Bit Name
Write
Read/Write
Write
Initial Value
0x70
Initial Value
0x00
RSV: Reserved
0
START
Read/Write
RSV
RSV: Reserved
BIT
MEMSIZE
BUFFER SIZE
Bit Name
8 Samples
Read/Write
Write
16 Samples
Initial Value
0x00
32 Samples
64 Samples
128 Samples
256 Samples
512 Samples
1K Samples
2K Samples
4K Samples
8K Samples
16K Samples
RSV
START
RSV: Reserved
START: Start data collection from J1. 1: Start. Need to
reset to 0 after writing 1 to complete trigger
BIT
Bit Name
FRB
FRA
CAPDONE
CLLDONE
Read/Write
Read
Initial Value
0x00
BSP: Bit-slip generator indicates that the data realignment circuitry has aligned to the word boundary successfully. 1: successful 0: Fail
PLL4LOCK: PLL altpll_source4 is locked. 1: locked
0: unlocked
PLL2LOCK: PLL altpll_source2 is locked. 1: locked
0: unlocked
RXLOCK
PLL2LOCK
PLL4LOCK
BSP
an147f
AN147-13
Bit Name
RSV
Read/Write
Write
Initial Value
0x00
0
RST
RSV: Reserved
DISPLAY
DESCRIPTION
XXX
RDY
FPGA Ready
RST
FPGA Reset
0-7
Channel Selected
ZZZZ
(Samples Counter)
Figure 13. Post Place and Routing Simulation at 125Msps Channel Skew
AN147-14
Operating frequency
an147f
AN147-15
DESCRIPTION
General
Developer Name
Gary Yu
Target Devices
Stratix IV GX FPGA EP4SGX230KF40
Source Code Provided
Yes
Source Code Format
Verilog
Design Uses Code or IP from Existing Reference Design, Application Note,
Yes
3rd party, or Megawizard Software
Simulation
Functional Simulation Performed
Yes
Timing Simulation Performed
Yes
Testbench Provided for Functional and Timing Simulations
Yes
Testbench Format
Verilog
Simulator Software and Version
NCVerilog (64bit) 08.20-s014
SPICE/IBIS Simulations
No
Implementation
Synthesis Software Tools and Version
QUARTUS II v11.0
Implementation Software Tools and Version
QUARTUS II v11.0
Static Timing Analysis Performed
Yes
Hardware Verification
Hardware Verified
Yes
Hardware Platform Used for Verification
DC1884A demo board and Stratix IV GX FPGA Development Board
AN147-16
Connect DC590B J3 and Stratix IV GX FPGA development board J7 to a host PC with USB cables.
Power sequence:
Open a DOS window and from the application directory launch a2psc.exe, which performs the following
routines:
AN147-17
Conclusion
The 1.6Gbps SERDES features of the Altera Stratix IV GX
FPGA are an ideal match for the LTM9011 and other serial
LVDS output analog to digital converters. The architecture
of the ALTLVDS megafunction allows the implementation
of ultra-high speed LVDS receivers under very simple timing constraints. The LVDS receivers can properly capture
high speed serial data streams without input buffer skew
adjustment since the DPA circuitry tracks any dynamic
phase variations between the clock and data.
an147f
AN147-18
www.linear.com