Soft USB Controller Design Challenges

softUSB: 1/00
Revision February 1, 2000
Soft USB Controller Design Challenges

Implementing peripheral solutions for an emerging bus standard such as USB can be challenging. Peripheral developers
must be responsive to external, co-developed events. For
USB, these include functionality with various host platforms
(using different chip sets and BIOS), various releases of the
host's operating system, and a continual evolution of peripheral device classes. A good way to accommodate USB development changes is to create USB controller chips that operate soft, that is from code downloaded from the host
computer into on-chip RAM, rather than using the traditional
ROM approach.
On the surface it may seem an easy matter to download code
over the USB and then execute the code to function as a USB
peripheral device. But the USB Specification allows a device
to enumerate only once, so there is an inherent conflict between the device that downloads code and the resultant device that executes the custom application. This paper describes the problem in detail and outlines the novel solution
embodied in the EZ-USB chip family.
Heres the objectivea soft, single-chip USB peripheral solution. One side of the device receives and sends USB traffic,
while the other side interfaces to the devices peripheral circuitry. Program code and data are stored in volatile RAM,
which is downloaded from the host via the USB channel (see
Figure 1).
When the chip powers on, there is no code in RAM and the
CPU is held in reset. To understand the requirements of a
soft architecture, it is helpful to review the anatomy of a USB
peripheral device from the inside out. Then the special measures required to implement the soft feature will be apparent.
The Basic USB Interface

Inside every USB peripheral is a Serial Interface Engine (SIE)
(see Figure 2). The SIE:
Enhanced
8051
Core
3.3V, 12-MHz,
4-clock cycle
Serializes and deserializes USB data.

Decodes the NRZI format used by USB.
Transfers bytes to and from the device.
Handles bit stuffing.
Checks the USB data for validity using CRC fields.
Handles bus signaling like reset, suspend, and resume.
Re-tries certain USB transfers if errors are encountered.
The SIE is roughly analogous to the UART chip connected to
a serial port. Serial data enters and leaves the SIE, and parallel bytes are delivered to, and accepted from, the peripheral.
However, USB is much more complex than a serial port. The
two examples that follow illustrate some of the added complexity.
What the SIE Does

Heres a simple example of what the SIE does (see Figure 3).
USB traffic is shown at the top, with time traveling from left to
right. The illustrated USB transaction represents a USB Bulk
data transfer.
A USB transaction consists of data packets that are identified
by special codes called Packet IDs (PIDS). The bulk transfer
shown above uses four PID types: OUT, DATA0, DATA1, and
ACK.
The first packet is an OUT token, announcing that the host is
about to send data to the peripheral (USB direction is hostcentric, OUT means host to device). The second packet contains the DATA1 PID followed by a block of bytes labeled Payload Data. The device indicates successful receipt of the
data by sending the ACK PID in the third, handshake packet.
The host then sends another OUT token, this time using the
DATA0 PID, followed by more data, and the devices ACK.
The two data PIDS, DATA0 and DATA1, provide added data
security beyond CRC checking to guard against corrupted
handshake, and to maintain synchronism throughout long
bulk transfers. Bulk data is transferred using alternating
I/O
USB
Function
Traffic
Serial
Interface
Engine
(SIE)
D+
D-
Program
and
Data
RAM
Bytes
USB
Transceiver
Figure 1. The Objective: SOFT
Cypress Semiconductor Corporation
Figure 2. The Basic USB Interface
3901 North First Street
San Jose
CA 95134
408-943-2600
February 1, 2000
softUSB: 1/00
Revision : February 1, 2000
S
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Data Packet
Payload
Data
Serial
Interface
Engine
(SIE)
D+
D-
Payload
Data
A
C
K
USB
Transceiver
Figure 3. What the SIE Does

with the aid of a CPU. Figure 4 shows a protocol layer transaction called a CONTROL transfer.
DATA0/1 PIDS. The host and peripheral maintain data toggle bits that are complemented when data is successfully
sent and acknowledged. If either side fails to read a correct
handshake, it does not flip its data toggle, causing a mismatch
with the next data PID. This initiates a retry. All of this is handled automatically by the SIE.
CONTROL transfers consist of two stages, SETUP and STATUS, and an optional third data stage. This example uses a
data stage. The Intelligence block first decodes the host request using the eight Setup Data bytes from the SIE. In this
example, the host has requested data from the peripheral
(such as a Get_Descriptor request). The Intelligence block
decodes the request from the eight SETUP bytes, retrieves
the requested data from internal memory, constructs packets
of the proper size, and sends them back through the SIE for
USB transmission. After the data has been transferred, the
A USB Control Transfer

Heres a more complex SIE illustration, which demonstrates
processing performed by the USB protocol layer, a layer of
intelligence that uses the SIE to respond to standard USB
requests. The protocol layer can be implemented in logic or
SETUP Stage
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8
A
bytes
T
A Setup
Data
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Data Packet
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H/S Pkt
DATA Stage
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STATUS Stage
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1 6
Data Packet
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Serial
Interface
Engine
(SIE)
Figure 4. A USB Control Transfer
2
8
bytes
Setup
Data
Payload
Data
intelligence
Payload
Data
A
C
K
softUSB: 1/00
Intelligence block commands the SIE to ACK the STATUS

phase to conclude the control transfer.
Table 1. Default Endpoints

Alternate Setting
When a device is first attached to USB, it answers a series of

host requests in a process called enumeration. During enumeration the device tells the host about its capabilities and
requirements. The CONTROL transfer shown in Figure 4 is
typical of the USB traffic during enumeration.
0
Endpoint
Type
Max Packet Size (bytes)
CTL
64
64
64
In a soft controller, the program RAM powers on in an unknown state, so the on-chip CPU is not available to perform
the Intelligence function described above. Therefore, the
SIE must be enhanced to handle enumeration without using
the CPU.
1 IN
INT
16
64
2 IN
BULK
64
64
2 OUT
BULK
64
64
4 IN
BULK
64
64
EZ-USB Enhanced SIE
4 OUT
BULK
64
64
The intelligence to fully enumerate as a USB device is incorporated into the SIE logic (see Figure 5). This Enhanced SIE
contains hard-coded descriptor tables to identify it as an Anchor Generic device. These descriptors instruct the operating system to load the correct driver to operate the device.
The Anchor Generic device contains the following sets of
USB endpoints (Table 1).
6 IN
BULK
64
64
Anchor Chips
Enhanced SIE
Full
Device
Enumeration
Serial
Interface
Engine
(SIE)
6 OUT
BULK
64
64
8 IN
ISO
16
256
8 OUT
ISO
16
256
9 IN
ISO
16
16
9 OUT
ISO
16
16
10 IN
ISO
16
16
10 OUT
ISO
16
16
Having a default set of endpoints simplifies the USB learning

curve, since USB transfers can be programmed and studied
starting with a fully functional USB device.
intelligence
AN2131Q Memory Map

The preceding table of default endpoints (Table 1) is actually
a subset of the 31 endpoints available in the AN2131Q. The
CPU firmware reports the desired endpoints to the host via
descriptor tables, and enables the desired endpoints (see
Figure 6).
Figure 5. EZ-USB Enhanced SIE

1024 Bytes
Isochronous
FIFOS
2000
EZ-USB regs
USB
Endpoint 0 IN
Endpoint 0 OUT
Endpoint 1 IN
Endpoint 1 OUT
Endpoint 2 IN
Endpoint 2 OUT
Endpoint 3 IN
Endpoint 3 OUT
Endpoint 4 IN
Endpoint 4 OUT
Endpoint 5 IN
Endpoint 5 OUT
Endpoint 6 IN
Endpoint 6 OUT
Endpoint 7 IN
Endpoint 7 OUT
1F3F
SOF
1024 Bytes
Isochronous
FIFOS
USB
1024
bytes
Bulk
Endpoint
Buffers
Endpoint 0
Endpoints 1-7
Endpoints 8-15
1B40
control
bulk/interrupt
isochronous
All 31 USB endpoints are

available
6.5K RAM
0000
Figure 6. AN2131Q Memory Map
softUSB: 1/00
Full
Device
Enumeration
Download
& Upload
Code
Anchor Chips
Enhanced SIE
Serial
Interface
Engine
(SIE)
Enhanced
8051
Core
3.3V, 12-MHz,
4-clock cycle
intelligence
Program
and
Data
RAM
Figure 7. Advanced SIE Enumerates and Loads Code
Advanced SIE Enumerates and Loads Code
Final USB Device
Its not enough just to enumerate. The Enhanced SIE must

also download code into on-chip RAM for operation as the
final USB device (Figure 7). The Enhanced SIE accomplishes
this by decoding a vendor-specific request that downloads
code into internal RAM. This request is handled over endpoint
zero, the default control endpoint. The eight set-up bytes that
define the Anchor Download are shown below:
Once the code is loaded and the CPU is brought out of reset,
the final USB device is operational. Now the CPU is in charge.
The CPU handles the USB device requests that were initially
fielded by the enhanced SIE. Because the CPU has access
to the added SIE intelligence, the firmware is simplified. In
effect, the enhanced SIE becomes a high-level engine for
USB requests (Figure 8).
The ReNumeration Process
Byte
Field
Value
Meaning
bmRequest
0x40
Vendor Request, OUT
bRequest
0xA0
Anchor Load
Starting address
Theres a hitch. USB allows a device to enumerate only once.

The three steps shown in Figure 9 accomplish the enumeration that configures the soft USB controller as a loader, capable of downloading the final device personality into internal
RAM. But once the RAM is loaded with the descriptors and
code that define the final device, its too late to connect to USB
as the final device.
Number of Bytes
The device needs to enumerate a second time, or ReNumerate (see Figure 10). Then the final device driver is loaded,
the device contains all firmware and descriptors, and our soft
controller is in business.
wValueL
AddrL
wValueH
AddrH
wIndexL
0x00
wIndexH
0x00
wLengthL
LenL
wLengthH
LenH
Anchor Chips
Enhanced SIE
USB
Function
Traffic
Serial
Interface
Engine
(SIE)
Enhanced
8051
Core
3.3V, 12-MHz,
4-clock cycle
intelligence
intelligence
Program
and
Data
RAM
Figure 8. Final USB Device
I/O
softUSB: 1/00
Host PC
recognizes device
attachment, starts
Enumeration
process
Host PC loads
loader driver,
which loads
firmware and
descriptors into
device from a
software file
Host PC
Your Peripheral Device
EZ-USB Core
provides device
descriptors to
identify the loader
driver.
Figure 9. The Enumeration Process
Host PC
recognizes device
attachment, starts
Enumeration
process
Host PC loads
loader driver,
which loads
firmware and
descriptors into
device from a
software file
Host PC
Enumerates
again , loads
device driver
Host PC
Your Peripheral Device
EZ-USB Core
provides device
descriptors to
identify the loader
driver.
Final USB device .

EZ-USB CPU
services USB and
provides device
functionality
The Magic
Happens
Figure 10. The ReNumeration Process

The magic is simple (see Figure 11). A USB hub detects a
high-speed device by the presence of a 1500 pull-up resistor connected to the D+ line. (The hub has a 15-k pull-down
which keeps the line low when nothing is connected.)
DISCON#
The DISCON# pin either drives to the 3.3V rail or floats, under
control of a CPU register bit. This emulates a physical disconnect and reconnect while maintaining power to the device.
Once reconnected, the USB device enumerates using the
downloaded code and descriptors. The entire enumerateReNumerate process happens in about one second.
1500
To 3.3V Regulator
1
2
3
4
EZ-USB
5V
DD+
GND
Figure 11. The Magic is Simple
softUSB: 1/00
8-byte
SETUP data
buffer
SETUP Stage
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Setup
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Endpoint
FIFO
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Endpoint
FIFO
Descriptor
Data Table
6
DATA Stage
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USB Setup data copied to FIFO
CPU copies FIFO data to RAM, decodes

"Get Descriptor" Request
CPU transfers first packet of data from

memory to endpoint FIFO.
FIFO Data sent in response to USB IN

token
CPU Transfers next packet of data from

memory to endpoint FIFO.
FIFO Data sent in response to USB IN

token
Repeat steps 5-6 as necessary.
Figure 12. Get_DescriptorConventional Method
Get_DescriptorConventional Method
Get_DescriptorEnhanced SIE Method
Once ReNumerated, the CPU can take advantage of the enhanced SIE to simplify the firmware needed to service USB
device requests. Figure 12 illustrates a typical device request
called Get_Descriptor.
Because the enhanced SIE contains logic to handle the

Get_Descriptor request, the CPU can take advantage of this
added hardware to respond to its own requests.
As in the conventional method, the CPU decodes the request,
although it accesses the eight setup bytes directly in memory,
saving the FIFO-to-memory transfer. Then the CPU simply
loads the address of the requested descriptor table into a control register. The Enhanced SIE does the rest (see Figure 13).
Most USB peripheral chips handle the Get_Descriptor in the

manner shown in Figure 12. The CPU transfers the eight setup bytes from an endpoint FIFO to RAM to decode the request (1,2). Then the CPU fetches the requested data from
internal RAM, packetizes it, and loads it into an endpoint FIFO
for USB transmission (3-6). The CPU must keep track of the
three stages of the control transfer, usually maintaining a firmware state machine.
Watch Those VID-PID-DIDs

There are some details to keep straight. In Anchor Generic
mode, six bytes of descriptor information tag the device to
an OS driver. To allow different vendors to customize their
own drivers, a small (16-byte) EEPROM attaches to the EZUSB chip to provide custom VID-PID-DID information (see
Figure 14).
softUSB: 1/00
SETUP Stage
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A E
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D D
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R P
P
Token Packet
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A 8 bytes
T
Setup
A
Data
0
Data Packet
C
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1
6
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8-byte
SETUP data
buffer
A
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K
H/S Pkt
DATA Stage
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Token Packet
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Payload
Data
Data Packet
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H/S Pkt
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Payload
Data
Data Packet
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STATUS Stage
2
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Token Packet
D C
A R
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Data Packet
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Descriptor
Data Table
H/S Pkt
EZ-USB core copies Setup data directly to RAM,

eliminating the FIFO-to-RAM copy step. 8051
decodes the "Get Descriptor" request.
8051 sets pointer to descriptor table in RAM,

EZ-USB core does entire multi-packet transfer.
Figure 13. Get_DescriptorEnhanced SIE Method
EZ-USB
PC
Loads Anchor
Chips Driver
USB
VID = 0547
Product ID (PID)
Device ID (DID)
(a) "Anchor Generic" Enumeration
EZ-USB
PC
Loads Device-Specific
Driver
Vendor ID (VID)
USB
Product ID (PID)
Device ID (DID)
Serial EEPROM
(b) Custom Device Enumeration
Figure 14. Watch Those VID-PID-DIDs
softUSB: 1/00
ISO OUT FIFO
movx a,@dptr
DPTR
FWR#
D[7..0]
External FIFO
or ASIC
Accumulator
ISO IN FIFO
movx @dptr,a
DPTR
FRD#
D[7..0]
External FIFO
or ASIC
Accumulator
Figure 15. AM2131Q Fast Transfer Modes

AN2131Q data bus, and fast strobes FRD# and FWR# are
generated (Figure 15).
AN2131Q Fast Transfer Modes

Its important to insure that the CPU keeps up with USB rates
when it transfers data to and from the peripheral (for example
an external FIFO). A turbo mode monitors transfers between the 8051 accumulator and endpoint FIFOS and buffers.
When enabled, USB data is transferred directly to the
Fast Transfers to an External FIFO

Figure 16 shows an isochronous transfer of 1008 bytes, transferred from an OUT endpoint to an external FIFO, and then
looped back to an IN endpoint.
Figure 16. Fast Transfer to an External FIFO
softUSB: 1/00
Revision: February 1, 2000
Expanding the AN2131Q

The AN2131Q has a non-multiplexed address bus, an 8-bit
data bus, and three 8-bit IO ports. Each IO pin has an alternate function, for example the Fast Read (FRD#) and Fast
Write (FWR#) strobes shown in Figure 16.
PORTA (8)
Alternate Function
OE
PORTB (8)
OUT
PORTC (8)
reg
Pin
PIN
AN2131Q
RD#
WR#
Address (16)
Data (8)
I2 C
Figure 17. Expanding the AN2131Q
Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Soft USB Controller Design Challenges

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