Class 5

CpE358/CS381
Switching Theory and

Logical Design
Class 5
Copyright 2004
Stevens Institute of Technology
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Switching Theory and Logical Design
Summer-1 2004
Today
Fundamental concepts of digital systems (Mano Chapter 1)
Binary codes, number systems, and arithmetic (Ch 1)
Boolean algebra (Ch 2)
Simplification of switching equations (Ch 3)
Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10)
Combinatoric logical design including LSI implementation (Chapter 4)
Hazards, Races, and time related issues in digital design (Ch 9)
Flip-flops and state memory elements (Ch 5)
Sequential logic analysis and design (Ch 5)
Synchronous vs. asynchronous design (Ch 9)
Counters, shift register circuits (Ch 6)
Memory and Programmable logic (Ch 7)
Minimization of sequential systems
Introduction to Finite Automata
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Standard Combinational Circuits in TTL

All part number prefixed by 74, 74S, 74LS, etc.
00, 01, 03, 10, 12, 13, 18,
20, 22, 26, 30, 37, 38, 39,
40
NAND
02, 23, 24, 25, 27, 28, 33
NOR
04, 05, 06, 14, 16
NOT
07, 17
Buffer
08, 09, 11, 15, 21
AND
32
OR
41, 42, 43, 44
4-line to 10-line decoder
45
BCD-to-decimal
46, 47, 48, 49
BCD-to-7-segment
35, 50, 51, 53, 54, 55, 56
AND-OR-Invert
52
AND-OR
60, 61
AND expander
62
AND-OR expander
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Flip-Flops
80, 82, 83,
Adders
81, 84, 89
RAM
85
Magnitude
comparator
86
XOR
87
True/complement
88
ROM
90-116
160-179,
190-199
Counters, S/R,
Latches
138, 139,
148-159,
251-258,
348-359
Decoder, MUX,
Encoders,
Selectors, DeMUX
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Generalized Combinational Circuits

In general, F( ) will represent some high-level function needed for a system
I
n inputs
Combinational
Circuit
O
m outputs
O = (o0 , o1, o2 ,..., om 1 ) = F (I ) = F (i 0 , i1, i 2 ,..., i n 1 )
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Generalized Combinational Circuits

E.g., ASCII to 7-segment decoder needed for a display system
b0
a
ASCII to
7 segment
decoder
ASCII
c
g
b7
O = (a, b, c, d , e, f , g ) = F (B ) = F (b0 , b1, b2 ,..., b7 )
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Analysis vs. Design

Analysis procedure:
Given a logic diagram, find F( )
y
F(x,y,z)
F ( x, y , z ) = x i y + x 'iz
Design procedure:
Given F( ), design a logic circuit that implements F( ) with minimum number of
gates
F ( x, y , z ) = xy + xz '+ xy '+ w = (w ' x ' y '+ xyz )'

wx\yz 00
01
11
10
00
01
11
10
F(x,y,z)
z
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w
x
y
Analysis
Consider this logic diagram what function does it perform?:
a
b
F(a,b,c,d,e,f)
c
d
e
f
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Analysis
a
T1
T2
F(a,b,c,d,e,f)
T3
T4
e
f
Label first level gate outputs
e
f
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1.
Analysis
a
T1
T2
F(a,b,c,d,e,f)
T3
T4
e
f
1.
2.
Label first level gate outputs

Determine Boolean functions
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T1=efa
T2=efb
T3=efc
T4=efd
Analysis
a
T1
T2
F(a,b,c,d,e,f)
T3
T4
e
f
1. Label first level gate outputs

2. Determine Boolean functions
3. Iterate until reaching output
F(a,b,c,d,e,f) = T1 + T2 + T3 + T4
F(a,b,c,d,e,f) = efa + efb + efc + efd
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T1=efa
T2=efb
T3=efc
T4=efd
Analysis
a
T1
T2
F(a,b,c,d,e,f)
T3
T4
e
f
ef
00
01
10
11
F( )
F( ) is a 4 input MUX
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1. Label first level gate outputs

2. Determine Boolean functions
3. Iterate until reaching output
F(a,b,c,d,e,f) = T1 + T2 + T3 + T4
F(a,b,c,d,e,f) = efa + efb + efc + efd
a
b
c
d
T1=efa
T2=efb
T3=efc
T4=efd
Design
Design a 2-line to 4-line decoder with enable
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Create a high-level function definition
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1.
Design
1.
Create a high-level function definition,

determine I/O requirements
B3
A1
B2
B1
A0
B0
E
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Design
2.
B3
A1
1.

Define truth table
B2
B1
A0
B0
E
E
A1
A0
B0
B1
B2
B3
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Design
2.
3.
B3
A1
1.
B2

Define truth table
Derive Boolean functions for each
output
B1
A0
B0
B0 = EA1A0
B1 = EA1A0
B2 = EA1A0
B3 = EA1A0
E
E
A1
A0
B0
B1
B2
B3
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Design
2.
3.
B3
A1
B2
4.
B1
A0
1.
B0
E
E
A1
A0
B0
B1
B2
B3
E
A1
A0

Define truth table
Derive Boolean functions for each
output
Draw the logic diagram and verify
correctness
B0 = EA1A0
B1 = EA1A0
B2 = EA1A0
B3 = EA1A0
B3
B2
B1
B0
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Binary Addition Review

1-bit addition:
+
0*
* carry
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1-bit addition:
+
0*
* carry
As two Boolean functions:
+
sum
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carry

1-bit addition:
+
0*
* carry
As two Boolean functions:
+
sum
carry
sum(a, b ) = a ' b + ab ' = a b
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carry (a, b ) = ab
Half Adder
sum(a, b ) = a ' b + ab ' = a b
a
b
carry (a, b ) = ab
sum(a,b)
carry(a,b)
a
b
HA
sum
carry
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Full Adder
ai
bi
FA
c_ini
c_outi
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sumi
Full Adder
ai
sumi
FA
bi
c_outi
c_ini
a
cin
cout
sum
1
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Full Adder
ab
ai
sumi
FA
bi
c_outi
c_ini
a
cin
cout
sum
00 01 11 10
sum
b
ab
00 01 11 10
carry
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Full Adder
ab
ai
sumi
FA
bi
c_outi
c_ini
a
cin
cout
sum
sum(a, b, ci ) = a b ci
b
ab
a
00 01 11 10
sum
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carry
b c (a, b, c ) = ac + bc + ab
o
i
i
i
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00 01 11 10
Full Adder Implementation

a
b
a
b
HA s
a
b
HA s
c
cout
cin
FA
a
b
ci
co
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FA s
Binary Adder
Multiple Full Adders can be cascaded to create an arbitrary precision adder
An-1 Bn-1
Cn
co FA ci
A2 B2
Cn-1
C3
co FA ci
A1 B1
C2
co FA ci
A0 B0
C1
co FA ci
Sn-1
S2
S1
S0
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C0
Binary Adder
Multiple Full Adders can be cascaded to create an arbitrary precision adder
But there is an accumulation of delay through the carry stages
AN-1 BN-1
CN
co FA ci
A2 B2
CN-1
C3
Sn-1
co FA ci
A1 B1
C2
s
2 XOR
delays
co FA ci
s
A0 B0
C1
co FA ci
C0
s
1 AND + 1 OR
delays
S2
S1
S0
(1 AND + 1 OR
Delays) x (N-1) stages
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Binary Adder Carry Propagation Delay

A/Bin
Calculationk
Calculationk+1
Calculationk
Sum
Calculationk+1
Carryi
Carryi+1
Carryi+2
Calculationk
Calculationk+1
Calculationk
Carryi+3
Calculationk+1
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1 XOR delay ~3 gate delays

1 AND delay ~2 gate delays
1 OR delay ~2 gate delays
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Calculationk
Calculationk+1
Carries in Adders
Consider the 8-bit sum:
01111111
+00000001
10000000
There is a carry at each stage
If the necessary carries could be scanned once in advance of the addition,
incremental delays could be avoided
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Carries in Adders
C4
s
P3
C3
HA
b
G3
P2
G2
HA
b
C2
Carry
Look-ahead
Generator
P
1
C1
HA
b
G1
P0
G0
HA
b
C4
S3
S2
S1
S0
C0
C0
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Review of Binary Subtraction

Define:
B
01001001
-00110101
x=rx
B +1
11001010+1
01001001
+11001011
100010100
73
-53
20
Is there an easy way to do the 2s complement in one step?
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Review of Binary Subtraction

Define:
B
01001001
-00110101
x=rx
B +1
11001010+1
01001001
+11001011
100010100
73
-53
20
Is there an easy way to do the 2s complement in one step?

A3
A2
B3
B2
B = 1s complement A
A1
A0
M (0-plus/1-minus)
B+C0 = 2s complement A
B0
C0
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B1
Adder/Subtractor
An-1
A2
A1
A0
M
Bn-1
C
V
Cn
co FA ci
B2
Cn-1
C3
co FA ci
B1
C2
co FA ci
B0
C1
co FA ci
Sn-1
(sign bit)
S2
S1
S0
C0
If V asserted, overflow has occurred

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Review of Multiplication
Decimal
123
x 45
615
492
5535
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carries
Review of Multiplication
Decimal
Binary
123
x 45
615
492
5535
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carries
101101
x 11001
101101
no carries
000000
(replicate
000000
and
101101
shift)
101101
10001100101
2-bit By 2-bit Binary Multiplication

x
C3
B1
B0
A1
A0
A0B1
A0B0
A1B1
A1B0
C2
C1
B1
B0
A0
C0
A1
C3
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c HA
s
c HA
s
C2
C1
C0
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4-Bit By 3-Bit Binary Multiplier

B3
B2
B1
B0
A0
B3
B2
B1
B0
A1
0
B3
B2
B1
B0
A3
A2
A1
Co
S3
S2
A0
B3
4-bit adder
Co S3
B2
B1
B0
S2
S1
S0
C4
C3
C2
A2
A3
A2
A1
C6
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B2
B1
B0
S0
C1
C0
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C5
A0
B3
4-bit adder
S1
Uses for Decoders

Memory address expansion
A0:N-1
A0:N+2
Bank 0
E
Bank 1
TS
Data_out
TS
E
AN
AN+1
B0
A0
A1
2-bit
to
4-line
E
B1
Bank 2
B2
B3
Bank 3
AN+2
TS
E
E
2-bit
to
4-line
Banks
4-7
Four 2N location
Memories
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TS
2-Line to 4-Line Decoder
A1
A0
B0
B1
B2
B3
E
A1
A0
B3
B2
B1
B0
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3-Line to 8-Line Decoder

A 2N to 22N Decoder can be created from two N to 2N Decoders
A2
A1
A1
A0
A0
E
A1
A0
B7
B2
B6
B1
B5
B0
B4
B3
B3
B2
B2
B1
B1
B0
B0
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B3
Encoder
Encoder performs inverse operation of Decoder
1
A1
A0
B3
B3
B2
B2
B1
B1
B0
A1
F(A0,A1) = (A0,A1)
A0
B0
2-Bit to
4-Line
Decoder
4-Line to
2-Bit
Decoder
F(A0,A1)
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Encoder Truth Table

Inputs
Outputs
D0
D1
D2
D3
D4
D5
D6
D7
x = D4 + D5 + D6+ D7
y = D2 + D3 + D6+ D7
z = D1 + D3 + D5+ D7
What should output be for input (00000000)?
What about (00100100)?
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Priority Encoder
Inputs
Outputs
D0
D1
D2
D3
D4
D5
D6
D7
Output encodes the largest (highest index) input that is 1.

V indicates if there are any 1s in the input
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Multiplexer
I0
I0
I1
I1
Y
I2
I2
I3
I3
S1
S0
B0
I0
I1
I2
I3
00
01
10
11
S1
A0
S0
A1
2-bit
to
4-line
E
B1
B2
B3
S1S0
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Uses for MUXes

Combining multiple information sources onto one channel
I0
I1
I2
I3
00
01
10
11
S1S0
I0
Time A
I1
Time A
I2
Time A
I3
Time A
S1
S0
Y
I0A I1A I2A I3A I0B I1B I2B I3B I0C I1C I2C I3C I0D I1D I2D I3D I0E I1E I2E I3E I0F I1F
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Function Implementation with MUX

With static values I[0:15], this multiplexer implements the truth table shown
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
S3S2S1S0
S2
S1
S0
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
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S3
DEMUX
I
00
01
10
11
Y0
Y0
Y1
Y2
Y3
Y1
Y2
S1S0
Y3
B0
S1
A0
S0
A1
DEMUX performs inverse function

of MUX
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B1
B2
B3
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2-bit
to
4-line
Multiplexing and Demultiplexing Data Steams
Multiple
input
sources
I0
I1
I2
I3
00
01
10
11
Single
communications
channel
I
S1S0
Sequenced
select lines
00
01
10
11
Y0
Y1
Y2
Y3
Reconstituted
output
signals
S1S0
Sequenced
and synchronized
select lines
Most speech signals in the telephone plant is carried on T1 transmission facility:

24 voice channels, each sampled at 8 kHz with 8 bits/channel +
synchronization = 1.544 Mb/s
Multiple T1s are combined to form a T3 line at ~45 Mb/s
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Summary
Fundamental concepts of digital systems (Mano Chapter 1)
Binary codes, number systems, and arithmetic (Ch 1)
Boolean algebra (Ch 2)
Simplification of switching equations (Ch 3)
Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10)
Combinatoric logical design including LSI implementation (Chapter 4)
Hazards, Races, and time related issues in digital design (Ch 9)
Flip-flops and state memory elements (Ch 5)
Sequential logic analysis and design (Ch 5)
Synchronous vs. asynchronous design (Ch 9)
Counters, shift register circuits (Ch 6)
Memory and Programmable logic (Ch 7)
Minimization of sequential systems
Introduction to Finite Automata
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Homework 5 due in Class 7

As always, show all work
Problems 4-1, 4-5 (x=4, y=2, z=1), (A=4, B=2, C=1), 4-6, 4-7
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CpE358/CS381

Switching Theory and

Standard Combinational Circuits in TTL

02, 23, 24, 25, 27, 28, 33

04, 05, 06, 14, 16

08, 09, 11, 15, 21

41, 42, 43, 44

4-line to 10-line decoder

46, 47, 48, 49

35, 50, 51, 53, 54, 55, 56

80, 82, 83,

Generalized Combinational Circuits

O = (o0 , o1, o2 ,..., om 1 ) = F (I ) = F (i 0 , i1, i 2 ,..., i n 1 )

Generalized Combinational Circuits

O = (a, b, c, d , e, f , g ) = F (B ) = F (b0 , b1, b2 ,..., b7 )

Analysis vs. Design

F ( x, y , z ) = xy + xz '+ xy '+ w = (w ' x ' y '+ xyz )'

Label first level gate outputs

Label first level gate outputs

1. Label first level gate outputs

1. Label first level gate outputs

Create a high-level function definition

Create a high-level function definition,

Create a high-level function definition,

Create a high-level function definition,

Create a high-level function definition,

Binary Addition Review

Binary Addition Review

Binary Addition Review

sum(a, b ) = a ' b + ab ' = a b

sum(a, b ) = a ' b + ab ' = a b

Full Adder Implementation

Binary Adder Carry Propagation Delay

1 XOR delay ~3 gate delays

Review of Binary Subtraction

Is there an easy way to do the 2s complement in one step?

Review of Binary Subtraction

Is there an easy way to do the 2s complement in one step?

If V asserted, overflow has occurred

2-bit By 2-bit Binary Multiplication

4-Bit By 3-Bit Binary Multiplier

Uses for Decoders

2-Line to 4-Line Decoder

3-Line to 8-Line Decoder

Encoder Truth Table

Output encodes the largest (highest index) input that is 1.

Uses for MUXes

Function Implementation with MUX

DEMUX performs inverse function

Multiplexing and Demultiplexing Data Steams

Most speech signals in the telephone plant is carried on T1 transmission facility:

Homework 5 due in Class 7

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