[14ELEC17H] VLSI Technology

2014/2015

Module Code: 14ELEC17H

Title: VLSI Technology
Modular weight: 10
Examination weighting: 60 %
Prerequisite modules: 14ELEC05H
Reassessment: No restrictions.
Internal Examiner/Module Leader: Dr. Ihab Adly
Semester taught: One
Key words: CMOS, microelectronics, silicon technology.
Date of latest revision: April 2014
Note: this module specification is based to a greater or lesser extent on Loughborough's
module 06ELC011
Aims
To develop a consistent picture of the processes used in the modern microelectronics
industry; including key steps in manufacturing, physical design constraints and a detailed
view of IC operation. Students will practice VLSI design flow; including entry, simulation
and verification. To introduce new IC technology trends and challenges; including scaling
and power dissipation problems.
Intended Learning Outcomes
Knowledge and understanding
On completion of this module students should be able to:
1. describe modern IC process flow, steps for silicon production
2. define the physical limits that determine the rules constraining IC design;
Subject-specific cognitive skills
On completion of this module students should be able to:
3. recognize the performance of various available IC technologies
4. select design and placement rules to simple circuit production;
Subject-specific practical skills
On completion of this module students should be able to:
5. use industry-standard design software for VLSI IC design;
Key/transferable skills
On completion of this module students should be able to:
6. demonstrate their problem solving skills through mathematical modelling of real
world problems.
Content

introduction to the VLSI industry;

introduction to Mentor Graphics or similar software;
materials in the Semiconductor Industry;
complementary logic and CMOS gates;
the Static CMOS Inverter;
the Dynamic CMOS Inverter;

fabrication steps in the planar CMOS process;

alternative logic styles;
logical effort and transistor sizing;
sequential logic;
design rules/stick diagrams;
memories
VLSI Technology Trends.

Methods of Learning, Teaching and Assessment

Total student effort for the module: 100 hours on average.
The BUE attendance policy applies, refer to current GAR and Student Handbook for further
details.

Teaching & Learning:

Type of session
Lecture
Workshops
Lab Sessions
Private study

Student Effort
Number in the Semester/s
12
6
6
12

Hours per week normally

2
2
2
4

Total hours
24
12
12
48

Assessment:

Assessment Focus

Group (2-3)

Unseen

Exam
Semester

Weight %

Assessment Type

30%

Mini-project using
Mentor Graphics or
alternative CAD
tool

4, 5, 6

Technical
report and
Discussion

10%

In-class Midterm
Exam (individual

1, 2, 3

One hour

60%

Unseen Exam

1, 2, 3

End of S1

Feedback given to students in response to assessed work

Individual written feedback on coursework;
Feedback discussed as part of a laboratory exercises;
Model answers
Developmental feedback generated through teaching activities
Dialogue between students and staff in tutorials and in laboratories

Reading List

Exam/
Written
Coursework
Length

ILOs
Assessed

2 hour

Recommended/Required Reading:

N. Weste and David Harris, "CMOS VLSI Design: A Circuits and Systems
Perspective", Addison Wesley, ISBN: 978-0321547743, 2010.
Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD
Tools, Addison-Wesley, ISBN-13: 978-1926567556, 2009.

Additional References:

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated

Circuits, Prentice Hall, 2nd Edition, ISBN-13: 978-0130909961, 2003.
R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, Wiley-IEEE
Press, 3rd Edition, ISBN-13: 978-0470881323, 2010.
P.E. Allen and D.R. Holdberg, CMOS Analog Circuit Design, 2nd Edition,
Oxford University Press, ISBN: 978-0195116441, 2004.