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LABORATORY
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SPRING 2016
SECTION 0
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INTRODUCTION
Having the lab simulated in PSPICE will save time during the
performance of the lab as it will help you to determine whether or not you have
built the circuit correctly. During the course of the lab your TA will inspect and
grade your PSPICE simulation . You may keep the PSPICE simulation to assist
you in writing the formal lab report, but it must be included in the report when
you hand it in.
Formal Lab Report:
The formal lab report is due to your TA at the beginning of the next lab period and
will contain the following:
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SECTION I
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LAB EQUIPMENT
The Oscilloscope
The oscilloscope is one of the more complex instruments in electronics
labs. Much time can be saved and frustration avoided if care is taken to
thoroughly understand how it works.
The cathode ray tube (CRT) display of the oscilloscope has a tight beam of
accelerated electrons that are scanned to produce light on a phosphor screen. The
input signal controls where the electron beam will scan.
The electron beam needs two voltages to specify its location on the plane
of the CRT screen. The x-coordinate is controlled by the 'time base' section of the
oscilloscope. This section is found on the right side of your instrument. The time
base electronics produce a ramp wave form that causes the electron beam to move
from the left side of the screen to the right. This occurs at the precisely controlled
rate specified on a dial, for example 50 microseconds per centimeter.
The y-coordinate is controlled by the wave form input to either the A or B
channel of the 'vertical amplifier'. This section is usually found on the left side of
oscilloscopes. The 'vertical deflection mode' control determines which of the
inputs (A or B) are displayed. This control also allows the sum of the A and B
vertical deflections to be displayed. Some oscilloscopes provide two methods for
displaying both channels simultaneously. 'Chop' mode switches the electron beam
quickly between the traces on the fly. 'Alt' mode traces one channel completely
and then traces the other channel on the next trigger.
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The Multimeter
The use of the multimeter is straightforward. Be aware that when
measuring current there can be a considerable voltage drop across the meter,
(about .5V). It is more accurate to measure currents in your circuits by measuring
voltage across a known resistance. If the measured parameter exceeds the range
set on the instrument, the display will flash. To correct this just change the range.
Note also that the AC/DC button should be in the correct position to read what is
desired.
SECTION II
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PSPICE REVIEW
PSPICE EXAMPLE
Chapter 6 in Haznedar explores bipolar logic families, the operation of
which form an integral part of the Digital Electronics course. The
Transistor-Transistor Logic (TTL) family is widely used, and the NAND logic
structure is considered to be the most basic. Figure 6.1 in Haznedar illustrates
a two-input NAND gate, reproduced here as Figure II.1. You will see that
PSPICE is a powerful tool as we use it see how this logic gate operates.
Often, when a circuit is constructed it fails to function properly. The
reason could be that it is simply not biased correctly. The DC node voltages
are calculated automatically by PSPICE every time an analysis is performed,
and provided on the PSPICE Output file. This is very useful, as these DC
node voltages can be compared to the measured DC node voltages in the
laboratory to ensure your circuit was built correctly.
When a logic circuit operates, certain discreet input voltage combinations
generate either a logic-high or logic-low output. These combinations are
shown in a truth table. Other important parameters of a logic gate are how
high an input voltage can go yet still be accepted by the circuit as a low input,
and how low an input voltage can go yet still be a high input. This
information is graphically illustrated by a Voltage Transfer Characteristic
(VTC). Examining the output of a logic circuit with varying inputs or finding
the VTC can be accomplished through the use of PROBE, the graphics postprocessor that comes with PSPICE. Once the output file is examined, we will
explore the use of PROBE.
Figure II.1 shows the circuit with the power supply voltage, input voltages,
and node numbers. (Note that the input voltage isolation diodes shown in
Haznedar are not used.)
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5V
4K
1.6K
130
Q4
Q1
D
Q2
VA
VB
Vo
Q3
1K
Figure II.1
PSPICE has many useful commands. Of course, they cannot all be listed
in these few pages, but here are some things to keep in mind:
The .OP statement gives a more detailed operating point output, and is
very useful in troubleshooting circuits.
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Commentary:
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Transient_analysis
With the circuit code typed in the way it appears above, PSPICE
will automatically transfer you to the Transient_analysis option in PROBE.
This option enables you to see the input and output values as if you were
using an oscilloscope. Once in the Transient_analysis screen, select
Add_trace from the menu.
Select or type in V(1) and hit enter. This is the VA input square
wave. Note the peak voltage values track with your VA command line in
your PSPICE code. Select Add_trace again, and add V(2). This is VB,
and you can see that VB's period is twice that of VA. Now add V(10),
your logic gate output. Does the circuit act as a NAND gate should?
What do the spikes at the output that occur at the input voltage polarity
shifts mean? Could this cause trouble if the NAND sent its output to the
input of another gate? How could this be prevented?
Some newer versions of PROBE allow you to add an additional
Y-axis. If you use this option, the output and input signals can be seen on
the same graph more clearly.
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Dc_sweep
The voltage transfer characteristic (VTC) is useful in determining
the noise margin of the gate. For PSPICE to analyze the VTC, some
changes need to be made to the PSPICE code. Comment out the VA
PULSE command with an asterisk, and delete the asterisk on the VA 1 0
DC 5V command line. This will put the VA input at a constant 5 volts.
The .TRAN statement is no longer needed, so comment it out with an
asterisk, then delete the asterisk on the .DC VB 0 5 .01 statement. Now
run the PSPICE analysis again. Once the analysis is complete, PSPICE
will automatically transfer you to the Dc_sweep option in PROBE. Select
Add_trace from the menu.
Select or type in V(10) and hit enter. This is the VTC for the TTL
NAND gate. Use the cursor command to determine the break points on
the curve. Are they different from those on the VTC illustrated in
Figure 6.10 in Haznedar? Why? What parameters of the semiconductors
need to be changed to match the figure?
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SECTION III
LAB EXPERIMENTS
EXPERIMENT 1:
1.1
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Introduction
This lab will familiarize you with the voltage transfer characteristics and
switching times of a BJT inverter. There are two different activities. In the first
activity you will look at the operation of a diode and the capacitances at the p-n
junction. In the second, the operation of a BJT inverter circuit, and different ways
to eliminate delays in input response will be explored.
1.2
Spice Assignment
Using the student version of PSPICE to simulate the lab activities. The
Spice assignment should include the following for each activity:
NOTE: The TIP 31 is not in the PSPICE library. You will have to to model the
TIP 31 using the .MODEL statement. There is a model on the WEB site.
1.3
Lab Activities
ACTIVITY 1:
This activity takes a simple diode circuit (Fig. 1.1) and inputs
several different square waves. As the diode is forward and reverse-biased,
storage and delay times are measured, and from this data diffusion and junction
capacitance are calculated.
1) Connect the circuit as shown in Figure 1.1, and set the voltage levels of the
square wave to:
(a)
ViL = 0V
ViH = 10V
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Using a 100KHz square wave, measure the storage time (Ts) of the
diode, then calculate the storage time constant, and Cd.
2) While maintaining 100KHz , change the voltage levels in the circuit to:
ViL = -10V
ViH = 10V
Measure the Recovery Time (TR), then calculate the recovery time
constant, and Cj.
3) Repeat parts 1 and 2 with (a) 1N4001 and then (b) 6A05 (switch to
10KHz).
ACTIVITY 2:
Start with an input voltage (Vi1) of 0V. Slowly raise Vi1 and measure
Vo1 at 0.2V increments. Stop taking measurements when the
transistor turns on.
Once the transistor turns on, measure the base and collector voltages.
Use these values to calculate the gain B(DC) of the transistor.
Plot Vo1 versus Vi1 and determine VOH, VOL, VIH, VIL, NMH,
and NML.
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2) Now connect the circuit illustrated in Figure 1.2a according to the table
below and input a 10KHz square wave at Vi1. Measure the voltages and
times illustrated in Figure 1.3 and sketch the output voltage waveforms.
(a)
(b)
(c)
RC
RB
ViL
ViH
1K
.1K
.1K
10K
1K
1K
0V
0V
-5V
5V
5V
5V
Measure the voltages and times illustrated in Figure 1.3 and sketch the
output voltage waveforms.
Input a 10KHz square wave with ViL = -5V and ViH = 5V and observe
how the storage time is removed.
Comment on the disappearance of the storage time and the delay time
when the capacitor is added to the circuit.
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10V
Vo2
Ts
1K
0V
914
10V
Td
0V
Figure 1.1
10V
10V
10V
RC1
470
Vi1
VCC
VCC
VCC
RB1
Vo1
RC1
470
914
RB1
Vo1
Vi1
CB
TIP 31
2K
2K
2K
Figure 1.2a
Figure 1.2b
Figure 1.2
Vo1
RB1
Vi1
TIP 31
TIP 31
RC1
470
Figure 1.2c
Vi1
10V
0V
5s
td1
ts1
tf1
tr1
O H 1
Vo1
O L 1
Figure
1.3
Inverter
Timing
Diagram
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Introduction
In this lab you will examine various logic gates using different BJT
topologies, and verify their characteristics. The first two circuits are TTL
(Transistor-Transistor Logic) configurations and are NAND and NOR gates,
respectfully. The final circuit is an ECL (Emitter Coupled Logic) configuration
and both NOR and OR gates are explored.
3.2
Spice Assignment
Using the student version of PSPICE simulate all lab activities. The Spice
assignment should include the following for each activity:
3.3
Lab Activities
ACTIVITY 1:
Verify that the circuit follows the NAND gate truth table.
2) Connect input A to 5V and plot Vo for B=0V to B=3V using 0.2V steps.
Find VOH, VOL, VIH, VIL, NMH, and NML from the resulting VTC.
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3) Simulate 10 loads for VOL by connecting the gate output to VCC through a
200 resistor and find VOL.
4) Simulate 10 loads for VOH by connecting the gate output to ground
through a 270 resistor and find VOH.
ACTIVITY 2:
Verify that the circuit follows the NOR gate truth table.
ACTIVITY 3:
Verify that the circuit follows the NOR gate truth table.
Determine VOH, VOL, VIH, VIL, NMH, and NML from the resulting
voltage characteristic.
ACTIVITY 4:
ECL 2-input OR
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1) Build the ECL, 2-input OR gate illustrated in Figure 3.3 using Q2N3904
BJTs and resistors. VREF = -1.2V
Determine VOH, VOL, VIH, VIL, NMH, and NML from the resulting
voltage characteristic.
Vc c
RB1
4K
RC2
RC4
1.5K
120
Q4
Q1
Q2
To
Loads
Q3
RB3
1K
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Vc c
1.5K
120
4K
4K
OUTPUT
B
1K
300
270
Q4
V1
Q3
Q2
OR
VREF
V2
2K
1.2K
NOR
2K
VE E
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Introduction
This lab will study the voltage transfer characteristics of nMOS and
CMOS inverters. The rise, fall, and propagation delay times for these inverters
will also be explored.
2.2
Spice Assignment
Using the student version of PSPICE simulate only the nMOS portion of
the lab. (The nMOS in the device library of the student version of PSPICE is an
IRF150. There is no CMOS in the device library of the student version .)
The nMOS name must start with an "M", and the general element line is:
MXXX
ND NG NS NB IRF150
Where ND, NG, NS, and NB are the numbers of the drain, ground, source, and
substrate nodes, respectively. The substrate is usually connected to ground
(node "0" (zero) in most PSPICE circuit files).
The PSPICE simulation should contain the following:
2.3
Lab Activities
ACTIVITY 1:
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1) Construct the nMOS inverter circuit illustrated in Figure 2.1 using the
4007 integrated circuit provided, adding a 1K resistor in series with the
input.
Plot the voltage transfer characteristics (Vout versus Vin) for an input
that varies between 0V and 5V.
NMOS Questions:
1. Determine VT from Part 1) of Activity 1.
2. Show the delay due to adding Rg = 1M in the circuit with both of
the transistors and no capacitive load.
3. Show the delay due to adding the load capacitor (CL = 1000pF),
but with no Rg.
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4. Show the delay due to a load capacitor (CL = 1000pF), but with
QSB eliminated.
ACTIVITY 2:
ACTIVITY 3:
In this activity, CMOS NAND, NOR, and XOR logic gates will be
examined, and their parameters explored
1) Using the ECG4007 integrated circuits (illustrated in Figure 2.3), build the
two-input CMOS NAND gate shown in Figure 2.4.
Measure the circuit output (Vout) fall times (tfc) for the following
simultaneous circuit changes :
A 01
NOTE:
B 01
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Measure the circuit output Vout rise time (trc) for the following
situations:
(1)
(2)
A 10
A 10
and
and
B 11
B 10
2) Using the ECG4007 integrated circuits (illustrated in Figure 2.3), build the
three-input CMOS NOR gate shown in Figure 2.5
Measure the circuit output (Vout) rise times (trc) for the following
simultaneous circuit changes :
A 10
C 10
Measure the circuit output Vout fall time (tfc) for the following
situations:
(1)
(2)
B 10
A 01
A 01
B 00
B 01
and
and
C 00
C 01
CMOS Questions:
1. Show the delay due to adding Rg = 1M in the circuit with both of
the transistors and no capacitive load for Activity 2, Part 1).
2. Show the delay due to adding the load capacitor (CL = 1000pF),
but with no Rg for Activity 2.
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VD D = 5 V
5,14
ECG4007
3
4
+
8
12
10
Vo u t
QS B
QS A
Vi n
Figure 2.1
VD D = 5 V
14
13
6
+
+
8
Vi n
Figure 2.2
Vo u t
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DD
14
13
12
11
10
p
n
n
SS
DD
out
SS
24
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V
DD
C
V
out
SS
25
EXPERIMENT 4:
4.1
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Introduction
This lab will study the operation of , and verify the characteristic tables
for, the following logic circuits:
4.2
Spice Assignment
4.3
Lab Activities
ACTIVITY 1:
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S
Q
R
Figure 4.1 SR NOR Latch
S
Q
Q
R
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J Feedback
J
CK
NAND
Latch
R
K
K Feedback
Qn+
Qn
Qn
R'
Q
CK
J n Kn
S'
Qn Q
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5V
5V
5V
2.2K
CLOCK
CLOCK
2.2K
10K
10K
10K
1uF
100
1Y
14
VCC
1A
14
VCC
1A
13
4Y
1B
13
1C
1B
12
4B
2A
12
1Y
2Y
2A
4
5
11
10
4A
3Y
2B
2C
4
5
11
10
3C
3B
2B
3B
2Y
3A
GND
3A
GND
3Y
7402
Inputs
7410
Output
Inputs
Output
1A
14
VCC
1A
14
VCC
1B
13
4B
1B
13
4B
1Y
12
4A
1Y
12
4A
2A
11
4Y
2A
11
4Y
2B
10
3B
2B
10
3B
2Y
3A
2Y
3A
GND
3Y
GND
3Y
7400
Inputs
Output
7408
Inputs
Output
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Introduction
This lab will study the construction and behavior of a Static CMOS
memory RAM cell.
5.2
Lab Activity
ACTIVITY :
Cause the BIT and the BIT signals to be written to the cell by
applying 5 V to the LOAD signal.
Verify that the signal stored at node A is 5V and the signal stored at
node B is 0V. Show your results in a table.
3) Repeat Part 1) but this time set BIT to 0V and BIT to 5V.
Verify that the signals at nodes A and B are opposite of what they were
before. Show your results in a table.
4) In real RAM circuits, the BIT and BIT lines extend across an entire RAM
chip, and have excessive capacitance in them. This is because the BIT
and BIT lines are bi-directional, and are used for both reading from, and
writing to, the cell. One pair of lines services an entire column of 8192
identical cells. There may be as many as 8192 rows of identical cells. A
unique cell is addressed and read by turning on the LOAD signal for its
row and sampling the BIT and BIT signals for its column. The excessive
capacitance is modeled here by attaching the two 1000 pF capacitors to
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each BIT and BIT line. Unfortunately, the capacitance in real circuits is
so severe that when one attempts to read the RAM cell, the voltage levels
of BIT and BIT are drastically degraded.
Attempt to read the RAM cell when it contains a logic "1" (node A is
5V and node B is 0V) by leaving BIT and BIT undriven, and applying
5V to the LOAD signal. (Use the oscilloscope to determine the
voltage levels of BIT and BIT ).
Now read the cell when it contains a logic "0", recording the actual
voltages you get on the BIT and BIT lines.
During read operations on real RAM chips, if the cell contains a logic "1",
the BIT signal will become 2.9V and the BIT signal becomes 2.1V.
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LOAD
5V
A
B
2000 pF
BIT
2000 pF
BIT
Figure 5.1 CMOS Static RAM Circuit Schematic
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DD
14
13
12
11
10
p
n
n
SS
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PARTS LIST
EXPERIMENT
LAB EXP. 1
ANALOG
100
470
1K
2K
10K
1000pF
TIP 31
1N914
SR102
6A05
2N3904
1N4001
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
LAB EXP. 2
LAB EXP. 3
Q2N3904
DN4001
120
270
300
1K
1.5K
2K
4K
(6)
(3)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
LAB EXP. 4
100
2.2K
390
820
33K
10K
1uF
Q2N3904
DN4001
2000pF
120
1K
1.5K
4K
(1)
(2)
(2)
(1)
(1)
(3)
(1)
(6)
(3)
(2)
(1)
(1)
(1)
(1)
LAB EXP. 5
CHIP
ECG4007
(3)
SN7400
SN7402
SN7410
SN7408
(3)
(2)
(1)
(1)
ECG4007
(3)
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TRANSISTORS
2N3904
TIP 31
SR102
1N914
DN4001
6A05
RESISTORS
100
120
270
390
820
33K
300
470
1K
1.5K
2K
2.2K
4K
10K
7
1
2
1
4
1
1
2
2
2
1
1
2
2
5
2
2
5
1
4
CAPACITORS
1uF
1000pF
2000pF
1
5
2
CHIPS
SN7400
SN7402
SN7410
SN7408
6
4
4
4
36