Subrata Mitra

Email: subrata.ufl@gmail.com, Phone: 352­278­3903
Address: 999, SW 16th Avenue, Apt #22, Gainesville-32601, Florida

Objective: To utilize my analytical, problem solving and technical skills as an intern (Summer 2010) and enhance
my technical and professional skills by continuous learning and applications in practical environment.

Education:
Graduate:           Master's in Computer Engineering, 
                             University of Florida, Gainesville  (Expected year for graduation: December, 2010)     
                             GPA 3.9/4.0              
Undergraduate:  Bachelor of Electronics and Telecommunication Engineering
                             Jadavpur University, Kolkata, India (July 2006)
               GPA 9.01/10 First class with Hons.

Technical skills:   
• 7 years experience with C++/STL/C, (2 years with Perl, Tcl, JAVA and UML), SystemC
• Application Development tools:  GCC, GDB/DDD, Microsoft Visual Studio,  CVS, Visual Source Safe, 
Eclipse, MATLAB, Concurrent Versioning System (CVS)
• Hardware description languages: Verilog, VHDL
• Environment: UNIX, Windows
Courses taken: 
• Analysis of Algorithms, Advanced Data Structure, Computer Networks, Mobile networks, Computer 
Architecture and Embedded systems
 
Professional Experience:3 years of experience as software product development as an R&D engineer in EDA.

Dec 2006- July2009 Senior Software Engineer (R&D) 

                                      Atrenta India Pvt. Ltd.  [Electronic Design Automation/Computer Software industry]
     
                    I worked  in the core development team of a CAD product called Genesis. It is a Excel like table based 
      automation software (has around 700k lines of code) written in C++/C and Perl and is used in 
      hardware designing in ESL (Electronic System Level) for System on Chip integration.
• Developed  algorithms for performance optimization and memory optimization.
• Developed the automation process of generation of  I/O multiplexers, top level connectivity in 
RTL(Verilog/VHDL) and automatic manipulation of hardware designing hierarchies preserving 
logical equivalence.
• Implemented Memory Manager.
• Extensively used C/C++, Perl and Tcl for development and DDD or Visual studio for debugging 
in UNIX and Windows environment.
• Creating unit test­cases, worked with testing team to design test cases for integration testing.
• Had a hands on experience of working on Real time SoC Designs in one leading semiconductor
company's design center in France where I was serving as an Applications Engineer on behalf
of my company, Atrenta Inc.
• I received CEE (Continuously Exceeding Expectations) ratings in each and every appraisal 
over 2years and 8 months.

July 2006 – Dec 2006       Consultant in Technology Advisory Services
                                           Price WaterHouse Coopers (PwC)      
• I was responsible for developing and maintaining a Web­Service called “Global Office” which is a 
network of 3 websites linked together which helps users to maintain keep all their Tax related 
information, calculating Taxes through accountants and Submitting returns online. It had almost 3 
million users worldwide.
• I had used Microsoft Technologies (.NET, C#), Oracle­SQL, HTML, Visual Basic, JavaScripts,
XML/XSLT.
• I had the opportunity to learn about various stages and techniques of software modeling for 
complex requirement.
•
June 2005­ July 2005     Summer intern 
            PriceWaterHouse Coopers, Kolkata, India
• I developed software for Mobile networks for finding location of mobile phones without using 
GPS technology. The emphasis was on security and economic issues.
• Used C++/MATLAB and VB for the project.

Projects / Research Work:

1) Developing a Simulator for Memory and Cache for Tomasula based pipeline architecture for
MIPS processors. Programming language used: C++.
MS-course work project for Computer Architecture.
2) B-Tree implementation and measuring its performance for different m values and analysis of
impact of cache misses on the performance. Programming language: C++
MS-cource work project for Advanced Data Structures.
3) Genetic Algorithm based excitation pattern for Time Modulated Linear Array antenna with 
            suppressed sidelobe level (SLL) and sideband level (SBL).  Using C++
            (B.E. Thesis project Microwave/Microstrip Antenna Laboratory Jadavpur University, India)
            Programming language used: C for writing Genetic Algorithm based optimization technique.
                           Mathematical Tool used: MATLAB.
4) Analysis of Self policing mechanism in Profile Cast P2P message sharing mechanism in Mobile
Adhoc Delay Tolerant Network. Developed Simulator in C++ and MATLAB was used.

Publication:
“Linear Antenna Array with Suppressed Sidelobe and Sideband Levels using Time Modulation”
in International conference on Computers and Devices for Communication (CODEC) ­2006
Organized by Institute of Radio Physics and Electronics, University of Calcutta.

Achievements:
• 13th among 600000 students and district topper in Secondary School Certificate Examination.
• Ranked 69th (top 0.3%) in Joint Entrance Examination for Engineering.
• Ranked 162nd (top 0.6%) in Joint Entrance Examination for Medical.
• Received National Merit Scholarship.
• Certified Painter, participated in many painting workshops and won prizes

Recommendations:
http://www.linkedin.com/in/mitrasubrata (3 recommendations)