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TROUBLESHOOTING GUIDE FOR

6120N

BYWilly Chen
TESTING TECHNOLOGY DEPARTMENT / TSSC
APR. 2000

6120N N/B MAINTENANCE


CONTENTS
1. Location Of Connectors & Switches....................................................................2
2. Location Of Major Components.................................. 5
3. Pin Descriptions Of Major Components..................................9
4. Major Chips Description...................................................28
5. Assembly & Disassembly................ ................................................... 32
6. Maintenance Diagnostics ................................................................. 52
7. System Block Diagram ......55
8. Trouble Shooting.............................. .. ......................................56
9. Spare Parts List......................................................................99
10. System Block Diagram & Mainboard Schematics109
I/O Board Schematics
Button Board Schematics
Trans Board Schematics
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6120N N/B MAINTENANCE


1 . Location Of Connectors & Switches (Main Board Top Side)
MAIN BOARD

Rear Side View

Rear Side View

J501 : External speaker connector.


connector.
J502 : External
External microphone connector.
J503 : PS/2 keyboard or mouse connector.

J508

J509

J504 : USB port connector.

PJ501

J501 , J502
J505

J506

J507

J504

J503

J505 : External CRT monitor connector.


J506 : Printer port connector.
J507 : Serial port Connector.
J508 : Port replicator connector.

J1

J2

J509 : TV terminal connector.

VR1

J3

PJ501 : Power jack.

Top Side View


J4
J5

Top Side View

J1 : Backlight and LED indicator connector.


J2 : LVDS LCD panel connector.
J3 : 144 pin 3.3V unbuffer expansion DIMM socket.
J4 : 144 pin 3.3V unbuffer expansion DIMM socket.
J5 : Internal keyboard connector.

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6120N N/B MAINTENANCE


1 . Location Of Connectors & Switches(Main Board bottom Side)
MAIN BOARD

J501 : External speaker connector.


connector.
J502 : External
External microphone connector.

J502 , J501

J503

PJ501 J504

J506

J507

J503 : PS/2 keyboard or mouse connector.


J504 : USB port connector.

J505
J508
J509
J510
BT501

J505 : External CRT monitor connector.


J506 : Printer port connector.
J507 : Serial port Connector.
J508 : Port replicator connector.

J511

J509 : TV terminal connector.


U503
U504

J510 : Fax/modem/voice card connector.


J511 : CPU fan connector.

J513

J513 : CDCD-ROM connector.

Bottom Side View


J514

J514 : Charger & D/D to M/B connector.


J515

J515 : FDD and HDD connector.


PJ501 : Power jack.
U503 : PPGA CPU socket.
U504 : PCI PCMCIA connector.
BT501 : CMOS backup battery.

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6120N N/B MAINTENANCE


1 . Location Of Connectors & Switches
7020 D/D & CHARGE BD
J4
SW2

SW1
J1
J2

J3

J501

J1 : Charger & D/D to M/B connector

SW1 : Touch pad module left button.

J2 : Battery pack connector.

SW2 : Touch pad module right button.

J3 : Left Internal Speaker Out.


J4 : Right Internal Speaker Out.

J501 : Touch pad module connector.

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6120N N/B MAINTENANCE


2. Location Of Major Components(Main Board top Side)
MAIN BOARD
Top Side View

U1 : PACS1284
U2 : ADM3311 SIO driver.
driver.
.
U3 : TPA0202 Audio amplifier.
a

U9 : CS4297 audio AC CODEC device.


MIC1 SW1

U2
SW2

U9
VR1

U3

U11 : CS4280 Audio controller.

U1

U14,U20 : OnOn-board 8MB SGRAM .

U11
U34

U14

U36

U16

U18 : ATI_RAGE_LT_Pro AGP VGA controller.


controller.

U18

U20

U16 : Intel FW82443BX(ZX) north bridge.


bridge.
U21 : W40S11W40S11-02 SDRAM clock buffer.

U21

U22 : W137 Clock synthesizer.

U22

U24 : Intel PIIX4 south bridge.


U29
U25

U24

U25 : TI1225 PCMCIA Cardbus controller.


U29 : PC97338 Super I/O.
U34 : PC87570 Keyboard mouse & battery charge
controller.
controller.

MIC1 : Internal microphone.


SW1 : LCD panel type select.
SW2 : Power on/off switch.
VR1 : Audio volume adjustment.

U36 : Flashable ROM system BIOS.


Notice : When you change the flash ROM,Please remove
the CMOS battery for minutes.
It is to clear the content of CMOS or it would not
boot up after change BIOS. * Page 8.

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6120N N/B MAINTENANCE


2. Location Of Major Components(Main Board bottom Side)
MAIN BOARD

U501 : HSDLHSDL-3600 Infrared Transceiver.


U501

PJ501

U503 : PPGA 370 CPU socket.

BT501

U504 : PCI PCMCIA connector.


BT501 : CMOS backup battery.
U503

U504

Bottom Side View

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6120N N/B MAINTENANCE


2. Location Of Major Components
7020 D/D CHARGE BD
PQ504 PQ502

PU501
PQ505 PQ503
PU502
PQ510
PQ508

SW2

PT1

SW1

PL1

PU501 : SB3052P +3V,+5V,+12V Generator.


PQ502 : NDS9410 NN-Channel Transistor.

PU502 : PulsePulse-widthwidth-modulation Control For


Battery Charge.

PQ503 : FDS6612 NN-Channel Power MOSFET.

PQ508 : SI4435 PP-Channel Power MOSFET.

PQ504 : NDS9410 NN-Channel Transistor.

PQ510 : SI4435 PP-Channel Power MOSFET.

PQ505 : FDS6690 NN-Channel Power MOSFET.

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6120N N/B MAINTENANCE

Top Side View


Flash ROM
U36

*Notice : When you change the flash ROM,Please


remove the CMOS battery for minutes.
It is to clear the content of CMOS . or it would
not boot up after change BIOS.

CMOS battery
BT
501

U504

Bottom Side View

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6120N N/B MAINTENANCE


3. Pin Descriptions Of Major Components
3.1 INTEL Celeron Processor

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6120N N/B MAINTENANCE


3. Pin Descriptions Of Major Components

3.1 INTEL Celeron Processor


S ig n a l

A [ 3 1 :3 ]#

A20M #

Type

I /O

AD S#

I /O

BCLK

BNR#

I /O

B P [ 3 :2 ]#

I /O

B P M [1 :0 ]#

I /O

B P R I#

B SEL

I /O

BR0#

I /O

C PU PR ES#
(P P G A o n ly )

D e s c r ip tio n
T h e A [ 3 1 :3 ] # ( A d d r e s s ) sig n a ls d e fin e a 2 ^ 3 2 -b y te p h y sic a l m e m o r y
a d d re ss sp a c e .
W h e n A D S # is a c tiv e , th e se p in s tr a n sm it th e a d d r e ss o f a tr a n sa c tio n ;
w h e n A D S # is in a c tiv e , th e se p in s tr a n sm it tr a n sa c tio n ty p e
in fo r m a t io n . T h e A [ 3 1 :2 4 ] # s ig n a l s a r e p a r i ty -p r o t e c te d b y th e A P 1 #
p a r ity sig n a l, a n d th e A [ 2 3 :3 ] # sig n a ls a r e p a r ity -p r o te c te d b y th e A P 0 #
p a r ity sig n a l.
O n th e a c tiv e -to -in a c tiv e tr a n sitio n o f R E S E T # , th e p r o c e sso rs sa m p le
th e A [ 3 1 :3 ] # p in s to d e te r m in e th e ir p o w e r-o n c o n fig u r a tio n .
I f th e A 2 0 M # ( A d d r e s s - 2 0 M a s k ) in p u t sig n a l is a sse r te d , th e In te l
C e l e r o n p r o c e s s o r m a s k s p h y s i c a l a d d r e s s b it 2 0 ( A 2 0 # ) b e fo r e lo o k i n g
u p a lin e in a n y in te r n a l c a c h e a n d b e fo r e d r iv in g a r e a d /w r ite
t r a n s a c t i o n o n t h e b u s . A s s e r t i n g A 2 0 M # e m u l a t e s t h e 8 0 8 6 p r o c e s s o r 's
a d d r e ss w r a p -a r o u n d a t th e 1 M B b o u n d a r y.
A sse r tio n o f A 2 0 M # is o n ly su p p o r te d in re a l m o d e .
A 2 0 M # is a n a sy n c h r o n o u s sig n a l. H o w e v e r, to e n su r e r e c o g n itio n o f
th is sig n a l fo llo w in g a n I /O w r ite in str u c tio n , it m u st b e v a lid a lo n g
w ith th e T R D Y # a sse r tio n o f th e c o r r e sp o n d in g I /O W r ite b u s
tr a n sa c tio n .
T h e A D S # ( A d d r e s s S t r o b e ) sig n a l is a sse r te d to in d ic a te th e v a lid ity
o f th e tr a n s a c tio n a d d r e ss o n th e A [3 1 :3 ] # p in s. A ll b u s a g e n ts o b se r v e
th e A D S # a c tiv a tio n to b e g in p a r ity c h e c k in g , p r o to c o l c h e c k in g ,
a d d r e s s d e c o d e , in t e r n a l s n o o p , o r d e fe r r e d r e p l y I D m a t c h o p e r a t io n s
a sso c ia te d w ith th e n e w tr a n sa c tio n .
T h e B C L K ( B u s C l o c k ) s ig n a l d e te r m i n e s th e b u s fr e q u e n c y . A l l I n te l
C e le r o n p r o c e s so r sy ste m b u s a g e n ts m u st r e c e iv e th is sig n a l to d r iv e
th e ir o u tp u ts a n d la tc h th e ir in p u ts o n th e B C L K r isin g e d g e .
A ll e x te r n a l ti m i n g p a r a m e te r s a r e s p e c i fi e d w i th r e s p e c t to th e B C L K
sig n a l.
T h e B N R # ( B lo c k N e x t R e q u e s t ) sig n a l is u se d to a sse r t a b u s sta ll b y
a n y b u s a g e n t w h o is u n a b le to a c c e p t n e w b u s tr a n sa c tio n s. D u r in g a
b u s sta ll, th e c u r r e n t b u s o w n e r c a n n o t issu e a n y n e w tr a n sa c tio n s.
S in c e m u ltip le a g e n ts m ig h t n e e d to r e q u e st a b u s s ta ll a t th e sa m e tim e ,
B N R # is a w ir e -O R sig n a l w h ic h m u s t c o n n e c t th e a p p r o p ria te p in s o f
a ll I n te l C e le ro n p r o c e ss o r sy ste m b u s a g e n ts. I n o r d e r to a v o id
w ir e -O R g litc h e s a sso c ia te d w ith s im u lta n e o u s e d g e tr a n sitio n s d r iv e n
b y m u l tip le d r iv e r s , B N R # i s a c t iv a t e d o n s p e c i fi c c l o c k e d g e s a n d
sa m p le d o n sp e c ific c lo c k e d g e s.
T h e B P [ 3 :2 ] # ( B r e a k p o in t ) s ig n a ls a r e o u t p u t s fr o m th e p r o c e s s o r t h a t
in d ic a te th e sta tu s o f b r e a k p o in ts .
( B r e a k p o in t M o n it o r ) sig n a ls a r e b r e a k p o in t a n d p e r fo r m a n c e
m o n ito r sig n a ls. T h e y a r e o u tp u ts fro m th e p r o c e sso r w h ic h in d ic a te th e
sta tu s o f b r e a k p o in ts a n d p r o g r a m m a b le c o u n te r s u se d fo r m o n ito r in g
p r o c e s s o r p e r fo r m a n c e .
T h e B P R I# ( B u s P r io r it y R e q u e s t ) sig n a l is u se d to a r b itr a te fo r
o w n e r sh ip o f th e I n te l C e le r o n p r o c e sso r sy ste m b u s.
O b s e r v in g B P R I # a c tiv e (a s a s se r te d b y th e p r io r ity a g e n t) c a u se s a ll
o th e r a g e n ts to sto p issu in g n e w r e q u e sts, u n le ss s u c h r e q u e sts a r e p a r t
o f a n o n g o in g lo c k e d o p e r a tio n . T h e p r io r ity a g e n t k e e p s B P R I #
a sse r te d u n til a ll o f its r e q u e sts a re c o m p le te d , th e n r e le a se s th e b u s b y
d e a sse r tin g B P R I # .
T h is sig n a l in d ic a te s th e s y ste m b u s fr e q u e n c y su p p o r te d b y th e
p r o c e s s o r. A l o g i c l o w i n d i c a t e s a h o s t b u s f r e q u e n c y o f 6 6 M H z .
T h e B R 0 # ( B u s R e q u e s t ) p in d r iv e s th e B R E Q [ 0 ] # sig n a l in th e
s y s t e m . D u r in g p o w e r-u p c o n fi g u r a ti o n , t h e c e n tr a l a g e n t a s s e r ts th e
B R E Q 0 # b u s sig n a l in th e sy ste m to a ss ig n th e sy m m e tr ic a g e n t I D to
t h e p r o c e s s o r. T h e p r o c e s s o r s a m p l e s i t s B R 0 # p i n o n t h e
a c t i v e - t o - i n a c t i v e t r a n s i t i o n o f R E S E T # t o o b t a i n i t s s y m m e t r i c a g e n t
I D . T h e p ro c e sso r a sse r ts B R 0 # to re q u e s t th e sy s te m b u s.
T h e C P U P R E S # sig n a l p r o v id e s th e a b ility fo r a sy ste m b o a r d to d e te c t
t h e p r e s e n c e o f a p r o c e s s o r. T h i s p i n i s a g r o u n d o n t h e p r o c e s s o r
in d ic a tin g to th e sy ste m th a t a p r o c e sso r is in sta lle d .

S ig n a l T y p e
D [ 6 3 :0 ]#

I/O

DBSY#

I/O

DEFER#

DRDY#

I/O

FERR#

FLUSH#

H IT # ,
H IT M #

I/O

IE R R #

IG N N E #

IN IT #

D e s c r ip tio n
T h e D [ 6 3 :0 ] # ( D a t a ) s ig n a ls a r e th e d a ta s ig n a ls . T h e s e s i g n a ls p ro v i d e
a 6 4 -b it d a ta p a th b e t w e e n th e I n t e l C e le ro n p r o c e s s o r s y s te m b u s
a g e n ts , a n d m u s t c o n n e c t th e a p p r o p ri a te p i n s o n a ll s u c h a g e n t s . T h e
d a t a d r i v e r a s s e r t s D R D Y # t o i n d i c a t e a v a l i d d a t a t r a n s f e r.
T h e D B S Y # ( D a ta B u s B u s y ) s i g n a l i s a s s e r te d b y t h e a g e n t
r e s p o n s ib le f o r d r iv in g d a ta o n th e I n te l C e le ro n p r o c e s s o r s y s te m b u s
to in d ic a te th a t th e d a ta b u s i s in u s e . T h e d a ta b u s is r e le a s e d a fte r
D B S Y # is d e a s s e r te d .
T h e D E F E R # s ig n a l is a s s e r t e d b y a n a g e n t to in d ic a te th a t a
tr a n s a c tio n c a n n o t b e g u a ra n t e e d in - o rd e r c o m p le tio n . A s s e rtio n o f
D E F E R # i s n o rm a lly th e r e s p o n s ib il it y o f th e a d d r e s s e d m e m o r y o r I /O
a g e n t.
T h e D R D Y # ( D a ta R e a d y ) s ig n a l i s a s s e rte d b y th e d a ta d r iv e r o n e a c h
d a t a t r a n s f e r, i n d i c a t i n g v a l i d d a t a o n t h e d a t a b u s . I n a m u l t i c y c l e d a t a
t r a n s f e r, D R D Y # m a y b e d e a s s e r t e d t o i n s e r t i d l e c l o c k s .
T h e F E R R # ( F lo a tin g - p o in t E r ro r ) s ig n a l is a s s e r te d w h e n th e
p r o c e s s o r d e t e c t s a n u n m a s k e d f l o a t i n g - p o i n t e r r o r. F E R R # i s s i m i l a r t o
t h e E R R O R # s i g n a l o n t h e I n t e l 3 8 7 c o p r o c e s s o r, a n d i s i n c l u d e d f o r
c o m p a tib ility w ith s y s te m s u s in g M S -D O S * - ty p e f lo a t in g - p o in t e r r o r
re p o rtin g .
W h e n t h e F L U S H # in p u t s ig n a l is a s s e r te d , th e p ro c e s s o r w r ite s b a c k
a ll d a ta in th e M o d i fi e d s t a t e fr o m t h e in t e rn a l c a c h e a n d in v a lid a te s a l l
in te r n a l c a c h e lin e s . A t th e c o m p le tio n o f th i s o p e ra tio n , th e p r o c e s s o r
is s u e s a F lu s h A c k n o w l e d g e tra n s a c ti o n .
T h e p ro c e s s o r d o e s n o t c a c h e a n y n e w d a ta w h i le th e F L U S H # s ig n a l
r e m a in s a s s e r te d .
F L U S H # i s a n a s y n c h r o n o u s s i g n a l . H o w e v e r, t o e n s u r e r e c o g n i t i o n o f
th is s ig n a l fo llo w in g a n I/O w r ite i n s t ru c tio n , it m u s t b e v a l id a lo n g
w i th th e T R D Y # a s s e r tio n o f th e c o r r e s p o n d in g I /O W r it e b u s
tra n s a c tio n .
O n th e a c tiv e - t o -in a c tiv e tr a n s it io n o f R E S E T # , t h e p r o c e s s o r s a m p le s
F L U S H # to d e te r m in e its p o w e r -o n c o n f ig u r a tio n .
T h e H IT # ( S n o o p H i t ) a n d H I T M # ( H it M o d if ie d ) s ig n a ls c o n v e y
tr a n s a c tio n s n o o p o p e r a tio n re s u l ts , A n y s u c h a g e n t m a y a s s e r t b o th
H I T # a n d H I T M # to g e th e r to in d ic a te th a t it r e q u ir e s a s n o o p s t a ll,
w h i c h c a n b e c o n t i n u e d b y r e a s s e r t i n g H I T # a n d H I T M # t o g e t h e r.
T h e I E R R # ( I n t e r n a l E r r o r ) s i g n a l i s a s s e r te d b y a p r o c e s s o r a s th e
r e s u l t o f a n i n t e r n a l e r r o r. A s s e r t i o n o f I E R R # i s u s u a l l y a c c o m p a n i e d
b y a S H U T D O W N t ra n s a c t io n o n th e I n te l C e le ro n p r o c e s s o r s y s te m
b u s . T h is t ra n s a c t io n m a y o p tio n a lly b e c o n v e rt e d to a n e x te r n a l e r r o r
s ig n a l (e .g ., N M I) b y s y s te m c o re lo g ic .
T h e p ro c e s s o r w i ll k e e p IE R R # a s s e r t e d u n til t h e a s s e r tio n o f R E S E T # ,
B IN IT # , o r IN IT # .
T h e I G N N E # ( I g n o r e N u m e r ic E r r o r ) s ig n a l i s a s s e r te d t o f o r c e th e
p r o c e s s o r to i g n o re a n u m e r ic e r ro r a n d c o n t in u e to e x e c u te n o n c o n tr o l
f lo a t in g - p o in t in s tru c tio n s .I f I G N N E # is d e a s s e rte d , t h e p r o c e s s o r
g e n e r a te s a n e x c e p t io n o n a n o n c o n tr o l f lo a t in g - p o in t in s tru c tio n i f a
p r e v i o u s f l o a t i n g - p o i n t i n s t r u c t i o n c a u s e d a n e r r o r.
I G N N E # h a s n o e ff e c t w h e n th e N E b it in c o n tro l re g is t e r 0 is s e t .
I G N N E # i s a n a s y n c h r o n o u s s i g n a l . H o w e v e r, t o e n s u r e r e c o g n i t i o n o f
th is s ig n a l fo llo w in g a n I/O w r ite i n s t ru c tio n , it m u s t b e v a l id a lo n g
w i th th e T R D Y # a s s e r tio n o f th e c o r r e s p o n d in g I /O W r it e b u s
tra n s a c tio n .
T h e I N I T # ( I n it ia liz a t io n ) s ig n a l, w h e n a s s e r te d , re s e t s in te g e r
r e g is te r s in s id e a ll p r o c e s s o r s w ith o u t a ffe c ti n g t h e ir in t e rn a l ( L 1 )
c a c h e s o r flo a tin g -p o in t r e g is t e rs .
E a c h p r o c e s s o r th e n b e g in s e x e c u tio n a t th e p o w e r - o n R e s e t v e c to r
c o n f ig u re d d u rin g p o w e r -o n c o n fig u r a tio n . T h e p ro c e s s o r c o n t in u e s to
h a n d le s n o o p r e q u e s t s d u r in g IN I T # a s s e rtio n . I N I T # is a n
a s y n c h ro n o u s s ig n a l a n d m u s t c o n n e c t th e a p p ro p r ia te p in s o f a l l b u s
a g e n ts .I f I N I T # i s s a m p le d a c tiv e o n t h e a c t iv e to in a c tiv e tr a n s itio n o f
R E S E T # , th e n t h e p r o c e s s o r e x e c u t e s it s B u ilt- in S e lf - T e s t (B IS T ) .

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6120N N/B MAINTENANCE


3.1 INTEL Celeron Processor
S ig n a l T y p e

L I N T [1 :0 ]

LOCK#

EDGCTRL

I/O

P IC C L K

P IC D [1 :0 ]

I/O

PLL1, PLL2
(P P G A o n ly )

PRDY#

PREQ#

PW RGOOD

R E Q [4 : 0 ]#

I/O

D e s c r ip tio n
T h e L I N T [1 :0 ] ( L o c a l A P I C I n te r r u p t ) s ig n a l s m u s t c o n n e c t th e
a p p r o p r ia te p in s o f a ll A P I C B u s a g e n ts , in c l u d in g a ll p ro c e s s o r s a n d
th e c o r e lo g ic o r I/ O A P I C c o m p o n e n t. W h e n th e A P I C is d i s a b le d , th e
L I N T 0 s ig n a l b e c o m e s IN T R , a m a s k a b le in te r r u p t re q u e s t s i g n a l , a n d
L I N T 1 b e c o m e s N M I , a n o n m a s k a b l e in te r ru p t . I N T R a n d N M I a re
b a c k w a rd c o m p a tib le w ith th e s ig n a ls o f th o s e n a m e s o n th e P e n tiu m
p r o c e s s o r. B o t h s i g n a l s a r e a s y n c h r o n o u s .
B o th o f th e s e s ig n a l s m u s t b e s o f tw a re c o n fig u r e d v ia B I O S
p r o g r a m m i n g o f th e A P I C re g is te r s p a c e to b e u s e d e ith e r a s
N M I /I N T R o r L I N T [1 :0 ] . B e c a u s e th e A P I C is e n a b le d b y d e f a u lt a fte r
R e s e t, o p e r a tio n o f th e s e p in s a s L I N T [1 :0 ] is th e d e f a u lt c o n f ig u ra tio n .
T h e L O C K # s ig n a l in d ic a te s to t h e s y s te m t h a t a t ra n s a c tio n m u s t
o c c u r a to m ic a l ly .
F o r a lo c k e d s e q u e n c e o f t ra n s a c tio n s , L O C K # is a s s e rte d f r o m th e
b e g in n in g o f th e fir s t t ra n s a c tio n e n d o f th e la s t tr a n s a c ti o n .
W h e n th e p r io r ity a g e n t a s s e r ts B P R I # to a rb itr a te fo r o w n e r s h ip o f t h e
s y s te m b u s ,it w ill w a it u n til it o b s e rv e s L O C K # d e a s s e r te d . T h is
e n a b le s s y m m e tri c a g e n ts to r e ta in o w n e rs h ip o f th e s y s te m b u s
th ro u g h o u t th e b u s lo c k e d o p e ra ti o n a n d e n s u r e th e a to m ic ity o f lo c k .
T h e E D G C T R L in p u t p ro v id e s A G T L + e d g e c o n tro l a n d sh o u ld b e
p u l l e d u p t o V C C C O R E w i t h a 5 1 5 % r e s i s t o r.
T h e P I C C L K ( A P I C C lo c k ) s ig n a l i s a n in p u t c lo c k t o th e p ro c e s s o r
a n d c o r e lo g ic o r I/ O A P I C w h ic h is r e q u ir e d f o r o p e r a t io n o f a ll
p r o c e s s o r s , c o re lo g ic , a n d I/ O A P I C c o m p o n e n ts o n th e A P I C b u s .
T h e P IC D [1 :0 ] ( A P I C D a ta ) s ig n a ls a re u s e d f o r b id i r e c tio n a l s e ria l
m e s s a g e p a s s in g o n th e A P IC b u s , a n d m u s t c o n n e c t th e a p p ro p ri a te
p in s o f th e I n te l C e le r o n p r o c e s s o r fo r p ro p e r in itia liz a tio n .
A ll In t e l C e le ro n p ro c e s s o r s h a v e in te rn a l a n a lo g P L L c lo c k g e n e ra to r s
th a t re q u ire q u ie t p o w e r s u p p lie s . P L L 1 a n d P L L 2 a r e in p u ts to th e
in t e r n a l P L L a n d s h o u ld b e c o n n e c te d to V C C C O R E th ro u g h a lo w -p a s s
f i l t e r t h a t m i n i m i z e s j i t t e r.
T h e P R D Y ( P r o b e R e a d y ) s ig n a l i s a p ro c e s s o r o u tp u t u s e d b y d e b u g
to o ls to d e t e r m in e p ro c e s s o r d e b u g r e a d i n e s s .
T h e P R E Q # ( P r o b e R e q u e s t ) s ig n a l i s u s e d b y d e b u g to o ls to r e q u e s t
d e b u g o p e r a t io n o f th e p ro c e s s o r s .
T h e P W R G O O D ( P o w e r G o o d ) s i g n a l i s a 2 .5 V t o l e r a n t p r o c e s s o r
in p u t. T h e p r o c e s s o r re q u ir e s th i s s ig n a l to b e a c le a n in d ic a tio n th a t th e
c lo c k s a n d p o w e r s u p p li e s (V C C C O R E , e tc .) a r e s ta b le a n d w ith i n th e ir
s p e c if ic a t io n s . C le a n im p l ie s th a t t h e s i g n a l w il l r e m a in lo w ( c a p a b le o f
s i n k in g le a k a g e c u r r e n t ), w i th o u t g lit c h e s , f r o m th e tim e th a t th e p o w e r
s u p p lie s a re tu rn e d o n u n til th e y c o m e w ith i n s p e c i fi c a tio n .
T h e s ig n a l m u s t th e n t r a n s i ti o n m o n o t o n i c a l ly t o a h i g h ( 2 .5 V ) s t a t e .
il lu s t ra te s th e r e la tio n s h ip o f P W R G O O D to o th e r s y s t e m s ig n a ls .
P W R G O O D c a n b e d r iv e n in a c tiv e a t a n y ti m e , b u t c lo c k s a n d p o w e r
m u s t a g a i n b e s ta b le b e fo re a s u b s e q u e n t r is in g e d g e o f P W R G O O D . I t
m u s t a ls o m e e t t h e m in i m u m p u ls e w id th , a n d b e fo llo w e d b y a 1 m s
R E S E T # p u lse .
T h e P W R G O O D s ig n a l m u s t b e s u p p l ie d to th e p ro c e s s o r ; i t is u s e d to
p r o te c t in t e rn a l c ir c u its a g a in s t v o lta g e s e q u e n c in g is s u e s . It s h o u ld b e
d r iv e n h ig h th r o u g h o u t b o u n d a ry s c a n o p e ra tio n .

T h e R E Q [4 :0 ]# ( R e q u e s t C o m m a n d ) T h e y a r e a s s e r te d b y th e c u r r e n t
b u s o w n e r o v e r tw o c lo c k c y c le s to d e f in e th e c u rr e n tly a c tiv e
tr a n s a c t io n ty p e .

S ig n a l T y p e

RESET#

R S [2 :0 ]#

SLP#

S M I#

STPCLK #

THERM TRI
P#

THERM DN
THERM DP

O
I

TM S

D e s c r ip t io n
A s s e r t in g th e R E S E T # s i g n a l r e s e t s t h e p ro c e s s o r t o a k n o w n s ta t e a n d
i n v a l id a t e s th e L 1 c a c h e w ith o u t w r itin g b a c k a n y o f th e c o n te n ts .
R E S E T # m u s t r e m a in a c tiv e fo r o n e m ic r o s e c o n d f o r a W a r m R e s e t;
f o r a p o w e r -o n R e s e t, R E S E T # m u s t s ta y a c t iv e f o r a t le a s t o n e
m illise c o n d a fte r V C C C O R E a n d C L K h a v e re a c h e d th e ir p ro p e r
s p e c if ic a t io n s . O n o b s e r v i n g a c t iv e R E S E T # , a l l s y s te m b u s a g e n ts w i ll
d e a s s e r t th e i r o u tp u ts w ith in tw o c lo c k s .
A n u m b e r o f b u s s ig n a l s a r e s a m p le d a t th e a c tiv e - to - in a c t iv e tr a n s it io n
o f R E S E T # fo r p o w e r-o n c o n fig u ra tio n .
T h e p ro c e s s o r m a y h a v e its o u t p u ts tris ta t e d v i a p o w e r - o n
c o n f ig u ra tio n . O t h e r w i s e ,i f I N I T # is s a m p l e d a c tiv e d u r in g th e a c t iv e t o - in a c tiv e tr a n s it io n o f R E S E T # , t h e p ro c e s s o r w ill e x e c u t e i ts B u il t- in
S e l f - T e s t ( B I S T ) . W h e t h e r o r n o t B I S T i s e x e c u t e d ,t h e p r o c e s s o r w i l l
b e g in p r o g r a m e x e c u t io n a t th e p o w e r o n R e s e t v e c to r (d e f a u lt
0 _ F F F F _ F F F 0 h ).
T h e R S [2 :0 ] # ( R e s p o n s e S t a t u s ) s i g n a ls a re d r iv e n b y th e r e s p o n s e
a g e n t ( th e a g e n t r e s p o n s ib le fo r c o m p le ti o n o f th e c u rr e n t t r a n s a c tio n ) ,
a n d m u s t c o n n e c t th e a p p ro p r ia t e p i n s o f a ll p r o c e s s o r s y s te m b u s
a g e n ts .
T h e S L P # ( S le e p ) s ig n a l, w h e n a s s e r t e d in S t o p - G r a n t s ta t e , c a u s e s
p r o c e s s o r s to e n te r th e S le e p s t a te . D u r in g S l e e p s ta te , th e p r o c e s s o r
s t o p s p r o v i d i n g in te rn a l c lo c k s ig n a l s to a ll u n its , l e a v in g o n ly th e
P h a s e -L o c k e d L o o p ( P L L ) s ti ll o p e ra t in g .
P r o c e s s o r s in th is s ta te w ill n o t r e c o g n iz e s n o o p s o r in te r r u p ts . T h e
p r o c e s s o r w ill re c o g n iz e o n ly a s s e rt io n s o f th e S L P # , S T P C L K # , a n d
R E S E T # s ig n a l s w h il e in S le e p s ta t e . I f S L P # is d e a s s e r te d , th e
p r o c e s s o r e x its S le e p s ta t e a n d r e tu r n s to S t o p - G r a n t s ta t e , r e s t a r tin g i ts
i n te r n a l c lo c k s ig n a ls to th e b u s a n d A P I C p r o c e s s o r c o r e u n i ts .
T h e S M I# ( S y s t e m M a n a g e m e n t I n t e r r u p t ) s ig n a l i s a s s e rte d
a s y n c h ro n o u s ly b y s y s te m lo g i c . O n a c c e p tin g a S y s te m M a n a g e m e n t
I n t e r ru p t , p ro c e s s o r s s a v e t h e c u r re n t s ta t e a n d e n te r S y s te m
M a n a g e m e n t M o d e (S M M ). A n S M I A c k n o w le d g e tra n s a c tio n is
i s s u e d , a n d t h e p r o c e s s o r b e g in s p r o g r a m e x e c u tio n fr o m th e S M M
h a n d l e r.
T h e S T P C L K # ( S to p C lo c k ) s ig n a l, w h e n a s s e r t e d , c a u s e s p r o c e s s o r s
t o e n t e r a lo w p o w e r S t o p - G r a n t s t a t e . T h e p ro c e s s o r is s u e s a S t o p G r a n t A c k n o w le d g e t r a n s a c tio n , a n d s to p s p r o v id in g in te rn a l c lo c k
s i g n a ls to a ll p r o c e s s o r c o r e u n it s e x c e p t th e b u s a n d A P IC u n i ts . T h e
p r o c e s s o r c o n ti n u e s to s n o o p b u s t ra n s a c t io n s a n d s e rv ic e in t e r ru p t s
w h ile in S to p - G r a n t s ta te . W h e n S T P C L K # is d e a s s e r te d , th e p r o c e s s o r
r e s t a r ts it s i n te rn a l c l o c k to a ll u n i ts a n d re s u m e s e x e c u tio n . T h e
a s s e r ti o n o f S T P C L K # h a s n o e ffe c t o n th e b u s c lo c k ; S T P C L K # i s a n
a s y n c h ro n o u s in p u t .
T h e p ro c e s s o r p ro te c ts it s e lf f ro m c a ta s t r o p h ic o v e r h e a tin g b y u s e o f a n
i n t e r n a l t h e r m a l s e n s o r. T h i s s e n s o r i s s e t w e l l a b o v e t h e n o r m a l
o p e r a tin g t e m p e r a tu r e to e n s u r e th a t t h e r e a r e n o fa ls e trip s . T h e
p r o c e s s o r w ill s to p a l l e x e c u tio n w h e n th e j u n c t io n t e m p e r a tu r e e x c e e d s
a p p r o x im a te ly 1 3 5 . T h i s i s s ig n a le d to th e s y s te m b y th e
T H E R M T R I P # ( T h e r m a l T r ip ) p i n . O n c e a c t iv a t e d , th e s ig n a l r e m a in s
l a tc h e d ,a n d th e p ro c e s s o r s to p p e d , u n til R E S E T # g o e s a c tiv e . T h e r e i s
n o h y s t e r e s is b u ilt i n t o th e th e r m a l s e n s o r it s e lf ; a s lo n g a s th e d ie
t e m p e r a t u re d r o p s b e l o w th e tr ip le v e l, a R E S E T # p u ls e w il l re s e t th e
p r o c e s s o r a n d e x e c u t io n w ill c o n tin u e . I f th e te m p e r a tu r e h a s n o t
d r o p p e d b e lo w th e tr ip le v e l, th e p r o c e s s o r w il l re a s s e rt T H E R M T R I P #
a n d r e m a in s to p p e d .
T h e r m a l D i o d e p - n ju n c ti o n . U s e d to c a lc u la te c o r e te m p e ra tu r e .
T h e r m a l D i o d e p - n ju n c ti o n . U s e d to c a lc u la te c o r e te m p e ra tu r e .
T h e T M S ( T e s t M o d e S e le c t ) s ig n a l i s a J T A G s p e c i fi c a tio n s u p p o rt
sig n a l u se d b y d e b u g to o ls.

-11-

6120N N/B MAINTENANCE


3.1 INTEL Celeron Processor
S ig n a l T y p e

D e s c r ip tio n
T h e T R S T # (T e s t R e s e t) sig n a l re s e ts th e T e st A c c e s s P o rt (T A P ) lo g ic .
I n t e l C e le r o n p ro c e s s o rs re q u i re th is s ig n a l to b e d ri v e n lo w d u ri n g
p o w e r o n R e s e t. A 6 8 0 o h m r e s i s to r is th e s u g g e s te d v a lu e fo r a p u ll
d o w n r e s is to r o n T R S T # .

TRST#

TCK

T h e T C K ( T e s t C lo c k ) s i g n a l p r o v id e s th e c lo c k in p u t fo r th e In te l
C e le r o n p r o c e s s o r T e s t A c c e s s P o rt .

TDI

T h e T D I (T e s t D a ta I n ) s ig n a l t ra n s f e r s s e ri a l t e s t d a ta i n to th e
p r o c e s s o r. T D I p r o v i d e s t h e s e r i a l i n p u t n e e d e d f o r J T A G s p e c i f i c a t i o n
s u p p o rt.

TDO

T h e T D O ( T e s t D a t a O u t ) s ig n a l t ra n s f e r s s e ri a l t e s t d a ta o u t o f t h e
p r o c e s s o r. T D O p r o v i d e s t h e s e r i a l o u t p u t n e e d e d f o r J T A G
s p e c if ic a t io n s u p p o rt.

TRDY#

T h e T R D Y # (T a r g e t R e a d y ) s ig n a l i s a s s e rt e d b y th e ta rg e t to in d ic a te
t h a t i t i s r e a d y t o r e c e i v e a w r i t e o r i m p l i c i t w r i t e b a c k d a t a t r a n s f e r.

V C C 1 .5
(P P G A o n ly )

V C C 2 .5
(P P G A o n ly )

V CC CM OS
(P P G A o n ly )

CORE DET

V ID [4 :0 ]
( S .E . P. P.)
V ID [3 :0 ]
(P P G A )

V R E F [7 :0 ]
(P P G A o n ly )

(P P G A
o n ly ) I

T h e V C C C M O S p in p r o v id e s th e C M O S v o l ta g e fo r u s e b y th e p la tf o r m .
T h e 2 . 5 V m u s t b e p r o v i d e d t o t h e V C C 2 .5 i n p u t a n d 1 .5 V m u s t b e
p r o v i d e d t o t h e V C C 1 .5 i n p u t . T h e p r o c e s s o r r e - r o u t e s t h e 2 . 5 V i n p u t t o
th e V C C C M O S o u tp u t v ia th e p a c k a g e . F u tu r e p r o c e s s o r s r e q u ir in g 1 .5 V
C M O S v o l t a g e l e v e l s w i l l r o u t e t h e 1 . 5 V a t t h e V C C 1 .5 i n p u t t o t h e
V C C C M O S o u tp u t.
T h e V C C C M O S p in p r o v id e s th e C M O S v o l ta g e fo r u s e b y th e p la tf o r m .
T h e 2 . 5 V m u s t b e p r o v i d e d t o t h e V C C 2 .5 i n p u t a n d 1 .5 V m u s t b e
p r o v i d e d t o t h e V C C 1 .5 i n p u t . T h e p r o c e s s o r r e - r o u t e s t h e 2 . 5 V i n p u t t o
th e V C C C M O S o u tp u t v ia th e p a c k a g e . F u tu r e p r o c e s s o r s r e q u ir in g 1 .5 V
C M O S v o l t a g e l e v e l s w i l l r o u t e t h e 1 . 5 V a t t h e V C C 1 .5 i n p u t t o t h e
V C C C M O S o u tp u t.
T h e V C C C M O S p in p r o v id e s th e C M O S v o l ta g e fo r u s e b y th e p la tf o r m .
T h e 2 . 5 V m u s t b e p r o v i d e d t o t h e V C C 2 .5 i n p u t a n d 1 .5 V m u s t b e
p r o v i d e d t o t h e V C C 1 .5 i n p u t . T h e p r o c e s s o r r e - r o u t e s t h e 2 . 5 V i n p u t t o
th e V C C C M O S o u tp u t v ia t h e p a c k a g e . F u tu r e p ro c e s s o r s r e q u ir in g 1 .5 V
C M O S v o l t a g e l e v e l s w i l l r o u t e t h e 1 . 5 V a t t h e V C C 1 .5 i n p u t t o t h e
V C C C M O S o u tp u t.
T h e V C O R E D E T s ig n a l w ill f lo a t f o r 2 .0 V c o r e p r o c e s s o r s a n d w ill b e
g r o u n d e d f o r fu tu r e p r o c e s s o r s w ith a lo w e r c o r e v o l ta g e .
T h e V I D (V o lta g e I D ) p in s c a n b e u s e d to s u p p o rt a u to m a tic s e le c ti o n
o f p o w e r s u p p ly v o lta g e s . T h e s e p in s a r e n o t s ig n a ls , b u t a r e e it h e r a n
o p e n c i r c u i t o r a s h o r t c i r c u i t t o V S S o n t h e p r o c e s s o r. T h e c o m b i n a t i o n
o f o p e n s a n d s h o r t s d e f i n e s t h e v o l t a g e r e q u i r e d b y t h e p r o c e s s o r. T h e
V I D p in s a re n e e d e d to c l e a n ly s u p p o r t v o lta g e s p e c i fic a tio n v a r ia tio n s
o n I n t e l C e le r o n p r o c e s s o rs . S e e T a b le 1 f o r d e fi n i ti o n s o f t h e s e p in s .
T h e p o w e r s u p p ly m u s t s u p p ly th e v o l ta g e th a t is r e q u e s te d b y th e s e
p in s , o r d is a b le its e l f .
T h e s e i n p u t s ig n a ls a re u s e d b y th e A G T L + in p u t s a s a r e f e re n c e
v o lta g e . A G T L + in p u t s a r e d i ff e r e n tia l r e c e i v e r s a n d w ill u s e th is
v o lta g e to d e te r m in e w h e th e r th e s ig n a l i s a lo g i c h i g h o r l o g ic lo w .

-12-

6120N N/B MAINTENANCE


3.2 INTEL 440ZX AGPSET HOST BRIDGE/CONTROLLER(1)
Host Interface Signals
Name
CPURST#

A[31:3]#
HD[63:0]#
ADS#
BNR#

BPRI#

BREQ0#

DBSY#
DEFER#

DRDY#
HIT#

HITM#

HLOCK#

Type
Description
O
CPU Reset. The CPURST# pin is an output from the 82443ZX. The
GTL+ 82443ZXgenerates this signal based on the PCIRST# input (from PIIX4E)
and also the SUSTAT# pin in mobile mode. The CPURST# allows the CPUs
to begin execution in a known state.
I/O Address Bus: A[31:3]# connect to the CPU address bus. During CPU
GTL+ cycles, the A[31:3]# are inputs.
I/O Host Data: These signals are connected to the CPU data bus. Note that the
GTL+ data signals are inverted on the CPU bus.
I/O Address Strobe: The CPU bus owner asserts ADS# to indicate the first of
GTL+ two cycles of a request phase.
I/O Block Next Request: Used to block the current request bus owner from
GTL+ issuing a new request. This signal is used to dynamically control the CPU
bus pipeline depth.
O
Priority Agent Bus Request: The 82443ZX is the only Priority Agent on
GTL+ the CPU bus. It asserts this signal to obtain the ownership of the address
bus. This signal has priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
O
Symmetric Agent Bus Request: Asserted by the 82443ZX when
GTL+ CPURST# is asserted to configure the symmetric bus agents. BREQ0# is
negated 2 host clocks after CPURST# is negated.
I/O Data Bus Busy: Used by the data bus owner to hold the data bus for
GTL+ transfers requiring more than one cycle.
O
Defer: The 82443ZX generates a deferred response as defined by the rules
GTL+ of the 82443ZXs dynamic defer policy. The 82443ZX also uses the
DEFER# signal to indicate a CPU retry response.
I/O Data Ready: Asserted for each cycle that data is transferred.
GTL+
I/O Hit: Indicates that a caching agent holds an unmodified version of the
GTL+ requested line. Also driven in conjunction with HITM# by the target to
extend the snoop window.
I/O Hit Modified: Indicates that a caching agent holds a modified version of the
GTL+ requested line and that this agent assumes responsibility for providing the
line. Also driven in conjunction with HIT# to extend the snoop window.
I
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and
GTL+ ADS#, until the negation of HLOCK# must be atomic, i.e. no PCI or AGP
snoopable access to DRAM is allowed when HLOCK# is asserted by the
CPU.

Name
HREQ[4:0]#

HTRDY#
RS[2:0]#

Type
Description
I/O Request Command: Asserted during both clocks of request phase. In the
GTL+ first clock, the signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second clock, the signals carry
additional information to define the complete transaction type. The
transactions supported by the 82443ZX Host Bridge are defined in the Host
Interface section of this document.
I/O Host Target Ready: Indicates that the target of the CPU transaction is able
GTL+ to enter the data transfer phase.
I/O Response Signals: Indicates type of response according to the following the
GTL+ table:
RS[2:0]
Response type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by 82443ZX)
100
Hard Failure (not driven by 82443ZX)
101
No data response
110
Implicit Writeback
111
Normal data response

Host Signals Not supported by the 82443ZX


Signal
A[35:32]#
AERR#
AP[1:0]#
BINIT#

Function
Address
Address Parity Error
Address Parity
Bus Initialization

DEP[7:0]#
IERR#
INIT#

Data Bus ECC/Parity


Internal Error
Soft Reset

BERR#
RP#
RSP#

Bus Error
Request Parity
Response Parity
Signal

Not Supported By 82443ZX


Extended addressing (over 4 GB)
Parity protection on address bus
Parity protection on address bus
Checking for bus protocol violation and protocol
recovery mechanism
Enhanced data bus integrity
Direct internal error observation via IERR# pin
Implemented by PIIX4E, BIST supported by external
logic.
Unrecoverable error without a bus protocol violation
Parity protection on ADS# and PREQ[4:0]#
Parity protection on RS[2:0]#

-13-

6120N N/B MAINTENANCE


3.2 INTEL 440ZX AGPSET HOST BRIDGE/CONTROLLER (2)
DRAM Interface Signals
Name
RASA[3:0]#
/CSA[3:0]#

RASB[3:0]#
/CSB[3:0]#

CKE[3:2]

CASA[7:0]#
/DQMA[7:0]

GCKE/CKE1

SRAS[A]#

CKE0/FENA

Type
Description
O
Row Address Strobe (EDO): These signals are used to latch the row
CMOS address on the MAxx lines into the DRAMs. Each signal is used to
select one DRAM row.These signals drive the DRAM array directly
without any external buffers.
Chip Select (SDRAM): For the memory row configured with SDRAM
these pins perform the function of selecting the particular SDRAM
components during the active state.
Note that there are 2 copies of RAS# per physical memory row to
improve the loading.
O
CKE is used to dynamically power down inactive SDRAM rows.
CMOS Note that there are 2 copies of CS# per physical memory row to reduce
the loading.
O
Column Address Strobe A-side (EDO): The CASA[7:0]# signals are
CMOS used to latch the column address on the MA[13:0] lines into the
DRAMs of the A half of the memory array. These are active low signals
that drive the DRAM array directly without external buffering.
Input/Output Data Mask A-side (SDRAM): These pins control the A
half of the memory array and act as synchronized output enables during
read cycles and as a byte enables during write cycles.
O
Global CKE (SDRAM): Global CKE is normally used in an 82443BX
CMOS 4 DIMM configuration requiring power down mode for the SDRAM.
External logic must be used to implement this function in an 82443BX.
This function is not supportrd in an 82443ZX.
SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock
Enable is used to signal a self-refresh or power-down command to an
SDRAM array when entering system suspend. CKE is also used to
dynamically power down inactive SDRAM rows. The combination of
SDRAMPWR (SDRAM register) and MMCONFIG (DRAMC register)
determine the functioning of the CKE signals. Refer to the DRAMC
register (Section 3.3.15, "DRAMC-DRAM Control Register (Device
0)" on page 3-19) for more details.
O
SDRAM Row Address Strobe (SDRAM): The SRAS[A]# signal is a
CMOS copy of the same logical SRASx signal (for loading purposes) used to
generate SDRAM command encoded on SRASx/SCASx/WE signals.
O
SDRAM Clock Enable 0 (CKE0). In mobile mode, CKE0 SDRAM
CMOS Clock Enable is used to signal a self-refresh or power-down command
to an SDRAM array when entering system suspend. CKE is also used
to dynamically power down inactive SDRAM rows.
FET Enable (FENA): In a 4 DIMM configuration. FENA is used to
select the proper MD path through the FET switches (refer to Section
4.3, "RAM Interface" on page 4-14 for more details). This function is
not supported in the 82443ZX.

Name
SCAS[A]#

MAA[13:0]
STRAP5
STRAP4
STRAP3
STRAP2
STRAP1
STRAP0
WEA#

MD [63:0]

Type
Description
O
SDRAM Column Address Strobe (SDRAM): The SCAS[A]# signal
CMOS is a copy of the same logical SCASx signal (for loading purposes) used
to generate SDRAM command encoded on SRASx/SCASx/WE signals.
O
Memory Address(EDO/SDRAM): MAA[13:0] are used to provide the
CMOS row and column address to DRAM. Each MAA[13:0] line has a
programmable buffer strength to optimize for different signal loading
conditions.
STRAP[5:0] are described in Table 2-10, Strapping Options.

O
Write Enable Signal (EDO/SDRAM): WE# is asserted during writes
CMOS to DRAM. The WE# lines have a programmable buffer strength to
optimize for different signal loading conditions.
I/O
Memory Data (EDO/SDRAM): These signals are used to interface to
CMOS the DRAM data bus.

Primary PCI Interface Signals


Name
AD[31:0]

DEVSEL#

FRAME#

IRDY#

Type
Description
I/O PCI Address/Data: These signals are connected to the PCI address/data
PCI bus. Address is driven by the 82443ZX with FRAME# assertion, data is
driven or received in the following clocks. When the 82443ZX acts as a
target on the PCI Bus, the AD[31:0] signals are inputs and contain the
address during the first clock of FRAME# assertion and input data (writes)
or output data (reads) on subsequent clocks.
I/O Device Select: Device select, when asserted, indicates that a PCI target
PCI device has decoded its address as the target of the current access. The
82443ZX asserts DEVSEL# based on the DRAM address range or AGP
address range being accessed by a PCI initiator. As an input it indicates
whether any device on the bus has been selected.
I/O Frame: FRAME# is an output when the 82443ZX acts as an initiator on the
PCI PCI Bus. FRAME# is asserted by the 82443ZX to indicate the beginning
and duration of an access. The 82443ZX asserts FRAME# to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is negated, the transaction is in the final data
phase. FRAME# is an input when the 82443ZX acts as a PCI target. As a
PCI target, the 82443ZX latches the C/BE[3:0]# and the AD[31:0] signals
on the first clock edge on which it samples FRAME# active.
I/O Initiator Ready: IRDY# is an output when 82443ZX acts as a PCI initiator
PCI and an input when the 82443ZX acts as a PCI target. The assertion of
IRDY# indicates the current PCI Bus initiator's ability to complete the
current data phase of the transaction.

-14-

6120N N/B MAINTENANCE


3.2 INTEL 440ZX AGPSET HOST BRIDGE/CONTROLLER (3)
Primary PCI Interface Signals
Name
C/BE[3:0]#

PAR

PLOCK#

TRDY#

Type
Description
I/O Command/Byte Enable: PCI Bus Command and Byte Enable signals are
PCI multiplexed on the same pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are
used as byte enables. The byte enables determine which byte lanes carry
meaningful data. PCI Bus command encoding and types are listed below.
C/BE[3:0]#
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
Reserved
0101
Reserved
0110
Memory Read
0111
Memory Write
1000
Reserved
1001
Reserved
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1101
Reserved (Dual Address Cycle)
1110
Memory Read Line
1111
Memory Write and Invalidate
I/O Parity: PAR is driven by the 82443ZX when it acts as a PCI initiator during
PCI address and data phases for a write cycle, and during the address phase for a
read cycle. PAR is driven by the 82443ZX when it acts as a PCI target
during each data phase of a PCI memory read cycle. Even parity is
generated across AD[31:0] and C/BE[3:0]#.
I/O Lock: PLOCK# indicates an exclusive bus operation and may require
PCI multiple transactions to complete. When PLOCK# is asserted, non-exclusive
transactions may proceed. The 82443ZX supports lock for CPU initiated
cycles only. PCI initiated locked cycles are not supported.
I/O Target Ready: TRDY# is an input when the 82443ZX acts as a PCI initiator
PCI and an output when the 82443ZX acts as a PCI target. The assertion of
TRDY# indicates the target agent's ability to complete the current data phase
of the transaction.

Name
SERR#

STOP#

Type
Description
I/O System Error: The 82443ZX asserts this signal to indicate an error
PCI condition. The SERR# assertion by the 82443ZX is enabled globally via
SERRE bit of the PCICMD register. SERR# is asserted under the following
conditions:
In an ECC configuration, the 82443ZX asserts SERR#, for single bit
(correctable) ECC errors or multiple bit (non-correctable) ECC errors if
SERR# signaling is enabled via the ERRCMD control register. Any ECC
errors received during initialization should be ignored.
The 82443ZX asserts SERR# for one clock when it detects a target abort
during 82443ZX initiated PCI cycle.
The 82443ZX can also assert SERR# when a PCI parity error occurs
during the address or data phase.
The 82443ZX can assert SERR# when it detects a PCI address or data
parity error on AGP.
The 82443ZX can assert SERR# upon detection of access to an invalid
entry in the Graphics Aperture Translation Table.
The 82443ZX can assert SERR# upon detecting an invalid AGP master
access outside of AGP aperture and outside of main DRAM range (i.e. in
the 640k - 1M range or above TOM).
The 82443ZX can assert SERR# upon detecting an invalid AGP master
access outside of AGP aperture.
The 82443ZX asserts SERR# for one clock when it detects a target abort
during 82443ZX initiated AGP cycle.
I/O Stop: STOP# is an input when the 82443ZX acts as a PCI initiator and an
PCI output when the 82443ZX acts as a PCI target. STOP# is used for
disconnect, retry, and abort sequences on the PCI Bus.

Primary PCI Sideband Interface Signals


Name
PHOLD#

PHLDA#

PREQ[3:0]#

PGNT[3:0]#

Type
Description
I
PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for
PCI PCI bus ownership. The 82443ZX will flush and disable the CPU-to-PCI
write buffers before granting the PIIX4E the PCI bus via PHLDA#. This
prevents bus deadlock between PCI and ISA.
O
PCI Hold Acknowledge: This signal is driven by the 82443ZX to grant PCI
PCI bus ownership to the PIIX4E after CPU-PCI post buffers have been flushed
and disabled.
I
PCI Bus Request: PREQ[3:0]# are the PCI bus request signals used as
PCI inputs by the internal PCI arbiter.
O
PCI

PCI Grant: PGNT[3:0]# are the PCI bus grant output signals generated by
the internal PCI arbiter.

-15-

6120N N/B MAINTENANCE


3.2 INTEL 440ZX AGPSET HOST BRIDGE/CONTROLLER (4)
Primary PCI Sideband Interface Signals
Name
PHOLD#

PHLDA#

PREQ[3:0]#

PGNT[3:0]#

Type
Description
I
PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for
PCI PCI bus ownership. The 82443ZX will flush and disable the CPU-to-PCI
write buffers before granting the PIIX4E the PCI bus via PHLDA#. This
prevents bus deadlock between PCI and ISA.
O
PCI Hold Acknowledge: This signal is driven by the 82443ZX to grant PCI
PCI bus ownership to the PIIX4E after CPU-PCI post buffers have been flushed
and disabled.
I
PCI Bus Request: PREQ[3:0]# are the PCI bus request signals used as
PCI inputs by the internal PCI arbiter.
O
PCI

Name

Type

ST[2:0]

O
AGP

ADSTB_A

I/O
AGP

ADSTB_B

I/O
AGP
I
AGP

PCI Grant: PGNT[3:0]# are the PCI bus grant output signals generated by
the internal PCI arbiter.

AGP Interface Signals


Name
PIPE#

SBA[7:0]

RBF#

Type
I
AGP

I
AGP

I
AGP

Description
AGP Sideband Addressing Signals 1
Pipelined Read: This signal is asserted by the current master to indicate a
full width address is to be queued by the target. The master queues one
request each rising clock edge while PIPE# is asserted. When PIPE# is
deasserted no new requests are queued across the AD bus. PIPE# is a
sustained tri-state signal from masters (graphics controller) and is an input to
the 82443ZX. Note that initial AGP designs may not use PIPE#.
Sideband Address: This bus provides an additional bus to pass address and
command to the 82443ZX from the AGP master. Note that, when sideband
addressing is disabled, these signals are isolated (no external/internal pullups are required).
AGP Flow Control Signals
Read Buffer Full. This signal indicates if the master is ready to accept
previously requested low priority read data. When RBF# is asserted the
82443ZX is not allowed to return low priority read data to the AGP master
on the first block. RBF# is only sampled at the beginning of a cycle. If the
AGP master is always ready to accept return read data then it is not required
to implement this signal.

SBSTB

GFRAME#

I/O
AGP

Description
AGP Status Signals
Status Bus: This bus provides information from the arbiter to a AGP Master
on what it may do. ST[2:0] only have meaning to the master when its
GGNT# is asserted. When GGNT# is deasserted these signals have no
meaning and must be ignored.
000 Indicates that previously requested low priority read data is being
returned to the master.
001 Indicates that previously requested high priority read data is being
returned to the master.
010 Indicates that the master is to provide low priority write data for a
previously queued write command.
011 Indicates that the master is to provide high priority write data for a
previously queued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the master has been given permission to start a bus
transaction. The master may queue AGP requests by asserting PIPE#
or start a PCI transaction by asserting FRAME#. ST[2:0] are always
an output from the 82443ZX and an input to the master.
AGP Clocking Signals - Strobes
AD Bus Strobe A: This signal provides timing for double clocked data on
the AD bus. The agent that is providing data drives this signal. This signal
requires an 8.2K ohm external pull-up resistor.
AGP Clocking Signals - Strobes
AD Bus Strobe B: This signal is an additional copy of the AD_STBA
signal. This signal requires an 8.2K ohm external pull-up resistor.
Sideband Strobe: THis signal provides timing for a side-band bus. This
signal requires an 8.2K ohm external pull-up resistor.
AGP FRAME# Protocol SIgnals (similar to PCI)2
Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains
deasserted by its own pull up resistor.

-16-

6120N N/B MAINTENANCE


3.2 INTEL 440ZX AGPSET HOST BRIDGE/CONTROLLER (5)
AGP Interface Signals

Clocks, Reset, and Miscellaneous

Name
GIRDY#

Name
HCLKIN

GTRDY#

GSTOP#
GDEVSEL#
GREQ#
GGNT#

GAD[31:0]
GC/BE[3:0]#

GPAR

Type
Description
I/O Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP
AGP compliant master is ready to provide all write data for the current
transaction. Once IRDY# is asserted for a write operation, the master is not
allowed to insert wait states. The assertion of IRDY# for reads indicates that
the master is ready to transfer to a subsequent block (32 bytes) of read data.
The master is never allowed to insert wait states during the initial data
transfer (32 bytes) of a read transaction. However, it may insert wait states
after each 32 byte block is transferred.
(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)
I/O Graphics Target Ready: New meaning. GTRDY# indicates the AGP
AGP compliant target is ready to provide read data for the entire transaction
(when the transfer size is less than or equal to 32 bytes) or is ready to
transfer the initial or subsequent block (32 bytes) of data when the transfer
size is greater than 32 bytes. The target is allowed to insert wait states after
each block (32 bytes) is transferred on both read and write transactions.
I/O Graphics Stop: Same as PCI. Not used by AGP.
AGP
I/O Graphics Device Select: Same as PCI. Not used by AGP.
AGP
I
Graphics Request: Same as PCI. (Used to request access to the bus to
AGP initiate a PCI or AGP request.)
O
Graphics Grant: Same meaning as PCI but additional information is
AGP provided on ST[2:0]. The additional information indicates that the selected
master is the recipient of previously requested read data (high or normal
priority), it is to provide write data (high or normal priority), for a
previously queued write command or has been given permission to start a
bus transaction (AGP or PCI).
I/O Graphics Address/Data: Same as PCI.
AGP
I/O Graphics Command/Byte Enables: Slightly different meaning. Provides
AGP command information (different commands than PCI) when requests are
being queued when using PIPE#. Provide valid byte information during
AGP write transactions and are not used during the return of read data.
I/O Graphics Parity: Same as PCI. Not used on AGP transactions, but used
AGP during PCI transactions as defined by the PCI specification.

PCLKIN

DCLKO
DCLKWR

Type
I
CMOS
I
CMOS

O
CMOS
I
CMOS

PCIRST#

I
CMOS

GCLKIN

I
CMOS
O
CMOS

GCLKO

CRESET#

O
CMOS

TESTIN#

I
CMOS

Description
Host Clock In: This pin receives a buffered host clock. This clock is used
by all of the 82443ZX logic that is in the Host clock domain.
PCI Clock In: This is a buffered PCI clock reference that is synchronously
derived by an external clock synthesizer component from the host clock.
This clock is used by all of the 82443ZX logic that is in the PCI clock
domain.
SDRAM Clock Out: 66 or 100 MHz SDRAM clock reference. It feeds an
external buffer clock device that produces multiple copies for the DIMMs.
SDRAM Write Clock: Feedback reference from the external SDRAM
clock buffer. This clock is used by the 82443ZX when writing data to the
SDRAM array.
Note: See the Design Guide for routing constraints.
PCI Reset: When asserted, this signal will reset the 82443ZX logic. All PCI
output and bi-directional signals will also tri-state compliant to PCI Rev 2.0
and 2.1 specifications.
AGP Clock In: The GCLKIN input is a feedback reference from the
GCLKOUT signal.
AGP Clock Out: The frequency is 66 MHz. The GCLKOUT output is used
to feed both the reference input pin on the 82443ZX and the AGP compliant
device.
Delayed CPU Reset: CRESET# is a delayed copy of CPURST#. This
signal is used to control the multiplexer for the CPU strap signals.
CRESET# is delayed from CPURST# by two host clocks.
Note: This pin requires an external pull-up resistor. If not used, no pull up is
required.
Test Input: This pin is used for manufacturing, and board level test
purposes.
Note: This pin has an internal 50K ohm pull-up.

Power Management Interface


Name
CLKRUN#

BXPWROK

Type
Description
I/OD Primary PCI Clock Run: The 82443ZX requests the central resource
CMOS (PIIX4E) to start or maintain the PCI clock by the assertion of CLKRUN#.
The 82443ZX tristates CLKRUN# upon deassertion of PCIRST# (since
CLK is running upon deassertion of reset). If connected to PIIX4E an
external 2.7K Ohm pull-up is required for Desktop, Mobile requires (8.2k10K) pull-up. Otherwise, a 100 Ohm pull down is required.
I
BX Power OK: BXPWROK input must be connected to the PWROK
CMOS signal that indicates valid power is applied to the 82443ZX.

-17-

6120N N/B MAINTENANCE


3.2 INTEL 440ZX AGPSET HOST BRIDGE/CONTROLLER (6)
Reference Pins
Name
GTLREF[B:A]
VTT[B:A]
VCC
VSS
REF5V
AGPREF

Description
GTL Buffer voltage reference input
GTL Threshold voltage for early clamps
Power pin @ 3.3V
Ground
PCI 5V reference voltage (for 5V tolerant buffers)
External Input Reference

Signal

Register
Name[bit]

MAB8#
STRAP1

DRAMC[5]

STRAP0

none

A[15]#

none

A7#

none

Strapping Options
Signal

Register
Name[bit]

MAB13#
STRAP5

NBXCFG[13]

STRAP4

NBXCFG[2]

STRAP3

STRAP2

PMCR[3]

PMCR[1]

Description
Reserved.
Host Frequency Select: If STRAP5 is strapped to 0, the host bus
frequency is 60/ 66 MHz. If STRAP5 is strapped to 1, the host bus
frequency is 100 MHz. An internal pull-down is used to provide the
default setting of 66 MHz.
In-Order Queue Depth Enable. If STRAP4 is strapped to 0 during
the rising edge of PCIRST#, then the 82442BX will drive A7# low
during the CPURST# deassertion. This forces the CPU bus to be
configured for non-pipelined operation. If STRAP4 is strapped to 1
(default), then the 82443ZX does not drive the A7# low during reset,
and A7# is sampled in default non-driven state (i.e. pulled-up as far
as GTL+ termination is concerned) then the maximum allowable
queue depth by the CPU bus protocol is selected (i.e., 8).
Note that internal pull-up is used to provide pipelined bus mode as a
default.
Quick Start Select. The value on this pin at reset determines which
stop clock mode is used. STRAP3 = 0 (default) for normal stop clock
mode. If STRAP3 = 1 during the rising edge of PCIRST#, then the
82443ZX will drive A15# low during CPURST# deassertion. This
will configure the CPU for Quick Start mode of operation.
Note that internal pull-down is used to provide normal stop clock
mode as a default.
AGP Disable: When strapped to a 1, the AGP interface is disabled,
all AGP signals are tri-stated and isolated. When strapped to a 0
(default), the AGP interface is enabled.
When MMCONFIG is strapped active, we require that
AGP_DISABLE is also strapped active. When MMCONFIG is
strapped inactive, AGP_DISABLE can be strapped active or inactive
but IDSEL_REDIRECT (bit 16 in NBXCFG register) must never be
activated.
This signal has an internal pull-down resistor.

Description
Reserved.
Memory Module Configuration, MMCONFIG: When strapped to
a 1, the 82443ZX configures its DRAM interface in a 430-TX
compatible manner. These
unused inputs are isolated while unused outputs are tri-stated:
RASB[3:0]#/CSB[3:0]#, CKE[3:2], GCKE/CKE1, MAA[13:0],
DCLKO.
When strapped to a 0 (default), the 82443ZX DRAM signal are used
normally. IDSEL_REDIRECT (bit 16 in NBXCFG register) is
programmed by BIOS, before it begins with device enumeration
process. The combination of SDRAMPWR (SDRAMC register) and
MMCONFIG (DRAMC register) determine the functioning of the
CKE signals. Refer to the DRAMC register for more details.
Note that internal pull-down is used to set the DRAM interface to a
normal configuration, as a default.
Host Bus Buffer Mode Select: When strapped 0, the desktop GTL+
66 MHz or 100 MHz host bus buffers are used (default).
When strapped '1' the mobile Low Power GTL+ 66 MHz host bus
buffers are selected.
Note that an internal pull-down is used to set the host bus buffers to a
desktop configuration as a default in the 82443ZX. An external pullup therefore is needed for mobile systems using the 82443BX or
82443DX.
Quick Start Select. The value on A15# sampled at the rising edge of
CPURST# will reflect if the quick start/stop clock mode is enabled
in the processors.
In-order Queue Depth Status. The value on A[7]# sampled at the
rising edge of CPURST# reflects if the IOQD is set to 1 or maximum
allowable by the CPU bus.

-18-

6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (1).
SIGNAL TYPE
DESCRIPTION
I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During
AD[31:0]
the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits).
During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction
consists of an address phase followed by one or more data phases. Little-endian
byte ordering is used. AD[7:0] define the least significant byte (LSB) and
AD[31:24] the most significant byte (MSB). When PIIX4 is a Target, AD[31:0]
are inputs during the address phase of a transaction. During the following data
phase(s), PIIX4 may be asked to supply data on AD[31:0] for a PCI read, or
accept data for a PCI write. As an Initiator, PIIX4 drives a valid address on
AD[31:2] and 0 on AD[1:0] during the address phase, and drives write or latches
read data on AD[31:0] during the data phase.
During Reset: High-Z After Reset: High-Z During POS: High-Z
C/BE#[3:0] I/O BUS COMMAND AND BYTE ENABLES. The command and byte enable
signals are multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# define the bus command. During the data phase
C/BE[3:0]# are used as Byte Enables. The Byte Enables determine which byte
lanes carry meaningful data. C/BE0# applies to byte 0, C/BE1# to byte 1, etc.
PIIX4 drives C/BE[3:0]# as an Initiator and monitors C/BE[3:0]# as a Target.
During Reset: High-Z After Reset: High-Z During POS: High-Z
CLKRUN# I/O CLOCK RUN#. This signal is used to communicate to PCI peripherals that the
PCI clock will be stopped. Peripherals can assert CLKRUN# to request that the
PCI clock be restarted or to keep it from stopping. This function follows the
protocol described in the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low After Reset: Low During POS: High
DEVSEL# I/O DEVICE SELECT. PIIX4 asserts DEVSEL# to claim a PCI transaction through
positive decoding or subtractive decoding (if enabled). As an output, PIIX4
asserts DEVSEL# when it samples IDSEL active in configuration cycles to
PIIX4 configuration registers. PIIX4 also asserts DEVSEL# when an internal
PIIX4 address is decoded or when PIIX4 subtractively or positively decodes a
cycle for the ISA/EIO bus or IDE device. As an input, DEVSEL# indicates the
response to a PIIX4 initiated transaction and is also sampled when deciding
whether to subtractively decode the cycle. DEVSEL# is tri-stated from the
leading edge of PCIRST#. DEVSEL# remains tri-stated until driven by PIIX4 as
a target.
During Reset: High-Z After Reset: High-Z During POS: High-Z
FRAME# I/O CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the
beginning and duration of an access. While FRAME# is asserted data transfers
continue. When FRAME# is negated the transaction is in the final data phase.
FRAME# is an input to PIIX4 when it is the Target. FRAME# is an output when
PIIX4 is the initiator. FRAME# remains tri-stated until driven by PIIX4 as an
Initiator.
During Reset: High-Z After Reset: High-Z During POS: High-Z

SIGNAL TYPE
DESCRIPTION
I/O INITIATOR READY. IRDY# indicates PIIX4 ability, as an Initiator, to
IRDY#
complete the current data phase of the transaction. It is used in conjunction with
TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are
sampled asserted. During a write, IRDY# indicates PIIX4 has valid data present
on AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data. IRDY#
is an input to PIIX4 when PIIX4 is the Target and an output when PIIX4 is an
Initiator. IRDY# remains tri-stated until driven by PIIX4 as a master.
IDSEL

PCIRST#

PHOLD#

PHLDA#

SERR#

INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during


PCI configuration read and write cycles. PIIX4 samples IDSEL during the
address phase of a transaction. If IDSEL is sampled active, and the bus command
is a configuration read or write, PIIX4 responds by asserting DEVSEL# on the
next cycle. PAR O CALCULATED PARITY SIGNAL. PAR is ven?parity
and is calculated on 36 bits; AD[31:0] plus C/BE[3:0]#. ven?parity means that
the number of ? within the 36 bits plus PAR are counted and the sum is always
even. PAR is always calculated on 36 bits regardless of the valid byte enables.
PAR is generated for address and data phases and is only guaranteed to be valid
one PCI clock after the corresponding address or data phase. PAR is driven and
tri-stated identically to the AD[31:0] lines except that PAR is delayed by exactly
one PCI clock. PAR is an output during the address phase (delayed one clock) for
all PIIX4 initiated transactions. It is also an output during the data phase (delayed
one clock) when PIIX4 is the Initiator of a PCI write transaction, and when it is
the Target of a read transaction..
During Reset: High-Z After Reset: High-Z During POS: High-Z
O PCI RESET. PIIX4 asserts PCIRST# to reset devices that reside on the PCI bus.
PIIX4 asserts PCIRST# during power-up and when a hard reset sequence is
initiated through the RC register. PCIRST# is driven inactive a minimum of 1 ms
after PWROK is driven active. PCIRST# is driven for a minimum of 1 ms when
initiated through the RC register. PCIRST# is driven asynchronously relative to
PCICLK.
During Reset: Low After Reset: High During POS: High
O PCI HOLD. An active low assertion indicates that PIIX4 desires use of the PCI
Bus. Once the PCI arbiter has asserted PHLDA# to PIIX4, it may not negate it
until PHOLD# is negated by PIIX4. PIIX4 implements the passive release
mechanism by toggling PHOLD# inactive for one PCICLK.
During Reset: High-Z After Reset: High During POS: High
I PCI HOLD ACKNOWLEDGE. An active low assertion indicates that PIIX4
has been granted use of the PCI Bus. Once PHLDA# is asserted, it cannot be
negated unless PHOLD# is negated first.
I/O SYSTEM ERROR. SERR# can be pulsed active by any PCI device that detects
a system error condition. Upon sampling SERR# active, PIIX4 can be
programmed to generate a non-maskable interrupt (NMI) to the CPU.
During Reset: High-Z After Reset: High-Z During POS: High-Z

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (2).
SIGNAL TYPE

DESCRIPTION

I/O STOP. STOP# indicates that PIIX4, as a Target, is requesting an initiator to stop
the current transaction. As an Initiator, STOP# causes PIIX4 to stop the current
transaction. STOP# is an output when PIIX4 is a Target and an input when
PIIX4 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#.
STOP# remains tri-stated until driven by PIIX4 as a slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
I/O TARGET READY. TRDY# indicates PIIX4 ability to complete the current data
TRDY#
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data
phase is completed when both TRDY# and IRDY# are sampled asserted. During
a read, TRDY# indicates that PIIX4, as a Target, has place valid data on
AD[31:0]. During a write, it indicates PIIX4, as a Target is prepared to latch data.
TRDY# is an input to PIIX4 when PIIX4 is the Initiator and an output when
PIIX4 is a Target. TRDY# is tri-stated from the leading edge of PCIRST#.
TRDY# remains tri-stated until driven by PIIX4 as a slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
O ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O
AEN
slaves from misinterpreting DMA cycles as valid I/O cycles. When negated,
AEN indicates that an I/O slave may respond to address and I/O commands.
When asserted, AEN informs I/O resources on the ISA bus that a DMA transfer
is occurring. This signal is also driven high during PIIX4 initiated refresh cycles.
During Reset: High-Z After Reset: Low During POS: Low
BALE O BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4 to
indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are
valid. The LA[23:17] address lines are latched on the trailing edge of BALE.
BALE remains asserted throughout DMA and ISA master cycles.
During Reset: High-Z After Reset: Low During POS: Low
I I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA
IOCHK#/
GPI0
bus. When asserted, it indicates that a parity or an uncorrectable error has
occurred for a device or memory on the ISA bus. A NMI will be generated to the
CPU if the NMI generation is enabled. If the EIO bus is used, this signal
becomes a general purpose input.
IOCHRDY I/O I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to
indicate that wait states are required to complete the cycle. This signal is
normally high. IOCHRDY is an input when PIIX4 owns the ISA Bus and the
CPU or a PCI agent is accessing an ISA slave, or during DMA transfers.
IOCHRDY is output when an external ISA Bus Master owns the ISA Bus and is
accessing DRAM or a PIIX4 register. As a PIIX4 output, IOCHRDY is driven
inactive (low) from the falling edge of the ISA commands. After data is available
for an ISA master read or PIIX4 latches the data for a write cycle, IOCHRDY is
asserted for 70 ns. After 70 ns, PIIX4 floats IOCHRDY. The 70 ns includes both
the drive time and the time it takes PIIX4 to float IOCHRDY. PIIX4 does not
drive this signal when an ISA Bus master is accessing an ISA Bus slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z

STOP#

SIGNAL
IOCS16#

TYPE
I

IOR#

I/O

IOW#

I/O

LA[23:17]/
GPO[7:1]

I/O

MEMCS16#

I/O

MEMR#

I/O

MEMW#

I/O

DESCRIPTION
16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA
Bus to indicate support for 16-bit I/O bus cycles.
I/O READ. IOR# is the command to an ISA I/O slave device that the slave
may drive data on to the ISA data bus (SD[15:0]). The I/O slave device must
hold the data valid until after IOR# is negated. IOR# is an output when PIIX4
owns the ISA Bus. IOR# is an input when an external ISA master owns the
ISA Bus.
During Reset: High-Z After Reset: High During POS: High
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave
may latch data from the ISA data bus (SD[15:0]). IOW# is an output when
PIIX4 owns the ISA Bus. IOW# is an input when an external ISA master
owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory
on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the
ISA Bus. The LA[23:17] lines become inputs whenever an ISA master owns
the ISA Bus. If the EIO bus is used, these signals become a general purpose
output.
During Reset: High-Z After Reset: Undefined During POS: Last LA/GPO
MEMORY CHIP SELECT
. 16. MEMCS16# is a decode of LA[23:17]
without any qualification of the command signal lines. ISA slaves that are
16-bit memory devices drive this signal low. PIIX4 ignores MEMCS16#
during I/O access cycles and refresh cycles. MEMCS16# is an input when
PIIX4 owns the ISA Bus. PIIX4 drives this signal low during ISA master to
PCI memory cycles.
MEMORY READ. MEMR# is the command to a memory slave that it may
drive data onto the ISA data bus. MEMR# is an output when PIIX4 is a master
on the ISA Bus. MEMR# is an input when an ISA master, other than PIIX4,
owns the ISA Bus. This signal is also driven by PIIX4 during refresh cycles.
For DMA cycles, PIIX4, as a master, asserts MEMR#.
During Reset: High-Z After Reset: High During POS: High
MEMORY WRITE. MEMW# is the command to a memory slave that it may
latch data from the ISA data bus. MEMW# is an output when PIIX4 owns the
ISA Bus. MEMW# is an input when an ISA master, other than PIIX4, owns
the ISA Bus. For DMA cycles, PIIX4, as a master, asserts MEMW#.
During Reset: High-Z After Reset: High During POS: High

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (3).
SIGNAL TYPE
DESCRIPTION
REFRESH# I/O REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a
refresh cycle is in progress. It should be used to enable the SA[7:0] address to
the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
when MEMR# is asserted, the entire expansion bus dynamic memory is
refreshed. Memory slaves must not drive any data onto the bus during refresh.
As an output, this signal is driven directly onto the ISA Bus. This signal is an
output only when PIIX4 DMA refresh controller is a master on the bus
responding to an internally generated request for refresh. As an input,
REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z After Reset: High During POS: High
O RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the
RSTDRV
ISA/EIO Bus. PIIX4 asserts this signal during a hard reset and during power-up.
RSTDRV is asserted during power-up and negated after PWROK is driven
active. RSTDRV is also driven active for a minimum of 1 ms if a hard reset has
been programmed in the RC register.
During Reset: High After Reset: Low During POS: Low
I/O SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
SA[19:0]
selection with the granularity of 1 byte within the 1-Megabyte section of
memory defined by the LA[23:17] address lines. The address lines SA[19:17]
that are coincident with LA[19:17] are defined to have the same values as
LA[19:17] for all memory cycles. For I/O accesses, only SA[15:0] are used,
and SA[19:16] are undefined. SA[19:0] are outputs when PIIX4 owns the ISA
Bus. SA[19:0] are inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: Last SA
I/O SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a
SBHE#
byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE#
is negated during refresh cycles. SBHE# is an output when PIIX4 owns the
ISA Bus. SBHE# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: High
I/O SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing
SD[15:0]
on the ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0]
correspond to the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z After Reset: Undefined During POS: High-Z
O STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA
SMEMR#
memory slave to drive data onto the data lines. If the access is below the
1-Mbyte range (00000000h?00FFFFFh) during DMA compatible, PIIX4
master, or ISA master cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed
version of MEMR#.

SIGNAL TYPE
DESCRIPTION
O ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O
slaves from misinterpreting DMA cycles as valid I/O cycles. When negated,
AEN indicates that an I/O slave may respond to address and I/O commands.
When asserted, AEN informs I/O resources on the ISA bus that a DMA transfer
is occurring. This signal is also driven high during PIIX4 initiated refresh cycles.
During Reset: High-Z After Reset: Low During POS: Low
BALE O BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4 to
indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are
valid. The LA[23:17] address lines are latched on the trailing edge of BALE.
BALE remains asserted throughout DMA and ISA master cycles.
During Reset: High-Z After Reset: Low During POS: Low
I I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA
IOCHK#/
GPI0
bus. When asserted, it indicates that a parity or an uncorrectable error has
occurred for a device or memory on the ISA bus. A NMI will be generated to
the CPU if the NMI generation is enabled. If the EIO bus is used, this signal
becomes a general purpose input.
IOCHRDY I/O I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to
indicate that wait states are required to complete the cycle. This signal is
normally high. IOCHRDY is an input when PIIX4 owns the ISA Bus and the
CPU or a PCI agent is accessing an ISA slave, or during DMA transfers.
.
IOCHRDY is output when an external ISA Bus Master owns the ISA Bus and
is accessing DRAM or a PIIX4 register. As a PIIX4 output, IOCHRDY is driven
inactive (low) from the falling edge of the ISA commands. After data is
available for an ISA master read or PIIX4 latches the data for a write cycle,
IOCHRDY is asserted for 70 ns. After 70 ns, PIIX4 floats IOCHRDY. The 70
ns includes both the drive time and the time it takes PIIX4 to float IOCHRDY.
PIIX4 does not drive this signal when an ISA Bus master is accessing an ISA
Bus slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
I 16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA
IOCS16#
Bus to indicate support for 16-bit I/O bus cycles.
I/O I/O READ. IOR# is the command to an ISA I/O slave device that the slave may
IOR#
drive data on to the ISA data bus (SD[15:0]). The I/O slave device must hold the
data valid until after IOR# is negated. IOR# is an output when PIIX4 owns the
ISA Bus. IOR# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
I/O I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave
IOW#
may latch data from the ISA data bus (SD[15:0]). IOW# is an output when
PIIX4 owns the ISA Bus. IOW# is an input when an external ISA master owns
the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
AEN

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (4).
SIGNAL
LA[23:17]/
GPO[7:1]

TYPE
DESCRIPTION
I/O ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the
ISA Bus. The LA[23:17] lines become inputs whenever an ISA master owns
the ISA Bus. If the EIO bus is used, these signals become a general purpose
output.
During Reset: High-Z After Reset: Undefined During POS: Last LA/GPO
MEMCS16# I/O MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17]
without any qualification of the command signal lines. ISA slaves that are
16-bit memory devices drive this signal low. PIIX4 ignores MEMCS16#
during I/O access cycles and refresh cycles. MEMCS16# is an input when
PIIX4 owns the ISA Bus. PIIX4 drives this signal low during ISA master to
PCI memory cycles.
I/O MEMORY READ. MEMR# is the command to a memory slave that it may
MEMR#
drive data onto the ISA data bus. MEMR# is an output when PIIX4 is a master
on the ISA Bus. MEMR# is an input when an ISA master, other than PIIX4,
owns the ISA Bus. This signal is also driven by PIIX4 during refresh cycles.
For DMA cycles, PIIX4, as a master, asserts MEMR#.
During Reset: High-Z After Reset: High During POS: High
I/O MEMORY WRITE. MEMW# is the command to a memory slave that it may
MEMW#
latch data from the ISA data bus. MEMW# is an output when PIIX4 owns the
ISA Bus. MEMW# is an input when an ISA master, other than PIIX4, owns the
ISA Bus. For DMA cycles, PIIX4, as a master, asserts MEMW#.
During Reset: High-Z After Reset: High During POS: High
REFRESH# I/O REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a
refresh cycle is in progress. It should be used to enable the SA[7:0] address to
the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
when MEMR# is asserted, the entire expansion bus dynamic memory is
refreshed. Memory slaves must not drive any data onto the bus during refresh.
As an output, this signal is driven directly onto the ISA Bus. This signal is an
output only when PIIX4 DMA refresh controller is a master on the bus
responding to an internally generated request for refresh. As an input,
REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z After Reset: High During POS: High
O RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the
RSTDRV
ISA/EIO Bus. PIIX4 asserts this signal during a hard reset and during
power-up. RSTDRV is asserted during power-up and negated after PWROK is
driven active. RSTDRV is also driven active for a minimum of 1 ms if a hard
reset has been programmed in the RC register.
During Reset: High After Reset: Low During POS: Low

SIGNAL TYPE

DESCRIPTION

SA[19:0]

I/O

SYSTEM ADDRESS[19:0]. These bi-directional address lines define the


selection with the granularity of 1 byte within the 1-Megabyte section of memory
defined by the LA[23:17] address lines. The address lines SA[19:17] that are
coincident with LA[19:17] are defined to have the same values as LA[19:17] for
all memory cycles. For I/O accesses, only SA[15:0] are used, and SA[19:16] are
undefined. SA[19:0] are outputs when PIIX4 owns the ISA Bus. SA[19:0] are
inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: Last SA
I/O SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a
SBHE#
byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is
negated during refresh cycles. SBHE# is an output when PIIX4 owns the ISA Bus.
SBHE# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: High
SD[15:0] I/O SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on
the ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond
to the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z After Reset: Undefined During POS: High-Z
SMEMR# O STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA
memory slave to drive data onto the data lines. If the access is below the 1-Mbyte
range (00000000h?00FFFFFh) during DMA compatible, PIIX4 master, or ISA
.
master cycles, PIIX4 asserts SMEMR#.
SMEMR# is a delayed version of
MEMR#.
IGNNE#

OD IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore


numeric exception pin on the CPU. IGNNE# is only used if the PIIX4
coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
During Reset: High-Z After Reset: High-Z During POS: High-Z
OD INITIALIZATION. INIT is asserted in response to any one of the following
conditions. When the System Reset bit in the Reset Control Register is reset to 0
and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting
INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded on the PCI
Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0. When
asserted, INIT remains asserted for approximately 64 PCI clocks before being
negated. This signal is active high for Pentium processor and active-low for
Pentium II processor as determined by CONFIG1 signal.
Pentium Processor:
During Reset: Low After Reset: Low During POS: Low
Pentium II Processor:
During Reset: High After Reset: High During POS: High

INIT

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (5).
SIGNAL TYPE
DESCRIPTION
OD CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that an
INTR
interrupt request is pending and needs to be serviced. It is asynchronous with
respect to SYSCLK or PCICLK and is always an output. The interrupt controller
must be programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low After Reset: Low During POS: Low
OD NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable
NMI
interrupt to the CPU. PIIX4 generates an NMI when either SERR# or IOCHK# is
asserted, depending on how the NMI Status and Control Register is programmed.
The CPU detects an NMI when it detects a rising edge on NMI. After the NMI
interrupt routine processes the interrupt, the NMI status bits in the NMI Status
and Control Register are cleared by software. The NMI interrupt routine must
read this register to determine the source of the interrupt. The NMI is reset by
setting the corresponding NMI source enable/disable bit in the NMI Status and
Control Register. To enable NMI interrupts, the two NMI enable/disable bits in
the register must be set to 0, and the NMI mask bit in the NMI Enable/Disable
and Real Time Clock Address Register must be set to 0. Upon PCIRST#, this
signal is driven low.
During Reset: Low After Reset: Low During POS: Low
OD SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous
SMI#
output that is asserted by PIIX4 in response to one of many enabled hardware or
software events. The CPU recognizes the falling edge of SMI# as the highest
priority interrupt in the system, with the exception of INIT, CPURST, and
FLUSH.
During Reset: High-Z After Reset: High-Z During POS: High-Z
STPCLK# OD STOP CLOCK. STPCLK# is an active low synchronous output that is asserted
by PIIX4 in response to one of many hardware or software events. STPCLK#
connects directly to the CPU and is synchronous to PCICLK.
During Reset: High-Z After Reset: High-Z During POS: HighI/O RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal.
RTCX1,
External capacitors are required. These clock inputs are required even if the
RTCX2
internal RTC is not being used.
I 48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This
CLK48
signal may be stopped during suspend modes.
I FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz,
PCICLK
PCICLK provides timing for all transactions on the PCI Bus. All other PCI
signals are sampled on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge. Because many of the circuits in PIIX4 run off
the PCI clock, this signal MUST be kept active, even if the PCI bus clock is not
active.
I 14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This
OSC
clock signal may be stopped during suspend modes.

SIGNAL TYPE
DESCRIPTION
O SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI
SUSCLK
bridge used for maintenance of DRAM refresh. This signal is stopped during
Suspend-to-Disk and Soft Off modes. For values During Reset, After Reset, and
During POS, see the Suspend/Resume and Resume Control Signaling section.
O ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It
SYSCLK
drives the ISA bus directly. The SYSCLK is generated by dividing PCICLK by
4. The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI
accesses to the ISA bus, SYSCLK may be stretched low to synchronize BALE
falling to the rising edge of SYSCLK.
During Reset: Running After Reset: Running During POS: Low
O PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either
PDA[2:0]
the ATA command block or control block is being addressed. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Primary IDE connector. If the IDE signals are
configured for Primary 0 and Primary 1, these signals are used for the Primary 0
connector.
O PRIMARY DISK CHIP SELECT FOR 1F0H- -1F7H RANGE. For ATA
PDCS1#
command register block. If the IDE signals are configured for Primary and
Secondary, this output signal is connected to the corresponding signal on the
Primary IDE connector. If the IDE
. signals are configured for Primary Master and
Primary Slave, this signal is used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
O PRIMARY DISK CHIP SELECT FOR 3F0- -3F7 RANGE. For ATA control
PDCS3#
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Primary IDE
connector. If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
PDD[15:0] I/O PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or
from the IDE device. If the IDE signals are configured for Primary and
Secondary, these signals are connected to the corresponding signals on the
Primary IDE connector. If the IDE signals are configured for Primary Master
and Primary Slave, this signal is used for the Primary Master connector.
O SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in
SDA[2:0]
either the ATA command block or control block is being addressed. If the IDE
signals are configured for Primary and Secondary, these signals are connected to
the corresponding signals on the Secondary IDE connector. If the IDE signals are
configured for Primary Master and Primary Slave, these signals are used for the
Primary Slave connector.

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (6).
SIGNAL TYPE
IGNNE#

INIT

INTR

NMI

SMI#

DESCRIPTION

OD IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore


numeric exception pin on the CPU. IGNNE# is only used if the PIIX4
coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
During Reset: High-Z After Reset: High-Z During POS: High-Z
OD INITIALIZATION. INIT is asserted in response to any one of the following
conditions. When the System Reset bit in the Reset Control Register is reset to 0
and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting
INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded on the PCI
Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0. When
asserted, INIT remains asserted for approximately 64 PCI clocks before being
negated. This signal is active high for Pentium processor and active-low for
Pentium II processor as determined by CONFIG1 signal.
Pentium Processor:
During Reset: Low After Reset: Low During POS: Low
Pentium II Processor:
During Reset: High After Reset: High During POS: High
OD CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that an
interrupt request is pending and needs to be serviced. It is asynchronous with
respect to SYSCLK or PCICLK and is always an output. The interrupt controller
must be programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low After Reset: Low During POS: Low
OD NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable
interrupt to the CPU. PIIX4 generates an NMI when either SERR# or IOCHK#
is asserted, depending on how the NMI Status and Control Register is
programmed. The CPU detects an NMI when it detects a rising edge on NMI.
After the NMI interrupt routine processes the interrupt, the NMI status bits in the
NMI Status and Control Register are cleared by software. The NMI interrupt
routine must read this register to determine the source of the interrupt. The NMI
is reset by setting the corresponding NMI source enable/disable bit in the NMI
Status and Control Register. To enable NMI interrupts, the two NMI
enable/disable bits in the register must be set to 0, and the NMI mask bit in the
NMI Enable/Disable and Real Time Clock Address Register must be set to 0.
Upon PCIRST#, this signal is driven low.
During Reset: Low After Reset: Low During POS: Low
OD SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low
synchronous output that is asserted by PIIX4 in response to one of many enabled
hardware or software events. The CPU recognizes the falling edge of SMI# as
the highest priority interrupt in the system, with the exception of INIT, CPURST,
and FLUSH.
During Reset: High-Z After Reset: High-Z During POS: High-Z

SIGNAL TYPE
DESCRIPTION
STPCLK# OD STOP CLOCK. STPCLK# is an active low synchronous output that is asserted
by PIIX4 in response to one of many hardware or software events. STPCLK#
connects directly to the CPU and is synchronous to PCICLK.
During Reset: High-Z After Reset: High-Z During POS: HighI/O RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal.
RTCX1,
External capacitors are required. These clock inputs are required even if the
RTCX2
internal RTC is not being used.
I 48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller.
CLK48
This signal may be stopped during suspend modes.
I FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz,
PCICLK
PCICLK provides timing for all transactions on the PCI Bus. All other PCI
signals are sampled on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge. Because many of the circuits in PIIX4 run off
the PCI clock, this signal MUST be kept active, even if the PCI bus clock is not
active.
I 14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This
OSC
clock signal may be stopped during suspend modes.
O SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI
SUSCLK
bridge used for maintenance of DRAM refresh. This signal is stopped during
Suspend-to-Disk and Soft Off modes. For values During Reset, After Reset, and
.
During POS, see the Suspend/Resume
and Resume Control Signaling section.
O ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It
SYSCLK
drives the ISA bus directly. The SYSCLK is generated by dividing PCICLK by 4.
The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI
accesses to the ISA bus, SYSCLK may be stretched low to synchronize BALE
falling to the rising edge of SYSCLK.
During Reset: Running After Reset: Running During POS: Low
O PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either
PDA[2:0]
the ATA command block or control block is being addressed. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Primary IDE connector. If the IDE signals are
configured for Primary 0 and Primary 1, these signals are used for the Primary 0
connector.
O PRIMARY DISK CHIP SELECT FOR 1F0H- -1F7H RANGE. For ATA
PDCS1#
command register block. If the IDE signals are configured for Primary and
Secondary, this output signal is connected to the corresponding signal on the
Primary IDE connector. If the IDE signals are configured for Primary Master and
Primary Slave, this signal is used for the Primary Master connector.
During Reset: High After Reset: High During POS: High

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (7).
SIGNAL TYPE
DESCRIPTION
O PRIMARY DISK CHIP SELECT FOR 3F0- -3F7 RANGE. For ATA control
PDCS3#
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Primary IDE
connector. If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
PDD[15:0] I/O PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or
from the IDE device. If the IDE signals are configured for Primary and
Secondary, these signals are connected to the corresponding signals on the
Primary IDE connector. If the IDE signals are configured for Primary Master
and Primary Slave, this signal is used for the Primary Master connector.
O SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in
SDA[2:0]
either the ATA command block or control block is being addressed. If the IDE
signals are configured for Primary and Secondary, these signals are connected to
the corresponding signals on the Secondary IDE connector. If the IDE signals
are configured for Primary Master and Primary Slave, these signals are used for
the Primary Slave connector.
O SECONDARY DISK IO WRITE. In normal IDE mode, this is the command to
SDIOW#
the IDE device that it may latch data from the SDD[15:0] lines. Data is latched
by the IDE device on the negation edge of SDIOW#. The IDE device is selected
either by the ATA register file chip selects (SDCS1#, SDCS3#) and the
SDA[2:0] lines, or the IDE DMA slave arbitration signals (SDDACK#). In read
and write cycles this signal is used as the STOP signal, which is used to
terminate an Ultra DMA/33 transaction. If the IDE signals are configured for
Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector. If the IDE signals are configured for Primary
Master and Primary Slave, these signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: High
I SECONDARY IO CHANNEL READY. In normal IDE mode, this input signal
SIORDY
is directly driven by the corresponding IDE device IORDY signal. In an Ultra
DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching
data on rising and falling edges of STROBE. In an Ultra DMA write cycle, this
signal is used as the DMARDY# signal which is negated by the drive to pause
Ultra DMA/33 transfers.If the IDE signals are configured for Primary and
Secondary, this signal is connected to the corresponding signal on the Secondary
IDE connector. If the IDE signals are configured for Primary Master and Primary
Slave, these signals are used for the Primary Slave connector. This is a Schmitt
triggered input.
I OVER CURRENT DETECT. These signals are used to monitor the status of
OC[1:0]#
the USB power supply lines. The corresponding USB port is disabled when its
over current signal is asserted.
I/O SERIAL BUS PORT 0. This signal pair comprises the differential data signal
USBP0+,
for USB port 0.

USBP0

SIGNAL

TYPE

DESCRIPTION

SERIAL BUS PORT 1. This signal pair comprises the differential data signal
for USB port 1.
I BATTERY LOW. Indicates that battery power is low. PIIX4 can be
programmed to prevent a resume operation when the BATLOW# signal is
asserted. If the Battery Low function is not needed, this pin can be used as a
general-purpose input.
CPU_STP#/ O CPU CLOCK STOP. Active low control signal to the clock generator used to
GPO17
disable the CPU clock outputs. If this function is not needed, then this signal
can be used as a general-purpose output.
For values During Reset, After Reset, and During POS, see the
Suspend/Resume and Resume Control Signaling section.
I/OD EXTERNAL SYSTEM MANAGEMENT INTERRUPT. EXTSMI# is a
EXTSMI#
falling edge triggered input to PIIX4 indicating that an external device is
requesting the system to enter SMM mode. When enabled, a falling edge on
EXTSMI# results in the assertion of the SMI# signal to the CPU. EXTSMI# is
an asynchronous input to PIIX4. However, when the setup and hold times are
met, it is only required to be asserted for one PCICLK. Once negated
EXTSMI# must remain negated for at least four PCICLKs to allow the edge
detect logic to reset. EXTSMI# is asserted by PIIX4 in response to SMI#
being activated within the Serial IRQ function. An external pull-up should be
placed on this signal.
USBP1+,
USBP1
BATLOW#/
GPI9

I/O

LID/
GPI10

PCIREQ
[A:D]#

PCI_STP#/
GPO18

PWRBTN#

RI#
GPI12

LID INPUT. This signal can be used to monitor the opening and closing of the
display lid of a notebook computer. It can be used to detect both low to high
transition or a high to low transition and these transitions will generate an
SMI# if enabled. This input contains logic to perform a 16-ms debounce of the
input signal. If the LID function is not needed, this pin can be used as a
general-purpose input.
PCI REQUEST. Power Management input signals used to monitor PCI
Master Requests for use of the PCI bus. They are connected to the
corresponding REQ[0:3]# signals on the Host Bridge.
PCI CLOCK STOP. Active low control signal to the clock generator used to
disable the PCI clock outputs. The PIIX4 free running PCICLK input must
remain on. If this function is not needed, this pin can be used as a
general-purpose output.
For values During Reset, After Reset, and During POS, see the
Suspend/Resume and Resume Control Signaling section.
POWER BUTTON. Input used by power management logic to monitor
external system events, most typically a system on/off button or switch. This
input contains logic to perform a 16-ms debounce of the input signal.
RING INDICATE. Input used by power management logic to monitor
external system events, most typically used for wake up from a modem. If this
function is not needed, then this signal can be individually used as a
general-purpose input.

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (8).
SIGNAL
RSMRST#

TYPE
DESCRIPTION
I RESUME RESET. This signal resets the internal Suspend Well power plane
logic and portions of the RTC well logic.
SMBALERT#/ I SM BUS ALERT. Input used by System Management Bus logic to generate
GPI11
an interrupt (IRQ or SMI) or power management resume event when enabled.
If this function is not needed, this pin can be used as a general-purpose input.
I/O SM BUS CLOCK. System Management Bus Clock used to synchronize
SMBCLK
transfer of data on SMBus.
During Reset: High-Z After Reset: High-Z During POS: High-Z
I/O SM BUS DATA. Serial data line used to transfer data on SMBus.
SMBDATA
During Reset: High-Z After Reset: High-Z During POS: High-Z
O SUSPEND PLANE A CONTROL. Control signal asserted during power
SUSA#
management suspend states. SUSA# is primarily used to control the primary
power plane. This signal is asserted during POS, STR, and STD suspend
states.
During Reset: Low After Reset: High During POS: Low
O SUSPEND PLANE B CONTROL. Control signal asserted during power
SUSB#/
GPO15
management suspend states. SUSB# is primarily used to control the
secondary power plane. This signal is asserted during STR and STD suspend
states. If the power plane control is not needed, this pin can be used as a
general-purpose output.
During Reset: Low After Reset: High During POS: High/GPO
O SUSPEND PLANE C CONTROL. Control signal asserted during power
SUSC#/
GPO16
management suspend states, primarily used to control the tertiary power
plane. It is asserted only during STD suspend state. If the power plane
control is not needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: High During POS: High/GPO
SUS_STAT1#/ O SUSPEND STATUS 1. This signal is typically connected to the
GPO20
Host-to-PCI bridge and is used to provide information on host clock status.
SUS_STAST1# is asserted when the system may stop the host clock, such as
Stop Clock or during POS, STR, and STD suspend states. If this function is
not needed, this pin can be used as a general-purpose output.
SUS_STAT2#/ O SUSPEND STATUS 2. This signal will typically connect to other system
GPO21
peripherals and is used to provide information on system suspend state. It is
asserted during POS, STR, and STD suspend states. If this function is not
needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: High During POS: Low/GPO
I THERMAL DETECT. Active low signal generated by external hardware to
THRM#/
GPI8
start the Hardware Clock Throttling mode. If enabled, the external hardware
can force the system to enter into Hardware Clock Throttle mode by
asserting THRM#. This causes PIIX4 to cycle STPCLK# at a preset
programmable rate. If this function is not needed, this pin can be used as a
general-purpose input.

SIGNAL
ZZ/
GPO19

GPI[21:0]

GPO[30:0]

CONFIG1

CONFIG2

PWROK

SPKR

TEST#

TYPE
DESCRIPTION
O LOW-POWER MODE FOR L2 CACHE SRAM. This signal is used to
power down a cache data SRAMs when the clock logic places the CPU into
the Stop Clock. If this function is not needed, this pin can be used as a
general-purpose output.
During Reset: Low After Reset: Low During POS: Low
I GENERAL PURPOSE INPUTS. These input signals can be monitored via
the GPIREG register located in Function 3 (Power Management) System IO
Space at address PMBase+30h. See Table 1 for details.
O GENERAL PURPOSE OUTPUTS. These output signals can be controlled
via the GPIREG register located in Function 3 (Power Management) System
IO Space at address PMBase+34h. If a GPO pin is not multiplexed with
another signal or defaults to GPO, then its state after reset is the reset condition
of the GPOREG register. If the GPO defaults to another signal, then it defaults
to that signal state after reset. The GPO pins that default to GPO remain stable
after reset. The others may toggle due to system boot or power control
sequencing after reset prior to their being programmed as GPOs. The GPO8
signal is driven low upon removal of power from the PIIX4 core power plane.
All other GPO signals are invalid (buffers powered off).
I CONFIGURATION SELECT 1. This input signal is used to select the type
of microprocessor being used in the system. If CONFIG1=0, the system
contains a Pentium microprocessor. If CONFIG1=1, the system contains a
. is used to control the polarity of INIT and
Pentium II microprocessor. It
CPURST signals.
I CONFIGURATION SELECT 2. This input signal is used to select the
positive or subtractive decode of FFFF0000h FFFFFFFh memory address
range (top 64 Kbytes). If CONFIG[2]=0, the PIIX4 will positively decode this
range. If CONFIG[2]=1, the PIIX4 will decode this range with subtractive
decode timings only. The input value of this pin must be static and may not
dynamically change during system operations.
I POWER OK. When asserted, PWROK is an indication to PIIX4 that power
and PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, PIIX4 asserts CPURST,
PCIRST# and RSTDRV. When PWROK is driven active (high), PIIX4
negates CPURST, PCIRST#, and RSTDRV.
O SPEAKER. The SPKR signal is the output of counter timer 2 and is internally
ANDed with Port 061h bit 1 to provide the Speaker Data Enable. This signal
drives an external speaker driver device, which in turn drives the ISA system
speaker.
During Reset: Low After Reset: Low During POS: Last State
I TEST MODE SELECT. The test signal is used to select various test modes
of PIIX4. This signal must be pulled up to VCC(SUS) for normal operation.

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6120N N/B MAINTENANCE


3.3 INTEL 82371EB PCI-TO-ISA / IDE XCELERATOR (PIIX4) (9).
SIGNAL TYPE
VCC
VCC (RTC)
VCC (SUS)
VCC (USB)
VREF

VSS
VSS (USB)

DESCRIPTION

CORE VOLTAGE SUPPLY. These pins are the primary voltage supply for
the PIIX4 core and IO periphery and must be tied to 3.3V.
V RTC WELL VOLTAGE SUPPLY. This pin is the supply voltage for the
RTC logic and must be tied to 3.3V.
V SUSPEND WELL VOLTAGE SUPPLY. These pins are the primary voltage
supply for the PIIX4 suspend logic and IO signals and must be tied to 3.3V.
V USB VOLTAGE SUPPLY. This pin is the supply voltage for the USB
input/output buffers and must. be tied to 3.3V.
V VOLTAGE REFERENCE. This pin is used to provide a 5V reference voltage
for 5V safe input buffers. VREF must be tied to 5V in a system requiring 5V
tolerance. In a 5V tolerant system, this signal must power up before or
simultaneous to VCC. It must power down after or simultaneous to VCC. In a
non-5V tolerant system (3.3V only), this signal can be tied directly to VCC.
There are then no sequencing requirements.
V CORE GROUND. These pins are the primary ground for PIIX4.
V USB GROUND. This pin is the ground for the USB input/output buffers.

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6120N N/B MAINTENANCE


4. MAJOR CHIP DESCRIPTION
INTEL 440ZX AGPSET:
82443ZX HOST BRIDGE/CONTROLLER
Processor/host bus support
~ Optimized for Pentium
PentiumII processor at 100 MHz system bus frequency; Support for 66 MHz
~ InIn-order transaction and dynamic deferred transaction support
~ Desktop optimized GTL+ bus driver technology (gated GTL+ receivers
receivers for reduced power)
Integrated DRAM controller
~ 8 to 256Mbytes
~ Supports 2 doubledouble-sided DIMMs (4 rows memory)
~ 6464-bit data interface
~ Unbuffered SDRAM (Synchronous) DRAM Support (x(x-1-1-1 access @ 66 MHz, xx-1-1-1 access @
100 MHz)
~ Enhanced SDRAM Open Page Architecture Support for 1616- and 6464-Mbit DRAM devices with 2k, 4k
and 8k page sizes
PCI bus interface
~ PCI Rev. 2.1, 3.3V and 5V, 33MHz interface compliant
compliant
~ PCI Parity Generation Support
~ Data streaming support from PCI to DRAM
~ Delayed Transaction support for PCIPCI-DRAM Reads
~ Supports concurrent CPU, AGP and PCI transactions
transactions to main memory

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6120N N/B MAINTENANCE


INTEL 440ZX AGPSET:
82443ZX HOST BRIDGE/CONTROLLER
AGP interface
~ Supports single AGP compliant device (AGP(AGP-66/133 3.3V device)
~ AGP Specification Rev 1.0 compliant
~ AGPAGP-data/transaction flow optimized arbitration mechanism
~ AGP sideside-band interface for efficient request pipelining without interfering
interfering with the data streams
~ AGPAGP-specific data buffering
~ Supports concurrent CPU, AGP and PCI transactions
transactions to main memory
~ AGP highhigh-priority transactions (
(expedite
expedite) support
Power Management Functions
~ Stop Clock Grant and Halt special cycle translation
translation (host to PCI Bus)
~ Dynamic power down of idle DRAM rows
~ Independent, internal dynamic clock gating reduces
reduces average power dissipationt
Packaging/Voltage
~ 492 Pin BGA
~ 3.3V core and mixed 3.3V and GTL I/O
Supporting I/O Bridge
~ System Management Bus (SMB) with support for DIMM
DIMM Serial Presence Detect (SPD)
~ PCIPCI-ISA Bridge (PIIX4E)
~ 3.3V core and mixed 5V, 3.3V I/O and interface to
to the 2.5V CPU signals via openopen-drain output
buffers
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6120N N/B MAINTENANCE


4.2 Intel 82371EB PCI-to-ISA / IDE accelerator (PIIX4E)
Supported Kits For Both Pentium And Pentium II Microprocessors
~ 82430TX ISA Kit
~ 82440bx ISA/DP Kit
Multifunction PCI To ISA Bridge
~ Supports PCI At 30 MHZ And 33 MHZ
~ Supports PCI Rev 2.1 Specification
~ Supports Full ISA Or Extended I/O (EIO) Bus
~ Supports Full Positive Decode Or Subtractive Decode Of PCI
~ Supports ISA And EIO At 1/4 Of PCI Frequency
Supports Both Mobile And Desktop Deep Green Environments
~ 3.3v Operation With 5v Tolerant Buffers
~ UltraUltra-low Power For Mobile Environments Support
~ PowerPower-on Suspend, Suspend To Ram, Suspend To Disk, And SoftSoft-off System States
~ All Registers Readable And Restorable For Proper Resume From 0.V Suspend
Power Management Logic
~ Global And Local Device Management
~ Suspend And Resume Logic
~ Supports Thermal Alarm
~ Support For External Microcontroller
~ Full Support For Advanced Configuration And Power Interface (ACPI)
(ACPI) Revision
1.0 Specification And OS Directed Power Management
Integrated IDE Controller
~ Independent Timing Of Up To 4 Drives
~ PIO Mode 4 And Bus Master IDE Transfers Up To 14 Mbytes/sec
~ Supports Ultra DMA/33 Synchronous DMA Mode Transfers Up To 33 Mbytes/sec
Mbytes/sec
~ Integrated 16 X 3232-bit Buffer For IDE PCI Burst Transfers
~ Supports GlueGlue-less SwapSwap-bay Option With Full Electrical Isolation
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6120N N/B MAINTENANCE


4.2 Intel 82371EB PCI-to-ISA / IDE Xcelerator (PIIX4E)
Enhanced DMA Controller
~ Two 82C37 DMA Controllers
~ Supports PCI DMA With 3 PC/PCI Channels And Distributed DMA Protocols
Protocols
~ Fast TypeType-F DMA For Reduced PCI Bus Usage
Interrupt Controller Based On Two 82C59
~ 15 Interrupt Support
~ Independently Programmable For Edge/level Sensitivity
~ Supports Optional I/O APIC
~ Serial Interrupt Input
Timers Based On 82C54
~ System Timer, Refresh Request, Speaker Tone Output
USB
~ Two USB 1.0 Ports For Serial Transfers At 12 Or 1.5 Mbit/sec
Mbit/sec
~ Supports Legacy Keyboard And Mouse Software With USBUSB-based Keyboard And Mouse
~ Supports UHCI Design Guide
MBUS
~ Host Interface Allows CPU To Communicate Via SMBUS
~ Slave Interface Allows External SMBUS Master To Control Resume Events
RealReal-time Clock
~ 256256-byte BatteryBattery-back CMOS SRAM
~ Includes Date Alarm
~ Two 88-byte Lockout Ranges
Microsoft Win95* Compliant
324 MBGA Package
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6120N N/B MAINTENANCE


5. System View And Disassembly
5.1 System View
5.1.1 Right-Side View

1. Battery Pack
2. CD-ROM/DVD-ROM Drive
3. IR Port

Figure 5-1. Right-Side View

5.1.2

Left-Side View
1. S-Video Output Connector
2. RJ-45 or RJ-11 Connector
(optional)
3. PC Card Slots
4. Floppy Disk Drive
5. Volume Control

Figure 5-2. Left-Side View

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6120N N/B MAINTENANCE


5.1.3 Rear View

Figure 5-3. Rear View

5.1.4

1. Kensington Lock Anchor


2. PS/2 Mouse/Keyboard Port
3. Power Connector
4. USB Port
5. Serial Port
6. Ventilation Opening
7. Parallel Port
8. VGA Port
9. Expansion Connector
10. Microphone Connector
11. Audio Output Connector

Front View

1. Top Cover Latch

Figure 5-4. Front View

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6120N N/B MAINTENANCE


5.1.5

Bottom View

1.
2.
3.
4.

Modem Card/LAN Card Cover


CPU Card Cover
Battery Pack & Locking Latch
FDD/HDD Module

Figure 5-5. Bottom View

5.1.6 Top-Open View


To open the cover, press the cover latch toward the right and lift the cover.

1.
2.
3.
4.
5.
6.
7.
8.

Figure 5-6. Top-Open View

LCD Display
Microphone
Power Button
Keyboard
Stereo Speaker Set
Touchpad
System Indicators
Power Indicators

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6120N N/B MAINTENANCE


5.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly
and show corresponding illustrations. Use the chart below to determine the
disassembly sequence for removing components from the notebook.

Modular Components
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8

Battery Pack
CD-ROM/DVD-ROM Drive
Hard Disk Drive
Floppy Disk Drive
CPU
Modem/LAN Card
Keyboard
SO-DIMM

LCD Assembly Components


5.2.9 LCD Assembly
5.2.10 LCD Panel
5.2.11 Inverter/LED Board

Base Unit Components


5.2.12 Battery/Touchpad Board
5.2.13 System Board
5.2.14 Touchpad Panel

You can also find details such as exploded views and parts lists in Chapter10.

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6120N N/B MAINTENANCE


5.2.1

Battery Pack

Disassembly
1. Put the notebook upside down with care.
2. Press the locking latch outward to unlatch the battery
pack and then pull it out of the compartment.

Reassembly
1. Fit the battery pack into the compartment. Make sure the
locking latches are in the locked position. (Refer to Figure
5-7 )

5.2.2

Figure 5-7. Removing the Battery Pack

CD-ROM/DVD-ROM Drive

Disassembly
1. Place the notebook upside down with care.
2. Open the CPU compartment cover by removing two
screws then sliding the cover toward the rear side
to open it. (Refer to Figure 5-8.)

Figure 5-8. Removing the CPU Compartment Cover

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6120N N/B MAINTENANCE

3. Remove one screw that fastens the CD-ROM/DVD-ROM drive.


(Refer to Figure 5-9.)
4. Push the rear side of the CD-ROM/DVD-ROM drive to disconnect the
drive from the system board, then slide it out of the compartment.

Reassembly
1. Slide the CD-ROM/DVD-ROM drive into the compartment.
The cable connector on the system board will automatically
plug into the rear side of the drive. (Refer to Figure 5-10.)

Figure 5-9. Removing One Screw

2. Secure the CD-ROM/DVD-ROMdrive with one screw.


(Refer to Figure 5-9 earlier.)
3. Replace the CPU compartment cover and secure with two
screws. (Refer to Figure 5-8 earlier.)

Figure 5-10. Removing the CD-ROM/DVD-ROM Drive

-37-

6120N N/B MAINTENANCE


5.2.3

Hard Disk Drive

Disassembly
1. Put the notebook upside down with care.
2. Remove one screw and slide the FDD/HDD module out of the
compartment.

3.

Remove four screws and disconnect the hard disk drive


from the connector. (Refer to Figure 5-12.)

Reassembly

Note: When
securing this
screw, the
force must be
less than 3.5 kg,
otherwise the
bracket may
break.

Figure 5-11. Removing the FDD/HDD Module

1. Place the hard disk drive in the bracket and plug in the hard
disk drive connector. Then secure the hard disk drive with
four screws. (Refer to Figure 5-12 )
2. Slide the HDD/FDD module into the compartment and secure
with one screw. (Refer to Figure 5-11 earlier.)
Figure 5-12. Removing the Hard Disk D

-38-

6120N N/B MAINTENANCE


5.2.4

Floppy Disk Drive

Disassembly
1. Remove the hard disk drive. (See section 5.2.3 Disassembly.)
2. Remove four screws to detach the bracket from the floppy disk drive.
(Refer to Figure 5-13.)

Reassembly
1. Replace the bracket and secure with four screws. (Refer to Figure 5-13.)
2. Replace the hard disk drive. Slide the HDD/FDD module into the
compartment and secure with one screw. (See section 5.2.3 Reassembly.)

Figure 5-13. Detaching the Bracket From the Floppy Disk Drive

-39-

6120N N/B MAINTENANCE


5.2.5

CPU

Disassembly
1. Place the notebook upside down and remove the CPU
compartment cover. (See section 5.2.2 Disassembly step 1 and 2.)
2. Remove four screws fastening the fan assembly. Unplug the fan
assemblys power cord and lift it free from the CPU module.
NOTE: When you remove the fan assembly, make sure that the
thermal pad underneath the fan is not damaged. If it is damaged,
you have to replace it with a new thermal pad.
Figure 5-14. Removing the Fan Assem

3. Insert a minus screwdriver 101 (JIS standard) to the OPEN (upper)


side of the socket and gently push the screwdriver to pry the CPU
out of the socket.

CAUTION: The maximum force for extraction of the CPU


should not exceed 100 lbs (45.5 kg).

F igu re 5-15. R em ovin g th e C P U

-40-

6120N N/B MAINTENANCE


Reassembly

1. Align the beveled corner of the CPU with the beveled corner of the socket
and insert the CPU pins into the holes. Insert a minus screwdriver to the
CLOSE (lower) side of the socket and push the screwdriver toward the
CPU to secure the CPU in place.
CAUTION:

The maximum force for insertion of the CPU should not exceed

100 lbs (45.5 kg).

Figure 5-16. Insertion the CPU

2. Place the fan assembly on top of the CPU. Plug in the power cord and secure
the fan assembly with four screws. (Refer to Figure 5-14 earlier.)
3. Replace the CPU compartment cover and secure with two screws.

-41-

6120N N/B MAINTENANCE


5.2.6 Modem Card

Disassembly
1. Place the notebook upside down with care.
2. Remove one screw and open the Modem card
compartment cover. (Refer to Figure 5-17)
3. Carefully lift up the inner edge of the card to disconnect it
from the system board.

Figure 5-17. Removing the Modem Card Compartment


Cover

Reassembly
1. Hold the Modem card at an angle so that the phone line connector is
pointed towards the opening on the notebook. Insert the connector into
the opening and press the other end to plug the Modem card into the
socket on the system board. (Refer to Figure 5-18 earlier.)
2. Replace the compartment cover and secure with one screw. (Refer to
Figure 5-17 earlier.)
Figure 5-18. Removing the Modem/LAN Card

-42-

6120N N/B MAINTENANCE


5.2.7

Keyboard

Disassembly
1. Open the top cover.
2. Press the locking latch downward to unlatch the LED panel and
then push it leftward to remove the panel. (Refer to Figure 5-19.)
3. Slightly lift up the keyboard and disconnect the cable from the
system board to detach the keyboard.

Figure 5-19. Removing the LED Panel

Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into
place. (Refer to Figure 5-20 earlier.)
2. Replace the LED panel. (Refer to Figure 5-19 earlier.)
Figure 5-20. Removing the Keyboard

-43-

6120N N/B MAINTENANCE


5.2.8

SO-DIMM

Disassembly

1. Remove the keyboard. (See section 5.2.7 Disassembly.)


2. Pull the retaining clips outwards and remove the SO-DIMM.
(Refer to Figure 5-21.)

Reassembly
1. To install the SO-DIMM, align the SO-DIMMs notched part
with the sockets corresponding part and firmly insert the SODIMM into the socket at an angle. Then push down until the
retaining clips lock the SO-DIMM into position. (Refer to Figure
5-21.)

Figure 5-21. Removing the SO-DIMM

2. Replace the keyboard. (See section 5.2.7 Reassembly.)

-44-

6120N N/B MAINTENANCE


5.2.9 LCD Assembly

Disassembly

1. Remove the hinge cover by inserting a flat


screwdriver to the rear of the cover and pry the
cover out. Repeat the same with the other hinge
cover. (Refer to Figure 5-22).
*Note the right and left hinges are not exchangeable.
2. Open the cover and remove the LED panel. (See section
5.2.7 Disassembly step 2.)

Figure 5-22. Removing the Hinge Covers

3. Disconnect two cables and remove four screws from the


hinges. Now you can separate the LCD assembly from
the base unit.

Reassembly
1. Attach the LCD assembly to the base unit and
secure with four screws on the hinges. Then
reconnect the LCD cables to the system board.
(Refer to Figure 5-23.)
2. Replace the LED panel.
3. Replace the two hinge covers. (Refer to Figure 522 earlier.)

Figure 5-23. Unplugging two Cables and Removing Four Screws

-45-

6120N N/B MAINTENANCE


5.2.10 LCD Panel
Disassembly

1. Open the top cover.


2. Remove the two rubber pads and two screws on
the lower part of the panel. Then insert a flat
screwdriver to the lower part of the frame and
gently pry the frame out. Repeat the process until
the frame is completely separated from the
housing.
3. To remove the LCD, remove three screws and unplug
the inverter cable.

Figure 5-24. Removing the LCD Frame

Reassembly
1. Reconnect the cable to the inverter board. Fit the LCD back into
place and secure with three screws. (Refer to Figure 5-25.)
2. Fit the LCD frame back to the housing. Replace the two screws and
two rubber pads. (Refer to Figure 5-24 earlier.)
Figure 5-25. Removing the LCD

-46-

6120N N/B MAINTENANCE


5.2.11 Inverter/LED Board

Disassembly

1. Detach the LCD frame. (See section 5.2.10 Disassembly step 1


and 2.)
2. To remove the inverter/LED board at the bottom side of the
LCD , remove two screws and unplug the cable from the board.

Reassembly
1. Reconnect the inverter cable. Fit the inverter/LED
board back into place and secure with two screws.
(Refer to Figure 5-26.)

Figure 5-26. Removing the Inverter/LED Board

2. Place the LCD frame back to the housing. (See section


5.2.10 Reassembly step 2.)

-47-

6120N N/B MAINTENANCE


5.2.12 Battery/Touchpad Board
Disassembly
1. Remove the battery pack. (See section 5.2.1 Disassembly.)
2. Remove the CD-ROM/DVD-ROM drive. (See section 5.2.2 Disassembly.)
3. Remove the FDD/HDD module. (See section 5.2.3 Disassembly step 1 and 2.)

4. Remove the CPU module. (See section 5.2.5 Disassembly.)


5. Remove the Modem card (if exist). (See section 5.2.6 Disassembly.)
6. Remove nine screws fastening the base unit frame.
Lift the frame free from the housing. (Refer to Figure 5-27.)
7. Remove seven screws fastening the metal shield. (Refer to Figure 5-28.)

Figure 5-27. Removing the Base Frame Screws

8. After removing the base frame, you will see the battery/touchpad
board in between the speakers. To remove the board, first remove
three screws and unplug three cables(Refer to Figure 5-29.), then
lift it free from the system board.

Figure 5-29. Removing the Battery/Touchpad Board

Figure 5-28. Removing the Battery/Touchpad Board

-48-

6120N N/B MAINTENANCE


5.2.12 Battery/Touchpad Board
Reassembly
1. Reconnect the battery/touchpad board to the system board. Plug three cables
and secure the board with three screws. (Refer to Figure 5-29 earlier.)
2. Replace the metal shield. Secure the shield with seven screws. (Refer to Figure
5-28 earlier.)
3. Replace the base unit frame. Secure the frame with nine screws. (Refer to
Figure 5-27 earlier.)
4. Replace the Modem card (if exist). (See section 5.2.6 Reassembly.)
5. Replace the CPU module. (See section 5.2.5 Reassembly.)
6. Replace the FDD/HDD module. (See section 5.2.3 Reassembly step 2.)
7. Replace the CD-ROM/DVD-ROM drive. (See section 5.2.2 Reassembly.)
8. Replace the battery pack. (See section 5.2.1 Reassembly.)

-49-

6120N N/B MAINTENANCE


5.2.13 System Board
Disassembly

1. Remove the keyboard. (See section 5.2.7 Disassembly.)


2. Remove the LCD assembly. (See section 5.2.9 Disassembly.)
3. Remove one screw fastening the system board.
Figure 5-30. Removing One Screw Fastening the System Board

4. Put the notebook upside down with care.


5. Remove the base frame, metal shield, and battery/touchpad board.
(See section 5.2.12 Disassembly.)
6. Remove two screws on the rear side.
7. Gently lift the system board free from the housing.
Reassembly
1. Fit the system board into the housing and secure with two screws on
the rear side. (Refer to Figure 5-31 earlier.)
2. Replace the battery/touchpad board and other components. (See
section 5.2.12 Reassembly.)
3. Put the notebook surface up. Replace the LCD assembly. (See section
5.2.9 Reassembly.)

Figure Figure 5-31. Removing One Screw


Fastening the System Board

4. Replace one screw and the keyboard module. (Refer to Figure 5-30
earlier.)

-50-

6120N N/B MAINTENANCE


5.2.14 Touchpad Panel

Disassembly

1. Remove the system board. (See section 5.2.13


Disassembly.)
2. The touchpad panel is located in between the speakers. To
remove the panel, unfasten three screws and remove the
metal cover, then you can lift the panel free from the
housing. (Refer to Figure 5-32.)

Figure 5-32. Removing Three Screws and Touchpad Panel

Reassembly
1. Fit the touchpad panel back into place. Replace the metal cover and
secure with three screws. (Refer to Figure 5-32 earlier.)
2. Replace the system board. (See section 5.2.13 Reassembly.)

-51-

6120N N/B MAINTENANCE


6. MAINTENANCE DIAGNOSTICS
6.1 INTRODUCTION
Each time the computer is turned on, the system BIOS runs a series of
internal checks on the hardware. This power-on self test (post)
allows the computer to detect problems as early as the power-on
stage. Error messages of post can alert you to the problems of your
computer.
If an error is detected during these tests, you will see an error
message displayed on the screen. If the error occurs before
the display is initialized,then the screen cannot display the error
message. Error codes or system beeps are used to identify a post
error that occurs when the screen is not available.
The value for the diagnostic port (378H) is written at the beginning of
the test. Therefore, if the test failed, the user can determine where
the problem occurred by reading the last value written to port 378H
by the PIO debug board plug at PIO port.

-52-

6120N N/B MAINTENANCE


6.2 ERROR CODES
Following is a list of error codes in sequence display on the PIO debug board.
CODE
00H
01H
02H
03H
04H
05H
06H

BEEP

Description
ST ART OF BOOT LOADER SECQUENCE.
DISABLE A20 T HROUGH A20, NOT SEND.

.._.

INIT IALIZE CHIPSET OR BIOS NOT SHADOWED.


PERFORM CONVENT IONAL RAM T EST WIT H CROSSED-PAT T ERN R/W.

._..

MOVE BOOT LOADER T O T HE RAM OR BIOS CHECKSUM BAD.


ST ART POINT OF EXECUT ION OF BOOT LOADER IN RAM.
PERFORM PNP INIT IALIZAT ION FOR CRYST AL AUDIO CHIP OR CHECK
OVERRIDE OPT ION, NOT SEND.

07H
08H
09H
0AH
0FH
10H
11H
12H
13H
14H
15H
16H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H

SHADOW SYST EM BIOS.


CHECKSUM SYST EM BIOS ROM, NOT SEND.
PROCEED WIT H NORMAL BOOT .
PROCEED WIT H CRISIS BOOT .
NO RAM OR DRAM SIZING.
INIT IAL L1, L2 CACHE, MAKE ST ACK AND DIAGNOSE CMOS.
T URN OFF FAST A20 FOR FOR POST . RESET GDT S, 8259S QUICKLY.
SIGNAL POWER ON RESET AT CMOS.
INIT IALIZE T HE CHIPSET , (SDRAM).***SOLUTION: TRY TO CLEAR CMOS***
SEARCH FOR ISA BUS VGA ADAPT ER.
RESET COUNT ER/T IMER 1.
USER REGIST ER CONFIG T HROUGH CMOS.
DISPAT CH T O 1ST 64K RAM T EST .
CHECKSUM T HE ROM.
RESET PIC'S(8259).
INIT IALIZE VIDEO ADAPT ER(S).
INIT IALIZE VIDEO (6845 REGS).
INIT IALIZE COLOR ADAPT ER.
INIT IALIZE MONOCHROME ADAPT ER.
T EST 8237A PAGE REGIST ERS.
PERFORM KEYBOARD SELF T EST .
T EST & INIT IALIZE KEYBOARD CONT ROLLER.
CHECK IF CMOS RAM VALID.
T EST BAT T ER FAIL & CMOS X-SUM.
T EST T HE DMA CONT ROLLER.
INIT IALIZE 8237A CONT ROLLER.
INIT IALIZE INT ERRUPT VECT ORS T ABLE.
RAM QUICK SIZING.

CODE BEEP
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
FO~F1H .

Description
PROT ECT ED MODE ENT ERED SAFELY.
RAM T EST COMPLET ED.
PROT ECT ED MODE EXIT SUCCESSFUL .
SET UP SHADOW.
PREPARE T O INIT IALIZE VIDEO.
SEARCH FOR MONOCHROME ADAOT ER.
SEARCH FOR COLOR ADAPT ER, VGA INIT IALIZE.
SIGN-ON MESSAGES DISPLAYED.
SPECIAL INIT OF KEYBOARD CONT ROLLER.
T EST IF KEYBOARD PRESENT .
T EST KEYBOARD INT ERRUPT .
T EST KEYBOARD COMMAND BYT E.
T EST , BLANK AND COUNT ALL RAM.
PROT ECT ED MODE ENT ERED SAFELY(2).
RAM T EST COMPLET ED.
PROT ECT ED MODE EXIT SUCCESSFUL .
UPDAT E KEYBOARD OUT PUT PORT T O DISABLE GAT E OF A20.
SET UP CACHE CONT ROLLER.
T EST IF 18.2HZ PERIODIC WORKING.
INIT IALIZE BIOS DAT A AREA AT 40:0.
INIT IALIZE T HE HARDWARE INT ERRUPT VECT OR.
SEARCH AND INIT T HE MOUSE.
UPDAT E NUMLOCK ST AT US.
OEM INIT IALIZAT ION OF COMM AND LPT PORT S.
CONFIGURE T HE COMM AND LPT PORT S.
INIT IALIZE T HE FLOPPIES.
INIT IALIZE T HE HARD DISK.
INIT IALIZE ADDIT IONAL ROMS.
OEM'S INIT OF POWER MANAGEMENT , (CHECK SMI).
UPDAT E NUMLOCK ST AT US.
T EST FOR COPROCESSOR INST ALLED.
OEM FUNCT IONS BEFORE BOOT (PCMCIA, CARDBUSS).
DISPAT CH T O OPERAT ION SYST EM BOOT .
JUMP INT O BOOT ST RAP CODE.
OEM'S INIT OF PM WIT H USB.
RMA T EST FAILED.

-53-

6120N N/B MAINTENANCE


6.3 PIO PORT (378H) DIAGNOSTIC TOOLS
6.3.1 PARTS USED:
LED

PIO CONNECTOR

6.3.2 CIRCUIT:

PIO
CONNECTOR

LED

25

13

14

PIN1 : STROBE

PIN 13 : SLCT

PIN10: ACK#

PIN 16 : INT#

PIN11: BUSY

PIN 17 : SELIN#

PIN12: PTERR

PIN 14 : AUTOFD#

PIN{9:2}: PD{7:0}

-54-

6120N N/B MAINTENANCE


7. System Block Diagram & Schematics
X2
14.318MHZ

66/100MHZ
CPUCLK

W137
W137
CLOCK
CLOCK
Synthesizer
Synthesizer

14.318MHZ

U503
Celeron
PPGA 370
CPU

66/100MHZ
SDRAMCLK

33MHZ
PCI CLK

144PIN 3.3V
Expansion

48MHZ

W40S11
W40S11
SDRAM
Clock
SDRAM
Buffer Clock
Buffer

4MB
Video SGRAM

AGP VGA
Controller

AGP BUS

Intel
Intel
82443ZX
82443ZX

MTR

ATI_RAGE_LT
PRO

North
North
Bridge
Bridge

SO-DIMM Socket

X9
29.499MHZ

LCD

66MHZ

PCI BUS
CRYSTAL
CRYSTAL
CS4280
PCI

ZV BUS

33MHZ

FAX/
MODEM

CS4280
PCI
Audio
Drive
Audio Drive

AUDIO
CONNECTOR

Intel
Intel
PIIX4E
PIIX4E
South
Bridge
South Bridge

CDROM

X1
24.576MHZ

USB
PORT

CRYSTAL
CRYSTAL
CODEC
CODEC
CS4297
CS4297

33MHZ

X4
32.768KHZ

HDD

33MHZ
14.318MHZ
48MHZ USB CLK

PCCARD
PCCARD
Controller
Controller

TI

TI
PCI 1225
PCI 1225
PCCARD
Socket

8MHZ
ISA CLK

ISA BUS
X5
16MHZ

PC87570
K/B PC87570
Controller
K/B Controller

PS/2 KB

Printer
Port

NS
NS
PC97338
PC97338
Super I/O CTRL_
Super I/O CTRL_

PS/2
Mouse
24MHZ/48MHZ

Battery
Battery

Touch pad
Touch pad
ICON LED

ADM3311
ADM3311
RS232
RS232
Driver
Driver
COM
COM
PORT
PORT

FDD
FIR

System
System
BIOS
FlashBIOS
ROM
Flash ROM
VDD5
VDD5S
VMAIN
+3V
+5V
+12V

D/D Module

-55-

6120N N/B MAINTENANCE


8. TROUBLE SHOOTING
8.1 No Power-------------------------------57

8.10 Hard Disk Drive Test Error------81

8.2 No Display -----------------------------61

8.11 CD-ROM Test Error---------------83

8.3 VGA Controller Failure-------------65

8.12 CMOS Test Error-------------------85

8.4 LCD No Display-----------------------67

8.13 SIO Port Test Error----------------87

8.5 External Monitor No Display------69

8.14 PIO Port Test Error----------------89

8.6 Memory Test Error------------------71

8.15 IrDA TEST ERROR---------------91

8.7 Keyboard Test Error----------------73

8.16 USB Port Test Error---------------93

8.8 Track Pad/ball Test Error----------75

8.17 Audio Drive Failure----------------95

8.9 Diskette Drive Test Error-----------79


-56-

6120N N/B MAINTENANCE


8.1 NO POWER
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

AC
SOURCE

AC
ADAPTOR

HDD
FDD
CD - ROM

BATTERY
PACK
J
4

-57-

6120N N/B MAINTENANCE


8.1 NO POWER
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.
ADINP2

6120N M/B

PD10
SFPJ-73

PL1
JP501
1

PC1
0.1U

ADAPTER IN

PF1
6.5A/32VDC

PT1
5

PD1
RLZ24D

PR1
4.7K

PC2
0.1U

VDD5

R195

VDD5_SW
FROM
PC87570

8
2
7
3

IN
5VTAP 6
SENSE
OUT 1
F/B
ERR- 5
SHUTDN
GND 4

Q30
SI2301DS
S

X C280
10U

U32
LP2951-02BM
R193
100K

R181
100K

PR511
100K

VDD5_SW
FROM PC87570

PC87570
85

DISCHARG_C

BAT_VOLT
8

RP92

U34

75

ADEN#

PQ502
DTC144WK

JP508

VDD5_SW#

VDD5

ADEN#_P
PQ13
2N7002

+5V

3
2

JP509

VDD5_P

Q32
3
DTC144WK

PD9
SFPJ-73

PR26
226K

VMAIN
F5
1A

VMAIN

PL11

PL2

1
14

1,2,3,4,5,6

40

1,2,3,4,5,6

40

J514

J1

6120N CHARGE & DD BD


BATTERY IN

14

DISCHARG_C

J2

BATT+

BATT+

6
PL516

PF501
6.5A/32VDC

PL503

PL511
PR11
301K
PC15
0.1U
50V

PL504
PC522
0.1U
50V

PR12
100K

4
8
7
6
5

1
2
3

PQ510
SI4435DY

BAT_V
PR10
100K

PR519
47K

PL505

PL506

BAT_V

PC14
100U
25V

-58-

6120N N/B MAINTENANCE


8.1 NO POWER
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.

VDD5

23
67
108
161

6120N M/B

EC_VDDA

VDD5
1
5

2
6

R518

POWERBTN

1K

10K

R275
47K

U503
INTEL
CPU
Module

L30

U34 VREF

SW1

R299

91

VDD5

78

L31

R286
0

VTT

EC_AVREF
R300

PWR_ON

R248
47K

4.7K

PU3
SI4416

PL14

PWR_ON

VID [4:1]

PQ2
SI2302DS
D

+5V

PR4

PR3
470

1K
PQ4
SCK431

PC4
10U
PC5
I000P

PD2
RLZ2.7B

6120N
D/D Module

47K

VMAIN

PL13

PL3

PWRGDCPU

PU5
SI4416

PL5
PL4

+2.5V_CPUIO

PWR_ON

PR501

PU1
SB3032P

PU2
SB3032P

PQ11
SPB46N03L
+3V

13

C344
10P

PU3
SI4416
VCC_CORE

J1

ADAPTER IN
(VMAIN)

80

104

PC87570

C515
1000P

J514

EC_VDDA
L29

PWRON

+3V

+3V

PL10

+5V

+5V

PL8

PR15
0

+3V
U27
AMD809
+5V

PR504
0

PQ502
FDS6612A
PQ504
FDS6690A
PQ503
SI9410DY
PQ505
SI9410DY

PU501
SB3052

PL9

+12V
OUTPUT

+12V

-59-

6120N N/B MAINTENANCE


8.1 NO POWER
Symptom:
When the power button is pressed, nothing happens, no fan activity
activity is heard and power indicator is not light up.
up.
No power

Is the
Notebook connected
to power (Either AC adaptor
or battery)?

No

Check following parts and signals:

Connect
AC adaptor
Or battery.

No

BoardBoard-level
Troubleshooting

Yes

VMAIN
OK?

Try another known good battery or AC adapter.

PC1
PT1
PF1
PD1
PD10

Yes

Yes

Replace
Motherboard

Is the
notebooks M/B and
CHARGE BD is connected
properly?

Replace the
faulty AC
adaptor or
Battery.

SIGNAL:

PL1
ADINP2
PL2
VMAIN
PL11
PD9
6120 CHARGE BD

Check following parts and signals:

No

Power
OK?

PARTS:

No

+5V, +12V
Or +3V
OK?

No

PARTS:

SIGNAL:

SW1
U34
J514

POWERBTN
PWR_ON
VMAIN
+5V_P
+12V_P
SHUTDOWN
VDD5
EC_VDDA

R518
R299

6120 CHARGER
BD

Yes

Correct it.
Yes
No

No

Power
OK?

Try another known good


CHARGE BD.

+VCC_CORE
OK?

Yes
Yes

Replace the
faulty Charge
BD.

Yes

End
Power
OK?

No
End

Check following parts and signals:


PARTS:
PU2
PQ11
PR15
PR11
PQ7
PQ5,6

PU5
PU506
PL514
PL3~PL5
PQ8
PQ9,10

SIGNAL:
VMAIN
CPU_PWR_ON
+3V
+5V

-60-

6120N N/B MAINTENANCE


8.2 NO DISPLAY (SYSTEM FAILURE)
Symptom:
There is no display on both LCD and monitor after power on although
although the LCD and monitor are knownknown-good.

AC
SOURCE

LCD

AC
ADAPTOR

FDD&
HDD
J3

J4

-61-

6120N N/B MAINTENANCE


8.2 NO DISPLAY (SYSTEM FAILURE)
Symptom:
There is no display on both LCD and VGA monitor after power on although
although the LCD and monitor is knownknown-good.
No Display

Monitor
or LCD module
OK?

Board-level
Troubleshooting

Replace
monitor
or LCD.

N0

Yes
Make sure that CPU module,
DIMM memory are installed
Properly.

Display
OK?
No

Replace
Motherboard

Yes
Correct it.

1.Try another known good CPU


module, DIMM module And BIOS.
2.Remove all of I/O device (FDD,
HDD, CD-ROM.) from
motherboard except LCD or monitor.

Display
OK?

Yes

1. Replace faulty part.


2. Connect the I/O device to the
M/B one at a time to find out
which part is causing the problem.

Plug PIO debug board to PIO


port to get the port 378H error
code.

System
BIOS writes
error code to port
378H?

Yes

Refer to port 378H


error code description
section to find out
which part is causing
the problem.

No
Check system clock and reset
circuit.

To be continued
Clock and reset checking

No

-62-

6120N N/B MAINTENANCE


8.2 NO DISPLAY (System Failure)
******* RESET CIRCUIT CHECKING *******
VDD5
VDD5

EC_VDDA

EC_VDDA
L29
+3V

6120N

91

23
67
108
161

L31

System Power Good


+3V

VREF 80

On Board
D/D
Module

VCC RESET# 2

PWROK

U34

U503

Q34
DTC144WK

CPU

AK26

PWRGDCPU

PWRGOOD
RESET#
X4

EC_PWROK

U7

EC_AVREF

+5V

U27
ADM809

R286
0

165

GND

PC87570

7408

CPURST#
PWROK

BXPWROK
JL32

HDD_RSTDRV

PWROK

RP38
10K * 4

AUDIO_RST#

Q17
DTC144WK

HARD DRIVE

PIIX4
South Bridge

5VS_CDROM

CD_RST#

B3

PCIRST#
RP38
10K * 4
JP17

Q19
DTC144WK

2
100
MR

U29
U9
CS4297
AC97 CODEC

AC97 Link
11

100

ARST#

ATI RAGE_LT
PRO
VGA
CONTROLL

PCIRST#

CD-ROM

440ZX
North Bridge

RSTDRV

J513

PCIRST#

U18

U16

PCIRST#

PCIRST#

J514
HDD_RST#

R122

CD_RSTDRV

44

PWROK

U24

+5VS_HDD

U11

110
RST#

CS4280
AUDIO

PC97338VJG
Super I/O

25

J510
MODEM
CONN.

166
PRST#

U25
PCI 1225
PCMCIA/
CARD BUS
CONTROLL

14

U33
TPS2216
POWER
SWITCH
MATRIX

-63-

6120N N/B MAINTENANCE


8.2 NO DISPLAY (System Failure)
***** CLOCK CIRCUIT CHECKING *****
VCC_CMOS
3

R126

X500
3
2 14.318MHz

C220
10P

U22

27

Clock
Generator

U503

1M

R167

CPU
SOCKET

C219
10P

33

BSEL0
AJ33

R87
2.7K

2
3

BCLK

VCC_CMOS

BSEL100

R228

R236

47K

Q10
MMBT3904

PICCLK

GCLKO

HCLKPII

FRQ_SEL

R162

33

24

R163

33

HCLKBX

66M Hz

R124

18

PCLKBX

33 M Hz

R103
18

U16

R235 66M Hz
10 DCLKO

R105

440ZX

DCLKO

+2.5V_CPUIO

SEL100/66#
PCI_STP#

PCI_STP#
R125

33

PCLKPIIX4

26

R164

33

14MPIIX4

13

R142

33

USB_48M

10

14

R123

U24

R121

R149

33

CLOCK

PIIX4

JL509

33 M Hz

PCLKMODEM

JL508

IO_48M

SDRAMCLK0 66M Hz

61
74

26

R131

SDRAMCLK1 66M Hz

23

R130

SDRAMCLK2

22

R129

SDRAMCLK3

111

J4
SODIMM
SOCKET

66M Hz

61

66M Hz

74

TPS2206

POWER
SWITCH
MATRIX

J510

180

U22

L18
25

+3V

U25

L16

W137

+3V
L17

VDDL

12 VDD48

CARD BUS
CONTROL

24

8
VDDPCI
VDD 19
VDDREF 28

U24

U11

PIIX4
SODIMM
SOCKET

CS4280-CQ
AUDIO

33

R132

+2.5V_CPUIO

PCLKCARD

PCLKAUDIO
33 M Hz

27

U21
W40S11

U33

32K_PWRMX

33
33

SODIMM
SOCKET

JL510

SUSCLK

32K_CARD 151
R120

BUF_IN

100M Hz

11

R106

VGA_32K

FRQ_SEL

20

DCLKWR/RD

DCLKWR

FRQ_SEL

R179
10K
16

10
DCLKRD

W137

J3

ATI RAGE
LT PRO
VGA

GCLKIN

66M Hz

23

U18

CLKAGP
66 M Hz
R110
18

W37

U29
IO_48M

PC97338VJG
SUPER I/O

+3V

U21 W40S11
OE

1,5,10,
VDD1~5 19,24,28

L15
+3V

SMBDATA

14

SMBCLK

15 SCLK

SDATA

L14
13

-64-

6120N N/B MAINTENANCE


8.3 VGA CONTROLLER FAILURE
Symptom:
There is no display on both LCD and Monitor although powerpower-onon-selfself-test is passed.
U20
U14
ON BOARD
SGRAM

AGP
AGP
BUS
BUS

VRAS#0
VCAS#0
VCS#0
VMCLK
VDSF
VWE#

VMA{10:0}
VDQM#{7:0}
VCS1#
VCS#3

LCD

VMD{63:0}

J1
Back Light
Controller

U16
INTEL
440ZX

G_AD{31:0}
Control
Signals

U18
ATI RAGE
LT PRO

J2
PANLE_VDD
TXCLKOUT+
TXCLKOUT-

TXOUT0+
TXOUT0-

TXOUT1+
TXOUT1-

TXOUT2+
TXOUT2-

J505
XTALIN
XTALOUT
CLKAGP
SCH.2

VGA
CONTROLLER

RED
GREEN
BLUE

HSYNC
VSYNC

DDCK
DDDA

ANALOG
CRT
DISPLAY

J509

VGA_32K
TV_CRMA
TV_LUMA
TV_COMP

TV

-65-

6120N N/B MAINTENANCE


8.3 VGA CONTROLLER FAILURE
Symptom:
There is no display on both LCD and monitor although powerpower-onon-selfself-test is passed.
VGA Controller Fail

1.Try another working monitor or


LCD module.
2.Remove all of I/O device from
M/B except LCD or monitor.

Display
OK?

Yes

Board-level
Troubleshooting

1.Replace faulty LCD or monitor.


2.Connect the I/O device to M/B
one at time to find out which part
is causing the problem.

One of the following parts on the VGA board may be


defective, use an oscilloscope to check the following signals or
replace the parts one at a time and test after each replacement.

No
1.Make sure that J2 connector on the M/B
is soldering OK.
2.Discharging CMOS by removed the
CMOS back-up battery to avoid the
case of no display caused by display
type setup error.

Display
OK?
No

Yes

Parts:
Replace
Motherboard

Replace faulty parts and one at


time to find out which part is
causing the problem.

U18
U14
RP50
RP26
RP35
RP42
X2
J2

signals:
U20
RP51
RP23
RP37
RP46

J506

G_AD {31:0}
VRAS#0
VCAS#0
VCS#0
VMCLK
VDSF
VWE#
VMA{10:0}
VDQM#{7:0}
VCS1#
VCS#3

PANLE_VDD
TXCLKOUT+
TXCLKOUTTXOUT0+
TXOUT0TXOUT1+
TXOUT1TXOUT2+
TXOUT2RED
GREEN
BLUE
HSYNC
VSYNC
DDCK
DDDA

-66-

6120N N/B MAINTENANCE


8.4 LCD NO DISPLAY OR PICTURE ABNORMAL
Symptom:
The LCD shows nothing or abnormal picture, but it is ok for external
external monitor.
U20

U16

+3V

U14

V_AVDD

L11

ON BOARD
SGRAM

V_A2VDD

L8

P/PAVDD

L10

LPVDD

L9

INTEL

JS1

+VDD5S

U34
110

PC87570
95

XTALOUT

440ZX

R67
XTALIN

U18

C146
18P

G_AD
{31:0}

ATI RAGE
LT PRO
VGA
CONTROLLER

LID#
BLADJ

(Analogy)

1M
3
2
4

R19

J1
1K 5

VMAIN

+3V

X2
29.498528MHz

L5

R277
0

L7
R63
10K

C145
18P

6
7

4
3
2

LCD

10
9,8,7,6
5
4
3
2
1

FA4

INVERTER BD.

ENABKL_VGA
3

ENABKL_VGA
Q8
DTC144WK

R28
1M

+5V

Q4
DTC144WK 3
FPVCC

+3V

+12V

R223
10K

D
G
S

Q37
2N7002

D
G

C33
0.22U

Q3
SI2302DS
PANEL_VDD

L24

J2
20

Control
Signals

AGP
AGP
BUS
BUS

TXCLKOUT+
TXCLKOUTTXOUT2+
TXOUT2-

21
7
8
11
12

TXOUT1+

15

TXOUT1TXOUT0+

14
17

TXOUT0-

18

-67-

6120N N/B MAINTENANCE


8.4 LCD NO DISPLAY OR PICTURE ABNORMAL
Symptom:
The LCD shows nothing or abnormal picture, but it is OK for external
external monitor.
LCD NO DISPLAY

1. Turn on power.
2. Try to adjust the LCD backlight by the
keyboard hothot-key to avoid the case of LCD no
display caused by the backlight to be adjusted
to too dark.

Check
J2,Q3,Q4,Q37,Q8,
U18,U34,U14,U20,L24,
L5,L7,J1 for cold
solder
?

BoardBoard-level
Troubleshooting
Display
Ok?

Yes

One of the following parts or signals on the motherboard may be


Defective, use an oscilloscope to check the signals or replace the
the
Parts one at a time and test after each replacement.

End
Try another known good LCD
module.

Display
Ok?
No

ReRe-soldering

No

No

Yes

Yes

Replace
Motherboard
Replace following parts and
test after each replacement
1. LCD
2. Back-light board(D/A)
3. LCD cable

Parts:

Signals:

Q3
Q8
J2
U18
U14
L5
L14
FA4

CRT_IN#
ENABKL_VGA
BLADJ
PANEL_VDD
+3V
LCD_ID{2:0}
TXOUT{2:0}TXCLKOUT-

Q4
Q37
J1
U34
U20
L7
X2

VMAIN

FPVCC
+12V
TXOUT{2:0}+
TXCLKOUT+

-68-

6120N N/B MAINTENANCE


8.5 EXTERNAL MONITOR NO DISPLAY OR COLOR ABNORMAL
Symptom:
The CRT monitor shows nothing or abnormal color, but it is ok for
for LCD
L512

RED

U20
U14

L511

GREEN

ON BOARD
SGRAM

L510

BLUE

ANALOG
CRT
DISPLAY

1
2

U16

AGP
BUS

RED

U18

INTEL

L509

R507
33

L508

GREEN
BLUE

440ZX

R508
33

3
13
14
15
12
10

ATI RAGE
LT PRO

J505

HSYNC
VSYNC

+5V

VGA
CONTROLLER

VCC

Q24
2N7002
L507

DDCK

R506
4.7K

VCC
R505
4.7K

DDDA
L506

+3V

U24
INTEL
PIIX4

CRT_IN#

R11
1K

PORT REPLICATOR CONN.

Q25
2N7002

J508

R19
100K

D/CRT_IN#

1 FA501

62

2 FA501

27

4 FA501

29

D_DDDA
D_DDCK

7
6

2 FA504
3 FA504

21
23

BLUE
GREEN
RED

8
5
6

1 FA504
4 FA504
3 FA501

20
24
28

C501
100P

D_VSYNC
D_HSYNC

-69-

6120N N/B MAINTENANCE


8.5 EXTERNAL MONITOR NO DISPLAY OR COLOR ABNORMAL
Symptom:
The CRT monitor shows nothing or abnormal color, but it is OK for
for LCD.

Monitor no display

Try another known good monitor.

Display
OK?

Yes

BoardBoard-level
Troubleshooting

N0
Check the BIOS setup to see
if no display caused by the
display type is setup error.

Yes
Display
OK?
No

End
Replace
Motherboard

One of the following components or signals on the motherboard


may be defective or cold solder use an oscilloscope to check
The signals or replace the parts one at a time and test after each
replacement.
Parts:
M/B
U18
L506
L508
L510
L512
R507
R508
CA501
RP501

Signals:
M/B
J505
L507
L509
L511
CA502
R2
R3
Q24
Q25

RED
BLUE
VSYNC
CRT_IN#
DDCK
DDDA

GREEN
HSYNC

-70-

6120N N/B MAINTENANCE


8.6 MEMORY TEST ERROR
Symptom:
PIO debug board shows the port 378H error code is stopped at 27H,28H or 29H,
29H, or error message of memory failure
is shown.
J4
J3
MDR[0:63]

MD[0:63]

MAB#[0:13]
DQMA#[0:7]

U16

SCASA#

66

66

SRASA#

65

65

WEA#

67

67

MECC[0:7]

INTEL
69 71

440ZX

CSA#0
CSA#1

62 68

142

141

69 71

CSA#2
CSA#3

CKE#2
CKE#3

CLOCL BUFFER

Clock Detail See


Section 8.3. Clock Checking
+3V

SMBDATA0

SMBCLK

Q42
DTC144WK
SMBDATA

SMBDATA1

R239
10K

SMBDATA0/1

82371EB

141

CKE#0
CKE#1

CKE#2
CKE#3

PIIX4

142

CSA#2
CSA#3

CKE#0
CKE#1

U24

62 68

CSA#0
CSA#1

Q41 2N7002

Q40 2N7002

SMBDATA0

SMBDATA1

-71-

6120N N/B MAINTENANCE


8.6 MEMORY TEST ERROR
Symptom:
PIO debug board shows the port 378H error code is stopped at 27H,28H or 29H,
29H, or error message of memory failure
is shown.
Memory Test Error

1.If your system installed with expansion


DIMM module then check them for proper
installation.
2.Make sure that your DIMM sockets are OK.
3.Then try another known good SO-DIMM
modules.

Yes

Test
OK?

Board-level
Troubleshooting

Replace the faulty


DRAM module.

Replace
Motherboard

If your system host bus clock running at


100MHZ then make sure that DIMM
module meet require of PC 100.

Yes

Replace the faulty


DRAM module.

Yes
Re-soldering

No

No

Test
Ok?

Check
U16,U24,U22,U21
J3,J4,Q40,Q41,Q42
For any cold
solder?

One of the following components or signals on the motherboard


may be defective ,Use an oscilloscope to check the signals or
replace the parts one at A time and test after each replacement.
Parts:

Signals:

U16 U24
U22 U21
Q40 Q41
Q42
RP15 ~ RP18
RP33 ~ RP34
RP36 RP39
J3
J4

MDR[0:63]
MAB#[0:13]
DQMA#[0:7]
SCASA#
SRASA#
WEA#
MECCR[0:7]

CSA#0
CSA#1
CSA#2
CSA#3
CSA#4
CSA#5

CKE#0
CKE#1
CKE#2
CKE#3
CKE#4
CKE#5

SMBCLK
SMBDATA
SMBDATA0/1

No

-72-

6120N N/B MAINTENANCE


8.7 KEYBOARD TEST ERROR (INCLUDING EXTERNAL KEYBOARD & PS/2
MOUSE)
Symptom:
1. Error message of keyboard failure is shown or any key doesn
doesnt work.
2. PIO debug board shows the port 378H error code is stopped at 20H,21H
20H,21H,,30H or 31H.
31H.

J5
BIOSCS#

KI{7 : 0}

157

SA{18:0}

KO{15 : 0}

SD{7:0}
IOR#

158

IOW#

159

MEMR#

162

FA1
59

F2
EXTERNAL PS/2
KEYBOARD

K/M_DATA
1

PC87570

163

MEMW#

+5V

U34

L2

J503
4

13

AEN

14

IOCHRDY
IRQ1

156

KEYBOARD

60

K/M_CLK

5
3

6
2
6

CONTROLLER

M_DATA

IRQ12

R293
X6
32.768KHZ
C342
10P

57

153

20M

25

32KX1/32CLKIN

27

32KX2

C1
1000P

PS/2 MOUSE

M_CLK
58

5
2

CA1
100P * 4

C343
33P
SCH.17

-73-

6120N N/B MAINTENANCE


8.7 KEYBOARD TEST ERROR (INCLUDING EXTERNAL KEYBOARD & PS/2
MOUSE)
Symptom:
1. Error message of keyboard failure is shown or any key doesn
doesnt work.
2. PIO debug board shows the port 378H error code is stopped at 20H or 21H
21H,,30H or 31H.
31H.
KEYBOARD or MOUSE
TEST ERROR

Is K/B or
Mouse cable connected
to notebook
properly?

No

Correct
It.

Board-level
Troubleshooting

Try another known good keyboard or


mouse.
Replace
Mother board

No

Yes

Replace the faulty


Keyboard or
Mouse.

Yes
Re-soldering

No

One of the following parts or signals on the motherboard


may be defective, use an oscilloscope to check the signals
or replace the parts one at a time and test after each
replacement.

Yes

Test
Ok?

Check
U34, J5,
J503,L2,F2,FA1,
For cold
Solder?

Parts

Signals

U34
X6
J5
J503
L2
F2
FA1
RP47 ~ RP49
CA1

KI{7:0}
SA2
BIOSCS#
IOW#
EC_IRQ1
XTAL
K/M_DATA
K/M_CLK

KO{15:0}
SD{7:0}
IOR#
EC_IRQ12
M_DATA
M_CLK

-74-

6120N N/B MAINTENANCE


8.8 TOUCH-PAD TEST ERROR (1)
Symptom:
An error message is shown when the touchtouch-pad is enabled.
6120N
6120N mother board
+5V
TP_VCCA
C350
1U

+5V

19

28
9
17

33P

R268

680K

R267
220K
1

1OUT

69

1IN- 2
1IN+ 3
2IN+

13

2OUT

2IN-

5
6

R265
1M

1,5

CABLE

T0UCH PAD

TP_VCCA
R263
1M

TP/T_DATA
21

PC87570
3

KEYBOARD

C355
33P

1M 10

22

11 X1

R269

CONTROLLER

TOUCH-PAD
MODULE

J7

TP_VCCA
U5
TLC2262AID

U6
TPM749DB

R402
10K

TPVCCA

V+

TP/T_CLK

+5V

U34

AVCC
RST

R401
10K
70

VCC

C352

R271

23

680K

SCH. 21

X2

1 X7

C353

33P

12 MHz
C354
33P

U4
DS1267-10
TPVCCA
R264
10K

7 CLK
9 DQ

BUTTON

W1 5
W0

13

TP_VCCA

+5V

TP_VCCA
L32

3
12

R261
330

RST

4
11

H1
H0
L1
L0

VCC

16

L33

VB 1
8
GND

R270
10K

-75-

6120N N/B MAINTENANCE


8.8 TOUCH-PAD TEST ERROR (1)
Symptom:
An error message is shown when the touchtouch-pad is enabled.

TOUCHTOUCH-PAD ERROR

Is
setup
OK?

Check
J7 , U34 , X7
U4 , U5 , U6
for cold
solder?

No
Correct it.
Yes

Is Cable
Connected properly
(J7 ) ?

Board-level
Troubleshooting

RERE-SOLDERING

NO

No
Correct it.

Yes
Replace
Main board

Try another known good


touch-pad module cable.

One of the following parts or signals on the


motherboard may be defective, use an
oscilloscope to check the signals or replace the
parts one at a time and test after each
replacement.
SIGNALS:

PARTS:

Yes

Test
Ok?

YES

U34
U4
U6
Replace the
Faulty parts.

X7
U5
J7

CHARGE BD

T_CLK
T_DATA
TP/T_CLK
TP/T_DATA

No

-76-

6120N N/B MAINTENANCE


8.8 TOUCH-PAD TEST ERROR (2)
Symptom:
An error message is shown when the touchtouch-pad is enabled.

6120N
6120N mother board
+5V
R401
10K

R402
10K

U34

70

R262

T_CLK

J1
18

45

L3

L2

T_CLK

0
69

PC87570
KEYBOARD

TP/T_DATA

R266
0

T0UCH PAD

+5V

J514
TP/T_CLK

TOUCH-PAD
MODULE

CHARGE BOARD

T_DATA

11,12

C4
47P

17

46

T_DATA

J501

CABLE

1,2

L1

3,4
5,6

C3
47P

7,8

SCH.24

9 10

CONTROLLER

SCH.1

SW_LEFT

SW1

BUTTON

R2

SWL

0
SW2
1

SW_RIGHT

R5

SWR

0
C2
47P

C1
47P

-77-

6120N N/B MAINTENANCE


8.8 TOUCH-PAD TEST ERROR (2)
Symptom:
An error message is shown when the touchtouch-pad is enabled.
TOUCHTOUCH-PAD ERROR

Is
setup
OK?

No
Correct it.

Check
J513 , U34 , R262 ,
R266 , BATT/TP BD
for cold
solder?

Yes
Is
Cable
Connected properly
( CHARGE BD
J514 )
?

No
Correct it.

Board-level
Troubleshooting

Yes
Replace
Main board

Try another known good


touch-pad module, CHARGE
BD & cable.

Yes

Replace the
Faulty parts.

RERE-SOLDERING

NO

One of the following parts or signals on the


motherboard may be defective, use an
oscilloscope to check the signals or replace the
parts one at a time and test after each
replacement.
PARTS:

Test
Ok?

YES

U34
J514
R262
R266
CHARGE BD

SIGNALS:
TP/T_CLK
TP/T_DATA

T_CLK
T_DATA

No

-78-

6120N N/B MAINTENANCE


8.9 DISKETTE DRIVE TEST ERROR
Symptom:
An error message is shown while loading data from disk to system.
system.
+12V

+5V

R100
1M

Q16
SI2304DS

Q15
DTC144WK

+5VS_FDD

C293

FDD_PWR#

PHLD#

PHLDA#

INTEL
PCI BUS

82371EB
DMA
CTL_

FDDLED#
D6

16

39

51

IOCHRDY

38
37
36

DREQ2

IRQ6

95

DACK2#

32
45

U29

35
34
33

SD{7:0}

PC93338VJG

TC

L23

J515
59

44
30

DRV0#
DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK0#
WPROT#
RDATA#
MTR0#
DSKCHG

57
51
43
48
50
52

FDD

60
47
54
56
58
45
55
46

SA{15:0}

SUPPER I/O

AEN

U22
W137
CLOCK
SYNTHESIZER

R9
680

MTR0#
42

17

IOR#

PIIX4

U16

440ZX

IOW#

U24

C292
1U

FDD_MODE

18

14

R149
33

I/O 48MHz

-79-

6120N N/B MAINTENANCE


8.9 DISKETTE DRIVE TEST ERROR
Symptom:
An error message is shown while loading data from disk to system.
system.

DISKETTE DRIVE TEST ERROR

1. Try another known good diskette,and


check the floppy and cable for proper
installation.
2. Check BIOS setup.

Re - boot
OK?

Yes

Board-level
Troubleshooting

Try another known good


floppy module.

No

Yes

YES
RERE-SOLDERING

NO

Correct
It.

No

Re - boot
OK?

Check
U29,L23,J515
Q15,Q16 for cold
solder?

Replace faulty parts.

Replace main
Board

One of the following components or signals on the motherboard


may be defective or cold solder use an oscilloscope to check the
signals or replace the parts one at a time and test after each
replacement.
Parts

Signals

U29
U24
U16
U22
R100
Q15
Q16
L23
J515
R9
D6
R149

SA{15:0}
DACK2#
IOR#
SD{7:0}
I/O_48MHz
IRQ6

DREQ2
AEN
IOW#
TC

DRV0#
DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK0#
WPROT#
RDATA#
MTR0#
DSKCHG
FDD_MODE

-80-

6120N N/B MAINTENANCE


8.10 HARD DRIVE TEST ERROR
Symptom:
Either an error message is shown, or the drive motor spins nonnon-stop, while reading data from or writing data
to hardhard-disk.
+12V

Mother B/D

R98
1M

Q13
DTC144WK

+5V

Q12
SI2304DS

+5VS_HDD

C288

J515

HDD_PWR#

Q17
DTC144WK

HDD_RSTDRV

PDCS3#
RP63
RP66

PDD [0:15]

SOUTH BRIDGE
PIIX4

RCS1P#

RCS3P#

33 * 8

14

13

PDIOR#
PDDACK#

EIDE
CONTROLLER

12

PDA2

11

RP70 33 * 8

PDA1
2

PIORDY

R94
1K

PDDREQ

+5VS_HDD

HDD LED
D5
R8
680

22

RPDIOR#

20

RPDDACK#

16

RDAP0

10

RDAP2

RDAP1

12

RIRQ14

14

PIORDY

18

RPDDREQ

24

RP44
33 * 4

Q11
2N7002

+5VS_HDD

RPDIOW#

IRQ14

RDDP[0:15]

16

+5VS_HDD

Intel
FW82371

44

10

RP70
33 * 8

PDA0

HDD_RST#
7

RP70
33 * 8

PDIOW#

3
4

RP38
10K * 4

PDCS1#

U24

+5VS_HDD
3

C284
1U

R143
5.6K

15

RP70
33 * 8

PIDEACT#

-81-

6120N N/B MAINTENANCE


8.10 HARD DRIVE TEST ERROR
Symptom:
Either an error message is shown, or the drive motor spins nonnon-stop, while reading data from or writing data
to hardhard-disk.
Hard drive
Test error

1. Check if BIOS setup is OK.


2. Try another working drive and
cable.

Board-level
Troubleshooting

One of the following parts or signals on the motherboard may


be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Signals:

Parts:
Re - boot
OK?

Yes
Replace the faulty parts.

No

Replace
Motherboard

Check the system driver for proper


installation.

No

Re - test
OK?

U24
RP44
RP66
Q12
Q17
Q11
J515

RP63
RP70
Q13

HDD_RSTDRV
PDCS1#
PDCS3#
PDD [0:15]
PDIOW#
PDIOR#
PDDACK#
PDA0
PDA2
PDA1
IRQ14
PIORDY
PDDREQ
+5V
HDD_PWR#

HDD_RST#
RCS1P#
RCS3P#
RDDP[0:15]
RPDIOW#
RPDIOR#
RPDDACK#
RDAP0
RDAP2
RDAP1
RIRQ14
PIORDY
RPDDREQ
PIDEACT#
+5VS_HDD

Yes
End

-82-

6120N N/B MAINTENANCE


8.11 CD-ROM TEST ERROR
Symptom:
An error message is shown when reading data from CDCD-ROM drive.
+12V

Mother B/D
Q21
DTC144WK
CD_PWR#

R140
1M
3

RP38
10K * 4

C557
1U

U9

Q19
DTC144WK

CD_RSTDRV
SDCS3#

EIDE
CONTROLLER

SDIOW#

A21

18
20

AUDIO
CS4297

SOUTH BRIDGE
PIIX4

L25

B20,B21

U24

A19,A20

C238

SDCS1#
SDD [0:15]

11

SDA2

12

33 * 8

CDROM_GND

A2

+5VS_CDROM

A18

RCS1S#

B18

RP60
33 * 8

RDDS[0:15]

RP60
33 * 8

RSDIOW#

B13

RSDIOR#

A12

RSDDACK#

A14

14

15

13

RP44
33 * 4

R150
1K

SDDREQ

CDROM LED
D4
R147

R158
5.6K

CD-ROM

RDAS0

B17

RDAS2

A17

RDAS1

B16

RIRQ15

B15

SIORDY

B14

RSDDREQ

A11

Q14
2N7002

B3

IRQ15

680

B1

33 * 8

+5VS_CDROM

+5VS_CDROM

CDROM_LEFT

RCS3S#

SDA1

SIORDY

C76
0.22U R44
C73
0
0.22U

CDROM_RIGHT A1

10

SDDACK#
RP60

R40
0

SDIOR#

SDA0

19

C536
0.22U

CD_RST#

RP65
RP62

J513

+5VS_CDROM
Q18
SI2304DS

+5VS_CDROM

Intel
FW82371

+5V
D

RP62
33 * 8

B19

SIDEACTS#

-83-

6120N N/B MAINTENANCE


8.11 CD-ROM TEST ERROR
Symptom:
An error message is shown when reading data from CDCD-ROM drive.
CDCD-ROM
TEST ERROR

1. Try another known good compact disk.


2. Check install for correctly.
BOARD-LEVEL
TROUBLESHOOTING

One of the following parts or signals on the motherboard may


be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.

YES

Test
OK?

Replace the faulty parts.


NO

Check the CD-ROM driver for proper


installation.

RE - TEST
OK?

NO

REPLACE
MOTHERBOARD

PARTS:

SIGNALS:

U24
RP44
RP60
RP62
RP65
R530
R528
L25
Q18
Q21
Q19
J513

CD_RSTDRV
SDCS3#
SDCS1#
SDD [0:15]
SDIOW#
SDIOR#
SDDACK#
SDA0
SDA2
SDA1
IRQ15
SIORDY
SDDREQ
+5V
CD_PWR#

CD_RST#
RCS3S#
RCS1S#
RDDS[0:15]
RSDIOW#
RSDIOR#
RSDDACK#
RDAS0
RDAS2
RDAS1
RIRQ15
SIORDY
RSDDREQ
SIDEACTS#
+5VS_CDROM

YES

END

-84-

6120N N/B MAINTENANCE


8.12 CMOS TEST ERROR
Symptom:
1. Error code is stopped at 22H.
2. CMOS data lost, or inaccurate system time & date.
***To clear CMOS data, remove battery pack
and disconnect AC adapter first, then remove
CMOS battery compartment cover on the
bottom side of notebook and take off the
CMOS back-up battery from its
socket for at least 10 minutes.***

U24

VDD5
3

RTCX1

D12
RLS4148

Intel

D10
BAV99
1

C282
18P

PIIX4
VCC_RTC
VCC_ECRTC
1

X5
32.768KHZ

CMOS

3
2

RAM
RTCX2

C67
1U
C283
18P

R41
D11
BAV70LT1

1K

BT501

-85-

6120N N/B MAINTENANCE


8.12 CMOS TEST ERROR
Symptom:
1. Error code is stopped at 22H.
2. CMOS data lost, or inaccurate system time & date.
CMOS TEST ERROR

1. Press the F2 key to re-set the date and time.


2. Check the CMOS battery for proper installation.
3. Turn off power for 1 hour then turn on again.
Board-level
Troubleshooting

One of the following parts or signals on the motherboard may


be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.

Yes
Re - boot
OK?
No
Replace
Motherboard

End
Try another known good
CMOS back-up battery.

Re - boot
Ok?

Yes

Parts:

Signals:

U24
BT501
D10
D11
D12
R41
X5
C282
C283
C67

RTCX1
RTCX2
VCC_ECRTC
VDD5

Replace
Battery.

No

-86-

6120N N/B MAINTENANCE


8.13 SIO PORT TEST ERROR
Symptom :
An error message occurs when a mouse or other I/O device is installed.
installed.
+3V

SD {7:0}
SA {15:0}

IOR#

17

IOW#

16

AEN

U24

COM1DCD#

10

74

COM1DSR#

11

73

COM1RXD

12

72

COM1RTS#

71

COM1TXD

69

COM1DTR#

70

COM1CTS#

13

68

COM1RI#

14

100

IO_48M Hz

Super I/O
PC93338VJG

CLOCK

Southbridge
D2
BAW56

RI#

19

D_DCD#

4 FA3

18

D_DSR#

17

D_RXD

22

D_RTS#

ADM3311 21 D_TXD
ARU 20 D_DTR#

4 FA2

16

D_CTS#

15

D_RI#

+3V

R5
100K

R4
100K

MODEM_RI#

SIO

SD

CA503
CA504

+3V

C11
0.1U

R7
100K

CARD_RI#
3

D10
2

RS232_OFF#

J507

3
Q2
DTC144Wk

+3V

25
V-

VCC

U2

23

+3V

3
V+

18

RSTDRV

PIIX4

U29

75

RLS4148
1

LOOPBACK CONNECTOR
FOR SIO TEST:

PIN DEFINITION OF SIO PORT:


PIN 1 : DCD----- Data Carrier Detect

PIN 2 : RD------- Receive Data


PIN 3 : TD------- Transmit Data
PIN 4 : DTR----- Data Terminal Ready
PIN 5 : SG-------- Signal Ground

GND

Q1
DTC144WK

PIN 6 : DSR------ Data Set Ready

PIN 7 : RTS------ Request To Send

PIN 1, 4, 6

Short

PIN 8 : CTS------ Clear To Send

PIN 2, 3

Short

PIN 9 : RI-------- Ring Indicator

PIN 7, 8, 9

Short

GND

-87-

6120N N/B MAINTENANCE


8.13 SIO PORT TEST ERROR
Symptom :
An error message occurs when a mouse or other I/O device is installed.
installed.
SIO TEST ERROR

Check
U29, U2
For cold
solder?

1. Check whether mouse or others I/O


device are installed properly.
(Including driver)
2. Try another working mouse or I/O
device.

Re - test
OK?

Yes

Board-level
Troubleshooting

Correct
It.

Replace
M/B board

Yes
Re-soldering

No
One of the following parts or signals on the motherboard
may be defective,plug SIO loop back at SIO port and run
SIO test program then use an oscilloscope to check
following signals or replace the parts one at a time and
test after each replacement.

No

No

BIOS
Setup
OK?
Yes

Correct
It.

Parts:

Signals:

U29
U2
J507
Q1
Q2
D2
D10
CA503
CA504
FA2
FA3

COM1DCD#
COM1DSR#
COM1RXD
COM1RTS#
COM1TXD
COM1DTR#
COM1CTS#
COM1RI#
RS232_OFF#
+3V

D_DCD#
D_DSR#
D_RXD#
D_RTS#
D_TXD#
D_DTR#
D_CTS#
D_RI#

-88-

6120N N/B MAINTENANCE


8.14 PIO PORT TEST ERROR
Symptom:
When a print command is issued, printer prints nothing or garbage.
garbage.
+5V
U1
PACS1284-02Q/T

D1
RLS4148

J506

P_LPD [0:7]

D/LPD [0:7]

SD {7:0}
SA {15:0}

U24
PIIX4

IOR#

17

IOW#

16

AEN

18

IO_48M Hz

100

D/STB#

14

16

P_STB#

79

D/SLIN#

D/SLIN#

17

78

D/INIT#

D/INIT#

16

76

D/AFD#

28

28

D/AFD#

14

77

D/ERR#

27

27

D/ERR#

15

83

D/ACK#

15

15

D/ACK#

10

82

D/BUSY

12

12

D/BUSY

11

81

D/PE

10

10

D/PE

12

80

D/SLCT

D/SLCT

13

U29

Super I/O

Southbridge
RSTDRV

93

PC93338VJG

CLOCK

PIN DEFINITION OF PIO PORT


PIN 1
PIN 2-9
PIN 10
PIN 11
PIN 12
PIN 13

STB
D0 - D7
ACK
BUSY
PE
SLCT

STROBE SIGNAL
PARALLEL PORT DATA BUS D0 TO D7
ACKNOWLEDGE HANDSHANK
BUSY SIGNAL
PAPER END
PRINTER SELECTED

PRINTER

PIO port

LOOPBACK CONNECTOR FOR PIO TEST:


PIN 14
PIN 15
PIN 16
PIN 17
PIN 18-25:

AFD AUTO LINE FEED


ERR ERROR AT PRINTER
INIT INITIATE OUTPUT
SLIN PRINTER SELECT
SIGNAL GROUND

PIN 1, 13
PIN 2, 15
PIN 12, 14

SHORT
SHORT
SHORT

PIN 10,16
PIN 11,17

SHORT
SHORT

LOOPBACK CONNECTOR FOR EPP TEST:


PIN 1, 2, 4, 6, 8
PIN 3, 5, 7, 9, 16
PIN 18, 19, 20, 21, 22, 23, 24, 25

SHORT
SHORT
SHORT

-89-

6120N N/B MAINTENANCE


8.14 PIO PORT TEST ERROR
Symptom:
When a print command is issued, printer prints nothing or garbage.
garbage.
PIO test error

1. Check whether cables , printer & printer


driver are installed properly.
2. Check if printer is on and in ready status.
Board-level
Troubleshooting
Re - test
OK?

Yes
Correct it.

Parts:

No
BIOS
Setup
OK?

One of the following parts or signals on the motherboard may be


Defective, plug in PIO loop back at PIO port and run PIO test
program then use an oscilloscope to check the following signals or
replace the parts one at a time and test after each replacement.

No
Correct it

Yes

Replace
M/B board

U29
U1
J506
D1

Signals:
D/LPD [0:7]
D/STB#
D/SLIN#
D/INIT#
D/AFD#
D/ERR#
D/ACK#
D/BUSY
D/PE
D/SLCT

P_LPD [0:7]
P_STB#

Try another known good printer.

Printing
Ok?

Yes

Replace
printer.

No

-90-

6120N N/B MAINTENANCE


8.15 IrDA TEST ERROR
Symptom:
The infrared function failure (ex. : can
cant detect Ir. device or transfer data from Ir.)

GPO12
GPO13

+3VS_FIR

IRMD0
IRMD1

+3VS_FIR

+3V

JL506

C502
10U

SD {7:0}
SA {15:0}

U24
PIIX4
Southbridge

IOR#

17

IOW#

16

AEN

18

RSTDRV
IO_48M Hz

100

U501
HSDL-3600

C501
0.47U

U20
66

IRMODE

65
63

IRRxA
IRTX

IRMODE
IRMD0
IRMD1

Super I/O
IRRxA
IRTX

PC93338VJG
+3VS_FIR

CLOCK

R502

4.7K

R501

4.7K

1
2
3
4
5
6
7
8
9
10

VCC
AGEND
FIR_SEL
MD0
MD1
NC
GND
Rxd
Txd
LEDA

11

GND

U501

Mode 0

Mode 1

FIR_SEL

RX Function

TX Function

Shutdown

Shutdown

SIR

Full Distance Power

SIR

2/3 Distance Power

SIR

1/3 Distance Power

MIR/FIR

Full Distance Power

MIR/FIR

2/3 Distance Power

MIR/FIR

1/3 Distance Power

X = Dont Care

Rx

Tx

HSDL-3600

PIN

Symbol

Description

VCC

Supply Voltage

AGND

Analog Ground

FIR_SEL

FIR Select

MD0

Mode 0

MD1

Mode 1

NC

No Connection

GND

Ground

RXD

Receiver Data Output

TXD

Transmitter Data Input

10

LEDA

Anode

-91-

6120N N/B MAINTENANCE


8.15 IrDA TEST ERROR
Symptom:
The infrared function failure (ex. : can
cant detect Ir. device or transfer data from Ir.)
IrDA TEST ERROR

1. Check if IrDA function of the device


is On.
2. To make sure there is no any obstacle
between these two Ir port and not out
of the spec. angle and range.

Re - test
OK?

Board-level
Troubleshooting

Parts:

Signals:

U29
U24
U501
R501
R502
C502
C501

TC
SA{15:0}
DREQ2
DACK2#
AEN
IOR#
IOW#
SD{7:0}
IO_48M Hz

Yes
Correct it.
Replace
M/B board

No

No

BIOS
setup
OK?

One of the following parts or signals on the motherboard may


be defective,plug Game Port loop back at Game Port and run
Game Port test program then use an oscilloscope to check
following signals or replace the parts one at a time and test
after each replacement.

Correct it.

IRMODE
IRMD0
IRD1
IRRXA
IRTX
+3V_FIR

Yes

-92-

6120N N/B MAINTENANCE


8.16 USB PORT TEST ERROR
Symptom:
An error occurs when a USB I/O device is installed.
+5V
F3

D/USB_PWR0
L4

USB_OC0#

R219
470K

C16
10U
10V

R242
560K
OC0#

INTEL
440ZX

U24
PCI BUS

PIIX4

VCC

USBP0+

27

H3

USBP0

R176

27

USBP1+ F1

USBP1+

R156

27

USBP1 H2

USBP1

R168

27

USBP0

G2

82371EB

C250
47P

J2

D/USBP0+

L514

D+

D/USBP0

L513

DGND

1
3
2
4
GND1
GND2

C262 R155
47P
15K
C249 C263
47P 47P

DMA

J504

USB_OC0#
R175

USBP0+

U16

J1

C15
1000P

R182
15K

USBP1+

USBP1

USB_OC1#

CTL_

F4

D/USB_PWR1

+5V
USB_OC1#

J508

FA502

R152 R225
15K 15K

R218
470K
R243
560K

C310
10U
10V

PORT REPLICATOR CONN.

-93-

6120N N/B MAINTENANCE


8.16 USB PORT TEST
ERROR
Symptom:
An error occurs when a USB I/O device is installed.
USB Test Error

Check if the USB device ,Is installed


properly.(Including driver)
Board-level
Troubleshooting
Yes

Correct
It.

Test
OK?

Check the following parts for cold solder or one of the following parts
on the mother-board may be defective, use an oscilloscope to check the
following signal or replace the parts one at a time and test after each
replacement.

Parts:

No

Signals:

M/B

Replace another known


good USB device.

Replace
M/B or I/O board
Yes

Re-test
OK?

Correct
It.
No

U24
J504
R175
R176
R156
R168
L513
L514
F3
L4
R219
R242

USB_OC0#
USBP0USBP0+
D/USB_PWR0
+5V

USB_OC1#
USBP1USBP1+
D/USB_PWR1

F4
R218
R243

Replace M/B or go into


board-level Troubleshooting.

-94-

6120N N/B MAINTENANCE


8.17 AUDIO DRIVE FAILURE
Symptom:
No sound from speaker after audio driver is installed.
+5V

VA

Input
InputOf
OfThe
TheAudio
AudioSubsystem
Subsystem

+3V
L521
0
1
9

C121
10U
16V

L520

25

C527
0.1U

38

C525
0.1U

X1
24.576MHZ

C/BE{3:0} #

U11

DEVSEL#

CRYSTAL

ARST#

100

XTLIN/OUT

20

ASDOUT

97

18

11
5

U9

FRAME#

CS4280

STOP#
AUDIO_PCIRST#

98

R21

33

ASYNC

99

AUDIO

REQ2#

R20

96

GNT2#

ASDIN

CDROM_R

DRIVE

ABITCLK

CS4297

CDROM_GND

19

13

R49
10K
C93
390P

23

C94

J502
4
2
1

L504

C529
47P

MIC IN

L28

R39
100K

C76
0.22U

R43
100K

R40
0

CDROM_RIGHT

R44
0

CDROM_LEFT

A1

B1

CD-ROM

CDROM_GND

C73
0.22U

B2

2
1

R45 MODENSPK
2

5
4

PIN SIDE
VIEW

J510
MODEM

6.8K

R530
10K

5
4

J508
C53
0.1U

C61
0.1U

R29
2.6K

FA503
6

R526
10K

R32
2.6K

D/LINE_IN_R

D/LINE_IN_L

42

PORT REPLICATOR CONN.


5

44

R528
10K

+3V
R50
10K

Q7
MMBT3904

LINE_IN/L

12 PC/BEEP

0.1U

From PIIX4

LINE_IN/R

L519

C530
1U

C536
0.22U

C542
0.01U
24

+3V

PCLK_AUDIO

4.7K

1
2

J513

0.1U

33

PCI
BUS

4.7K

PHONE C80

CODEC

AC97
CODEC LINK

SPKR

CDROM_L

8
10

R35

XTL/IN

TRDY#
IRDY#

R529

C69
0.22U

21

AD{31:0}

MIC1

L3

JP4

C95
0.1U

CARDSPKR#
149

U25
Card Bus
Controller

-95-

6120N N/B MAINTENANCE


8.17 AUDIO DRIVE FAILURE
Symptom:
No sound from speaker after audio driver is installed.
VA

Output
OutputOf
OfThe
TheAudio
AudioSubsystem
Subsystem

L520

+3V

L521
0

+5V

25

1
9

C527
0.1U

38

JP4

C121
10U
16V
C525
0.1U

C508
1U

AD{31:0}
2

C/BE{3:0} #

36

C528
AOUT_R 2.2U

35

AOUT_L

XTL/IN

X1
24.576MHZ

3 XTLIN/OUT

C511
0.1U

R511

R512

10K

15K

R513

R514

10K

33K

U3
TPA0202
Amplifier

TRDY#
IRDY#
DEVSEL#

U11
CRYSTAL

100

ARST#

97

ASDOUT

98

ASDIN

U9
11

C524
2.2U

FRAME#
STOP#

CS4280

GNT2#

PCI
BUS

33

ASYNC

99

RST_PCI2#
REQ2#

R21

CS4297

AUDIO

R20

96

DRIVE

10

ABITCLK

CODEC

VR1
10K

C537
0.1U

41

C531
0.1U

7 18

J514

20 RHP IN
21 RLINE IN

22
15

ROUT+
ROUT-

47
49

4 LLINE IN
5 LHP IN

3
10

LOUT+
LOUT-

48
50

R515
100K
C522
1U

C518
0.1U

D27
BAW56
3

J2
J5

R523

R524

10K

15K

R522

R519

10K

33K

+VA

C25
100U

C12
100U

L502
R15
1K

R517
100K

C503
100P

HEADPHOEN
3
5
4
2

R1
1K

C504
100P

R230
100K

J508

FA503
D/LINE_OUT_R

D/LINE_OUT_L

D/HP_IN

J501

L503

5
4

1
2

From PIIX4

J4

14 SE/BTL#
16 HP/LINE#

39

AC97
CODEC LINK

SPK_OFF

L516

11 MUTE IN

33

CLK_PCI_AUDIO

BATT /TP
BD

+5V

PHONE JACK U3 PIN14,16 OUTPUT


PLUG IN
HI
HP IN
UNPLUG
LOW
LINE IN

1
1

5
4

PIN SIDE
VIEW

41
45

PORT REPLICATOR CONN.


75

-96-

6120N N/B MAINTENANCE


8.17 AUDIO DRIVE FAILURE
Symptom:
No sound from speaker after audio driver is installed.

AUDIO DRIVE FAIL

1. Check to see that all cables and power


cord are connected properly.
2. Make sure that all of software drivers
are installed properly.

Re - test
OK?

CABLES: Internal speaker


External speaker
Microphone
Line in

Is audio
driver initiated
OK?

Yes

Board-level
Troubleshooting

No
Try another known good
speaker and cables.
Replace
Motherboard
Yes

Test
OK?

Correct it.
No
Yes

Yes

If no sound from
Microphone then

End

M/B U11,U9,U3 and X1 may be


cold solder or failure, use an
oscilloscope to check below signals
before replacing it.

No

If no sound from
Line-in then
If no sound from
CD-ROM then
If no sound output
to speaker then

Signals:

A
B
C
D

PCI BUS
AD{31:0}
C/BE{3:0}#
AUDIO_PCIRST#
TRDY#
IRDY#
STOP#
P_GNT1#
DEVSEL#
FRAME#
P_REQ1
P_IRQC#
PCLKAUDIO

AC97 Codeo Link


ARST#
ASDOUT
ASDIN
ASYNC
ABITCLK
+3V
+5V
VA

No

-97-

6120N N/B MAINTENANCE


8.17 AUDIO DRIVE FAILURE
Symptom:
No sound from speaker after audio driver is installed.

Check
C69,L504,
MIC1,J502,L3 for
cold solder or
defective?

Check
FA503,R29,
R32,C61,C53 for any
cold solder or
defective?

Check
J513,R40,
R44,C76,C536,C73 for
cold solder or
defective?

Check U3
,C528,C524,VR1,
R511,R513,R522,R523,R512,
R514,R519,R524,C508,C511,C518,
C522,C12,C25,L502,L503,
J501,CHARGE BD.
for cold solder or
defective?

YES

Parts replacement or
re-soldering.
NO

YES

Parts replacement or
re-soldering.

YES

Parts replacement or
re-soldering.

NO
Parts replacement or
re-soldering.

NO
Check
U11,X1,U9,
R20,R21,L6,L520,
L516, for cold solder
or defective?

NO

YES
Parts replacement or
re-soldering.

-98-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(1)
Part Number
442999900006
441600002009
541666570003
541666570006
541666703004
441999900014
441665700012
298000000002
338530010005
338712010015
340665700011
221666540001
342665700045
342666600002
342665700023
342665700024
342665700003
344665700043
422600000101
422600000103
332300000115
332300000117
272075103702
272075103702
272005103401
312161002631

Description
AC ADPT ASSY OPTION;6120N
AC ADPT ASSY;PWR-60B,CV/CC-19 MS
ACCESSORY KIT;EN,6020-UTILITY ON
ACCESSORY KIT;EU,6020
AK;4-EU,BOX,6020+ CTO
BATT ASSY OPTION;NIMH,4.5/4AH,60
BATT ASSY;11V/4.5AH,NIMH,SYO,602
BATTERY HOLDER;FOR CR2032,BH-800
BATTERY;LI,3V/220MAH,CR2032
BATTERY;NIMH,1.2V/4.5AH,4/3A,SAN
BEZEL ASSY;TEAC,CDROM,6020
BOX;INNER AK,6120
BRACKET;CD-ROM,6020
BRACKET;HDD,TITAN
BRACKET;HYUNDAI,LCD 2ND,L,6020
BRACKET;HYUNDAI,LCD 2ND,R,6020
BRACKET;IO,6020,PRT
BUTTON;TOUCHPAD 2ND,6020
CABLE ASSY;A/D TO CHASSIS,PWR-60
CABLE ASSY;FAX MODEM,10P,4C,AUST
CABLE;FFC,FDD,6020
CABLE;FFC,TOUCHPAD,12P,6020
CAP;.01U ,50V,+80-20%,0603,SMT
CAP;.01U ,50V,+80-20%,0603,SMT
CAP;.01U ,CR,50V,10%,0805,X7R
CAP;.01U ,PE,100V,5% ,AX

Location

BT501

C136,C137,C141,C142
PC7,509,523,511
C2
C8

Part Number
272075104701
272075104701
272003104701
272005104701
272072224701
312263303851
272002474401
272075102701
272075102701
312431001044
312431001043
272075102403
272005102401
272075101701
272075100701
272021106501
272012106701
272022106701
272023106501
272043106501
272043106501
272073180401
272071105701
272013105501
272013105501
272002105701

Description
CAP;.1U ,50V,+80-20%,0603,SMT
CAP;.1U ,50V,+80-20%,0603,SMT
CAP;.1U ,CR,25V ,+80-20%,0805,Y
CAP;.1U ,CR,50V,+80-20%,0805,Y5
CAP;.22U ,16V ,+80-20%,0603,Y5V,
CAP;.33U ,POLY,275V,20%,X2,AX
CAP;.47U ,CR,16V ,10%,0805,X7R,S
CAP;1000P,50V ,+80-20%,0603,SMT
CAP;1000P,50V ,+80-20%,0603,SMT
CAP;1000P,CR,1KV ,10%,DISK,X7R
CAP;1000P,CR,1KV ,10%,DISK,Y5P
CAP;1000P,CR,50V,10%,0603,X7R,SM
CAP;1000P,CR,50V,10%,0805,X7R
CAP;100P ,50V ,+80-20%,0603,SMT
CAP;10P ,50V ,+80-20%,0603,SMT
CAP;10U ,10V ,20%,1210,X7R,SMT
CAP;10U ,16V ,+80-20%,1206,Y5U,
CAP;10U ,16V,+80-20%,1210,Y5V,S
CAP;10U ,25V ,20%,1210,Y5U,SMT
CAP;10U ,CR,25V ,20%,1812,Y5U,S
CAP;10U ,CR,25V ,20%,1812,Y5U,S
CAP;18P ,CR,25V ,10%,0603,NPO,S
CAP;1U ,CR,10V ,80-20%,0603,Y5
CAP;1U ,CR,25V ,+80-20%,1206,S
CAP;1U ,CR,25V ,+80-20%,1206,S
CAP;1U ,CR,16V ,-20+80%,0805,SM

Location
C10,C100,C102,C104
PC4,5,15,501,503,
PC2
C1,9,10,12,17
C33,C338,C536,C69
C6
C501
C1,C103,C15,C172
PC502,506
C16,20
C5
PC6
C14,18
C3,C503,C504,C505
C203,C204,C215,C219
PC35,PC524,PC533
C16,PC16,PC32,PC4
PC504
PC534,PC535
PC532,PC536
PC1,PC524
C145,C146,C282,C283
C159,C173,C174,C189
PC23,PC522
PC3
C101,C109,C115,C116

-99-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(2)
Part Number
272002105701
272002105701
272012225702
272075222701
312262201741
272075221302
272005221401
272431225501
272075220701
272041226501
272073330701
272075391301
272012475701
312434701041
272075470701
272075470701
272431476502
272005560401
272431566501
221665720003
221665720004
431667910001
523466570004
523499995002
523410295018
451665700093

Description
CAP;1U ,CR,16V ,-20+80%,0805,SM
CAP;1U ,CR,16V ,-20+80%,0805,SM
CAP;2.2U ,CR,16V ,+80-20%,1206,Y
CAP;2200P,50V ,+80-20%,0603,SMT
CAP;2200P,POLY,250V,10%,Y1,AX
CAP;220P ,50V ,5% ,0603,SMT
CAP;220P ,CR,50V ,10%,0805,X7R,S
CAP;220U ,TT,4V,20%,7243,OS-CON,
CAP;22P ,50V ,+80-20%,0603,SMT
CAP;22U ,CR,10V ,20%,1812,X7R,S
CAP;33P ,25V ,+80-20%,0603,SMT
CAP;390P ,CR,50V,5%,0603,NPO,SMT
CAP;4.7U ,CR,16V ,+80-20%,1206,Y
CAP;4700P,CR,1KV ,10%,DISK,Y5P
CAP;47P ,50V ,+80-20%,0603,SMT
CAP;47P ,50V ,+80-20%,0603,SMT
CAP;47U ,6.3V,20%,SP-CON,7343,S
CAP;56P ,CR,50V ,10%,0805,NPO,S
CAP;56U ,TT,4V,20%,SP-CON,7343,
CARTON;AC ADAPTER,6020
CARTON;W/O ROC,N-B,6020
CASE KIT;6120N,ID2
CD ROM DRIVE ASSY;24X,CD-224E,60
CD ROM DRIVE OPTION;24X,6020
CD ROM DRIVE;24X,CD-224E-A92,TEA
CD ROM ME KIT;24X,CD-224E-A92,60

Location
PC510,505
C15
C260,C298,C301,C43
C157
C23
C31,C32,C34,C35
C4
PC17,PC504,PC505
C91,C99
C98,PC28
C343,237,5
C93
C105,C125,C126,C127
C22
C249,C250,C262,C263
C1-4
PC520
C3
PC521

Part Number
335152000026
310131103004
335152000020
342665500008
313000020195
313000020190
273000500012
313000020191
273000500016
313000020192
273000500015
313000020180
273000500011
331720015006
331720025005
331720009004
291000151202
291000152604
291000152602
331030060003
331030044006
291000025002
291000015202
291000011001
331040060003
291000012102

Description
CFM-BAT;FUSE,THERMAL,NEC,SF91E
CFM-BAT;NTCR,10K,SEMITEC,103AT-4
CFM-BAT;THERMAL BREAKER,ISUZU,IP
CFM-SUYIN;S-STANDOFF,#4-40H4.8,N
CHOKE COIL;1.3mH(MIN),18.5TS,D.5
CHOKE COIL;1.5UH,20%,7.5T,6*8
CHOKE COIL;10UH,4.7A,5.7MM,SMT
CHOKE COIL;112UH(MIN),7.5T,2*0.6
CHOKE COIL;14UH/13.5T,D.6,55040
CHOKE COIL;15mH(MIN),50.5T,D.6
CHOKE COIL;50UH(REF),D.4*2,5.5T,
CHOKE COIL;6UH ,15%,D0.9,9MM,550
CHOKE COIL;80UH/33T,D.30,55040,L
CON;D,FM,15P,2.29,R/A,3ROW
CON;D,FM,25P,2.775,R/A
CON;D,MA,9P,2.775,R/A
CON;FPC/FFC,12P,0.5MM,R/A,UPPER,
CON;FPC/FFC,26P,1MM,R/A,ELCO,SMT
CON;FPC/FFC,26P,1MM,R/A,SMT,ELCO
CON;HDR,FM,20P*3,.8MM,ST,DIP
CON;HDR,FM,22P*2,2.0MM,ST,SUYIN,
CON;HDR,FM,25P*2,1.27MM,R/A,SMT
CON;HDR,FM,26P*2,1.0MM,ST,SMT,HR
CON;HDR,MA,10P*1,1.25,ST,SMT
CON;HDR,MA,20P*3,.8MM,R/A,AMP
CON;HDR,MA,21P,DUAL ROW,1.25,ST,

Location

T2
L1
PT2
T3
PL502
T1
PT1
PL514
PL1
J505
J506
J507
J501
J5
J2
J1
J3
J514
J1
J1
J515
J2

-100-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(3)
Part Number
291000015012
291000025003
291000025203
291000020202
291000026004
331030006006
291000020402
291000251441
331870004005
331870006011
331810006010
331810006009
331810006014
331910003003
331910002003
331510080001
331840005007
291000410301
346667700004
342665700016
340666500008
340666530004
340666500003
340665700030
441667910031
344665700065

Description
CON;HDR,MA,25P*2,.8MM,ST,SMT,KX1
CON;HDR,MA,25P*2,1.27MM,R/A,SMT
CON;HDR,MA,26P*2,.5MM,R/A,W/NUT,
CON;HDR,MA,2P*1,1.25,R/A,SMT,HIR
CON;HDR,MA,30P*2,.6MM,R/A,SMT,(2
CON;HDR,MA,6P*1,2.0,ST,GLD
CON;HDR,SHROUD,MA,4P*1,2.0,R/A,U
CON;IC CARD,FM,72P*2,.6MM,H3MM,S
CON;MINI DIN,4P,R/A,W/GROUNDING,
CON;MINI DIN,6P,R/A,W/GROUNDING
CON;MODULAR JACK,FM,6P4C,R/A,GR
CON;MODULAR JACK,FM,6P4C,R/A,SW
CON;MODULAR JACK,FM,6P4C,R/A,UK
CON;POWER JACK,3P,16VDC/3A
CON;PWR PLUG,2P,250V/2.5A,SUPERC
CON;RBN,MA,80P,.63MM,R/A
CON;STEREO JACK,5P,R/A,W9.1,LGY2
CON;WFR,MA,3P,1.25,ST,SMT/MB
CONDUCTIVE SHEET;S-CONN,7020
CONTACTOR;HDD,6020
COVER ASSY;2ND,6120
COVER ASSY;COL-2,14.1",LCD,6120L
COVER ASSY;CPU,6120
COVER ASSY;LENS,ID2,COL2,6020
COVER ASSY;M/B,6120N,ID2
COVER;AC ADAPTER,6020

Location
J501
J1
J513
J3,4
J510
J2
J504
U504
J509
J503

PJ501
J1
J508
J501,502
J511

Part Number
344665730004
344665700005
344665700004
344665700041
272625101401
272625470401
272615562501
291006214411
291006214410
288100032013
288100032013
288100032013
288100701002
288100099001
288100056003
328100026005
288100202001
288101004024
328101610002
328100406001
288104148001
288100020002
288100027001
288100020001
288100024002
288100024002

Description
COVER;HINGE,2ND,6020
COVER;MODEM,6020,PRT
COVER;PCMCIA,6020,PRT
COVER;PHONE JACK,6020
CP;100P*4,8P,50V ,10%,1206,NPO,S
CP;47P*4 ,8P,50V ,10%,1206,NPO,S
CP;5600P*4,8P,50V ,20%,0612,X7R,
DIMM SOCKET;144P,.8MM,AMP353870,
DIMM SOCKET;144P,REVERSE,AMP,SMT
DIODE;BAS32L,VRRM75V,MELF,SOD-80
DIODE;BAS32L,VRRM75V,MELF,SOD-80
DIODE;BAS32L,VRRM75V,MELF,SOD-80
DIODE;BAV70LT1,70V,225MW,SOT-23
DIODE;BAV99,70V,450MA,SOT-23
DIODE;BAW56,70V,215MA,SOT-23
DIODE;BYV26E,FAST,1A,1000V,AX,SO
DIODE;DAN202K,80V,SWITCH,SMT
DIODE;EC10QS04,RECT,40V,1A,CHIP,
DIODE;F16P10QS,16A,FAST RECOVERY
DIODE;PBL406,4A,800V,SIP,4P
DIODE;RLS4148,200MA,500MW,MELF,S
DIODE;RLZ2.0B,ZENER,2.02-2.2,5%,
DIODE;RLZ2.7B,ZENER,2.6-2.91,5%,
DIODE;RLZ20C,ZENER,19.23V,5%,SMT
DIODE;RLZ24D,ZENER,23.63V,5%,SMT
DIODE;RLZ24D,ZENER,23.63V,5%,SMT

Location

CA1,CA505,CA506
CA2,CA3,CA501,CA502
CA4,CA5
J4
J3
PD3,PD6,PD8
PD2,502,503,507
D3,9
D11,D27,D30
D10
D14,D2
D8
PD501
PD1,504
D1
D10
D1,12,13,15,16,28,29
PD5
PD2
PD508
PD1
PD1

-101-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(4)
Part Number
288100073002
288100073002
288100016003
328114003001
312271006350
312271006350
272602107501
312271006359
312271206951
312272206152
312272206152
312272206154
312272205051
312273306154
312274706354
227666500007
227665700001
227665700007
227666500006
481667900001
523411442008
523466570001
273000610004
273000150013
273000150013
273000130010

Description
DIODE;SFPJ-73,DC2010,30V,3A,SMT
DIODE;SFPJ-73,DC2010,30V,3A,SMT
DIODE;TZMC16,ZENER,16V,5%,SMT
DIODE;UF4003G,200V/1A,PRE./DO-41
EC;100U ,25V,20%,RA,6.3*7,-40~10
EC;100U ,25V,20%,RA,6.3*7,-40~10
EC;100U,16V,M,6.3*5.5,-55+85'C,S
EC;100U,25V,M,D6.3,RA,-40~105',L
EC;120U ,400V,20%,RA,D35,-25'~10
EC;220U ,4V ,M,RA,D8*5,OS-CON
EC;220U ,4V ,M,RA,D8*5,OS-CON
EC;220U ,6.3V,20%,RA,D10*5,OS-CO
EC;22U,20V,M,RA,D6.3,-55+105,OSEC;330U ,4V ,+-20%,100*5,SP.OSEC;470U ,25V ,20%,RA,D10,-20'~10
END CAP;MIDDLE,AK,6120
END CAP;N/B,6020
END CAP;TOP/BTM,AC ADAPTER,6020
END CAP;TOP/BTM,AK,6120
F/W ASSY;SYS&KBC BIOS,13"/14",61
FD DRIVE;1.44M,3 MODE,D353G
FDD/HDD COMBO ASSY;6020
FERRITE ARRAY;120OHM/100MHZ,M TY
FERRITE CHIP;120OHM/100MHZ,2012,
FERRITE CHIP;120OHM/100MHZ,2012,
FERRITE CHIP;130OHM/100MHZ,1608,

Location
PD10,PD503,PD9
PD505,506,509
D4
D5
PC518,519,523
PC8,9,14
C12,C21,C25,C310
C13
C53
PC515,516
PC12
PC11
PC13
PC513,517
C7,11,19

U36

FA1,FA2,FA3,FA4,FA5
L10,L11,L13,L16,L2
PL2,501-506,511
L506,L507,L508,L509

Part Number
273000130013
273000130013
273000130006
313000150019
313000150020
346600000025
288003600001
295000010008
295000010105
335152000031
295000010016
295000010020
345665700010
345666500001
345665700019
345665700012
344600000296
344600000296
340666500002
342665700040
342665700041
340667000006
340666530002
451666540051
451600001001
344665700066

Description
FERRITE CHIP;30OHM/100MHZ,1608
FERRITE CHIP;30OHM/100MHZ,1608
FERRITE CHIP;600OHM/100MHZ,.2A,1
FERRITE CORE;25OHM/100MHZ,D3
FERRITE CORE;25OM100MZ,CORE ONLY
FILM;300MM*500M,PE
FIR;HSDL3600#007,FRONT VIEW,10P,
FUSE;1.1A,POLY SWITCH,1812,SMT
FUSE;1A,NORMAL,1206,SMT
FUSE;LAG,4A ,HIBREAK,5*20MM
FUSE;NORMAL,6.5A/32VDC,3216,SMT
FUSE;NORMAL,7A/24VDC,1206,SMT
GASKET;AUDIO,6020
GASKET;IO BRACKET,6120
GASKET;PCMCIA,6020
GASKET;USB,6020
GRAIN;PPO.94V-1,BLACK,PRC
GRAIN;PPO.94V-1,BLACK,PRC
HEATSINK ASSY;CPU,6120
HEATSINK;L,AC ADAPTER,6020
HEATSINK;R,AC ADAPTER,6020
HOUSING ASSY;6020+
HOUSING ASSY;COL-2,ID2,LCD,6120L
HOUSING KIT;6120L,ID2
HOUSING KIT;AC 60B
HOUSING;AC ADAPTER,6020

Location
PL6,PL7
L1-3,PL507-509
L28,L3,L501,L502
L2

U501
F2,F3,F4
F5
F1
PF1
PF501

HS1
HS2

-102-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(5)
Part Number
344665700069
344600000235
331650037002
284500003007
282574014004
282574108002
284501021002
286203311001
286300431016
284504280001
284504297001
283466712001
284182371005
284582443010
286317812001
286100358012
286100393004
286302951015
286300809002
284501284002
284587570001
284597338001
284501225001
286303032001
286303052001
286300431011

Description
HOUSING-1;HDD,6020
IC CARD CON PART;72P*2,6020
IC SOCKET;370P,ZIF,ZIFPGA370
IC;3D RAGE LT PRO,AGP,BGA,328P,J
IC;74AHC14,HEX INVERTER,TSSOP,14
IC;74AHC1G08,SINGLE AND GATE,SOT
IC;ADM1021,TEMPERATURE MTR,SSOP1
IC;ADM3311E,RS-232,TSSOP,28P
IC;AME431ACFT,1%,ADJ REG,SOT89
IC;CS4280-CQ,PCI AUDIO,TQFP,128P
IC;CS4297,AUDIO CODEC,TQFP,48P
IC;FLASH,512K*8-90,PLCC,32P,6133
IC;FW82371EB,PIIX4E,PCI/ISA,BGA3
IC;FW82443BX,HOST BRIDG,BGA492,6
IC;HA178L12UA,VOLT REGULATOR,SCIC;LM358,DUAL OP/AMP,SO 8P
IC;LMV393,DUAL COMPARTOR,SSOP,8P
IC;LP2951ACM,VOLTAGE REGULATOR,S
IC;MAX809S,RESET CIRCUIT,2.9V,SO
IC;PACS1284-02Q/T,TERMIN NET,QSO
IC;PC87570,KBD & PWR CTLR,TQFP,1
IC;PC97338VJG,SUPER I/O,TQFP,100
IC;PCI1225PDV,PCI/CARDBUS,LQFP,2
IC;SB3032P,PWM CTLR,SO,16P
IC;SB3052P,PWM CTRL,SSOP,28P
IC;SC431CSK-.5,.5%,ADJ REG,SOT23

Location

U503
U18
U10
U7
U19
U2
Q4
U11
U9
U24
U16
PU1
U3
PU503,PU504
U32
U27
U1
U34
U29
U25
PU1,PU2
PU501
PQ12,PQ4

Part Number
283866700001
286300594001
286100202001
286302206001
286303843002
286500137001
284104011001
273000051001
346665700033
346665700034
346665700012
346665400009
346665700026
340665700001
451667900003
242600000380
242662300009
242600000378
242665700016
242666500002
242600000088
242690500078
242690500078
242600000003
242600000169
242600000364

Description
IC;SGRAM,1M*32-100,PQFP,100P,602
IC;TL594C,PWM CONTROL,SO,16P
IC;TPA0202,AUDIO AMP,2W,TSSOP,24
IC;TPS2206,CARDBUS PWR CTLR,SSOP
IC;UC3843BD,PWM CTLR,SO,8P,SMT
IC;W137,CLOCK GENERATOR,SSOP,28P
IC;W40S11-02,SDRAM BUFFER,SSOP,2
INDUCTOR;22UH ,110mA,3225,SMT
INSULATOR;A/D,23MM,MAD-60B,6020
INSULATOR;A/D,65MM,MAD-60B,6020
INSULATOR;FDD BACK,6020
INSULATOR;I/O PANEL,VENUS
INSULATOR;MODEM,6020
IO DOOR ASSY;6020,ASM
LABEL KIT;LOGO,MAXDATA,6120N
LABEL;10*8MM,BIOS,HI-TEMP 260
LABEL;25*10MM,3020F
LABEL;27*7MM,HI-TEMP 260'C
LABEL;AGENCY,ADPT-19,6020
LABEL;AGENCY-GLOBAL BCIQ,6120
LABEL;BAR CODE,125*65,COMMON
LABEL;BAR CODE,32*16MM,MD4
LABEL;BAR CODE,32*16MM,MD4
LABEL;BAR CODE,NEW,COMMON
LABEL;BLANK,23.8*5MM,COMMON
LABEL;BLANK,6*6MM,HI-TEMP

Location
U14,U20
PU502
U3
U33
U2
U22
U21
L12

-103-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(6)
Part Number
242600000364
242600000099
242600000001
242600000195
242665600006
242665600007
242665700013
441666540004
451666540033
413000020138
334212000010
294011200017
334112000129
416260001001
561566570012
561566650018
561566650015
561566570036
451665700071
339115000008
242666500055
416266791901
416266791001
526266791023
375102030010
328001103001

Description
LABEL;BLANK,6*6MM,HI-TEMP
LABEL;MODEL,5M,MITAC
LABEL;PAL,20*5MM,COMMON
LABEL;SOFTWARE,INSYDE BIOS-M
LABEL;WINDOWS 98,CARTON,5036
LABEL;WINDOWS 98,LCD COVER,5036
LABEL;Y2K,6020
LCD ASSY;TFT,HYUN,14.1",6120L,ID
LCD ME KIT;TFT,HYUN,14.1",6120L,
LCD;HT14X11,TFT14.1,XGA,HYUNDAI
LED HOLDER;ROUND,NYLON,LED-18.5
LED;GREEN,H0.8,0603,CL-190,SMT
LED;ROUND,D3.2,H4.6MM,P2.54,HI,G
MAIN UNIT;AC 60B-19V
MANUAL KIT;EU,6020,NON-BRAND
MANUAL;REF,FR/IT/SP,6020/6120,NMANUAL;USER'S,EN,6120/6020NON-BR
MANUAL;USER'S,GR,6020/6120NON-BR
ME KIT;HDD,6020
MICROPHONE;D9.7*H6.7,WM-034BY
NAMEPLATE;MAXDATA,6120
NB PLATFORM OPTION;14.1",6120N,I
NB PLATFORM;TFT,HT14X11,6120N,ID
NBX;6120N/T4XX/XXA/3XX9/N3DNBA M
NUT-HEX;M2,2,NIW
OPTOCOUPLE;TCET1103,60mA,4P

Location

D4-9
D2

MIC1

U1

Part Number
461600001001
461667030003
221665750002
412665700003
412219300019
316665700007
316665700013
316665700014
316666530002
316667900001
316666600002
222664720001
222600020049
222665520003
222665720002
222665720003
340667000005
335512000003
411665700009
411666530005
411666530004
411667900001
411667900003
411667900002
411600000112
411600000113

Description
PACKING KIT;AC-60B
PACKING KIT;N-B,6020+ CTO
PARTITION;AC ADAPTER,25 IN 1,602
PCB ASSY;FAX MODEM,CTR-21,WIN,60
PCB ASSY;INVERTER BD,14.1",6020
PCB;PWA-6020/CDROM TRANS BD
PCB;PWA-6020/MAD-60B BD
PCB;PWA-6020/MAD-60BI BD
PCB;PWA-6120L/CHARGER BD
PCB;PWA-6120W/M BD
PCB;PWA-TITAN,HDD/FDD BD
PE BAG;310*450,T.08,RECY.,5026VO
PE BAG;50*70MM,W/SEAL,COMMON
PE BAG;80*200MM,5033
PE BAG;LCD ASSY,14",6020
PE BAG;W130*L250,6020
PLATE ASSY;TP 2nd,6020+
POLYSWITCH;3.8A,LR4-380
PWA;PWA-6020 CD-ROM TRANSLATION
PWA;PWA-6120L,CHARGER BD,SMT
PWA;PWA-6120L,CHARGER BD,T/U
PWA;PWA-6120N,MOTHER BD
PWA;PWA-6120N,V0 MOTHER BD,SMT
PWA;PWA-6120N,V0 MOTHER BD,T/U
PWA;PWA-PWR-60B-19,A/D BD,SMT
PWA;PWA-PWR-60B-19,A/D BD,T/U

Location

R0B
R01
R01
R00
R02
R02

-104-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(7)
Part Number
411666600001
411666600005
332810000034
271086057101
271045107101
311100157301
271045207101
271045207101
271002000301
271002000301
271071000002
271071000002
271012000301
271013010301
271013119301
311121101337
271071121111
271071100302
271002101301
271071101101
271071104101
271071104302
271012104301
271071102311
271002103301
271071103101

Description
PWA;PWA-TITAN,HDD/FDD BD,SMT
PWA;PWA-TITAN,HDD/FDD BD,T/U
PWR CORD;250V/2.5A,2P,BLK,EU,175
RES;.005 ,2W ,1% ,7520,SMT
RES;.01 ,1W ,1% ,2512,SMT
RES;.015 ,MnCu,1/4W,5%,10.2*5.0,
RES;.02 ,1W ,1% ,2512,SMT
RES;.02 ,1W ,1% ,2512,SMT
RES;0 ,1/10W,5% ,0805,SMT
RES;0 ,1/10W,5% ,0805,SMT
RES;0 ,1/16W,0603,SMT
RES;0 ,1/16W,0603,SMT
RES;0 ,1/8W,5% ,1206,SMT
RES;1 ,1/4W,5% ,1206,SMT
RES;1.1 ,1/4W,5% ,1206,SMT
RES;1.1K ,CF,1/4W,5% ,AX
RES;1.21K,1/16W,1% ,0603,SMT
RES;10 ,1/16W,5% ,0603,SMT
RES;100 ,1/10W,5% ,0805,SMT
RES;100 ,1/16W,1% ,0603,SMT
RES;100K ,1/16W,1% ,0603,SMT
RES;100K ,1/16W,5% ,0603,SMT
RES;100K ,1/8W,5% ,1206,SMT
RES;102K ,1/16W,1% ,0603,SMT
RES;10K ,1/10W,5% ,0805,SMT
RES;10K ,1/16W,1% ,0603,SMT

Location

PR11
PR521,514
JP1
PR13
PR505
L14,L15,L17,L18,L513
R6
PR15,R106,R122,R129
R2,5,PR503,PR5
R3,4,8,11,14
R43,R44
R41,R42,R18
R24
PR513
R105,R234,R235,R52
R13
R112,R136,R55,R56
PR10,12,508,512,
PR17,506,511,R193,
R27,28,33,35
PR6
R23,32
PR5,PR8

Part Number
271071103101
271071103302
271012103301
271071111101
271071118311
271071124301
271071124311
271071137211
271071134101
271002147211
271072151101
271071153301
271071180301
271071184301
271002102301
271071102102
271071102102
271071102302
271071105101
271071105101
271071105301
271002221111
271071222302
271071225301
271071272301
271071204302

Description
RES;10K ,1/16W,1% ,0603,SMT
RES;10K ,1/16W,5% ,0603,SMT
RES;10K ,1/8W,5% ,1206,SMT
RES;110 ,1/16W,1% ,0603,SMT
RES;118K ,1/16W,1% ,0603,SMT
RES;120K ,1/16W,5% ,0603,SMT
RES;124K ,1/16W,1% ,0603,SMT
RES;13.7K,1/16W,1% ,0603,SMT
RES;130K ,1/16W,1% ,0603,SMT
RES;14.7K,1/10W,1% ,0805,SMT
RES;150 ,1/10W,1% ,0603,SMT
RES;15K ,1/16W,5% ,0603,SMT
RES;18 ,1/16W,5% ,0603,SMT
RES;180K ,1/16W,5% ,0603,SMT
RES;1K ,1/10W,5% ,0805,SMT
RES;1K ,1/16W,1% ,0603,SMT
RES;1K ,1/16W,1% ,0603,SMT
RES;1K ,1/16W,5% ,0603,SMT
RES;1M ,1/16W,1% ,0603,SMT
RES;1M ,1/16W,1% ,0603,SMT
RES;1M ,1/16W,5% ,0603,SMT
RES;2.21K,1/10W,1% ,0805,SMT
RES;2.2K ,1/16W,5% ,0603,SMT
RES;2.2M,1/16W,5% ,0603,SMT
RES;2.7K ,1/16W,5% ,0603,SMT
RES;200K ,1/16W,5% ,0603,SMT

Location
PR4,501,502,509
PR16,R101,R118,R144
R19
R282,562
PR9
R260
PR513
PR13
PR509
R16
R111,R13,R284,R285
R152,R155,R182,R225
R103,R110,R162,R163
R24
R15
R51
PR3,507
PR4,PR507,R1,R114
PR20,PR22,PR24,PR514
PR6,7,9
R100,R126,R140,R25
R22,12
PR518
PR23,PR510
R61,R71,R87,R166
R290

-105-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(8)
Part Number
271071203101
271071203101
271071206301
271002220301
271071221302
271071221211
271012224301
271071226311
271071237311
271071243311
271071249311
271071270301
271071271301
271002274311
271071301211
271071301311
271071324211
271071324012
271071330302
271071331301
271012331301
271071333301
271071392211
271071305301
271012432301
271013478301

Description
RES;20K ,1/16W,1% ,0603,SMT
RES;20K ,1/16W,1% ,0603,SMT
RES;20M ,1/16W,5% ,0603,SMT
RES;22 ,1/10W,5% ,0805,SMT
RES;22 ,1/16W,5% ,0603,SMT
RES;22.1K,1/16W,1% ,0603,SMT
RES;220K ,1/8W,5% ,1206,SMT
RES;226K ,1/16W,1% ,0603,SMT
RES;237K ,1/16W,1% ,0603,SMT
RES;243K ,1/16W,1% ,0603,SMT
RES;249K ,1/16W,1% ,0603,SMT
RES;27 ,1/16W,5% ,0603,SMT
RES;270 ,1/16W,5% ,0603,SMT
RES;274K ,1/10W,1% ,0805,SMT
RES;30.1K,1/16W,1% ,0603,SMT
RES;301K ,1/16W,1% ,0603,SMT
RES;32.4K,1/16W,1% ,0603,SMT
RES;324K ,1/16W,1% ,0603,SMT
RES;33 ,1/16W,5% ,0603,SMT
RES;330 ,1/16W,5% ,0603,SMT
RES;330 ,1/8W,5% ,1206,SMT
RES;33K ,1/16W,5% ,0603,SMT
RES;39.2K,1% ,1/16W,0603,SMT
RES;3M ,1/16W,5% ,0603,SMT
RES;4.3K ,1/8W,5% ,1206,SMT
RES;4.7 ,1/4W,5% ,1206,SMT

Location
PR18,PR512
PR520
R293
R39
R294,R295,R296
PR15
R37,38
PR26
PR7
PR516
PR2
R156,R168,R175,R176
R10,R11,R12
R31
PR14
PR11
PR508
PR19
R120,R121,R123,R124
R119,220,167,
R5
R514,R519
PR27
PR8
R7
R501,R502

Part Number
271002472301
271002472301
271071472302
271071472302
271071499111
271071442011
271071470301
271071471302
271071474301
271012474301
271071473101
271071473301
271071473301
271071487311
271071562301
271071510301
271012510301
271071514301
271071560301
271071564301
271013564301
271071593101
271071622301
271071682101
271002698111
271071681301

Description
RES;4.7K ,1/10W,5% ,0805,SMT
RES;4.7K ,1/10W,5% ,0805,SMT
RES;4.7K ,1/16W,5% ,0603,SMT
RES;4.7K ,1/16W,5% ,0603,SMT
RES;4.99K,1/16W,1% ,0603,SMT
RES;442 ,1/16W,1% ,0603,SMT
RES;47 ,1/16W,5% ,0603,SMT
RES;470 ,1/16W,5% ,0603,SMT
RES;470K ,1/16W,5% ,0603,SMT
RES;470K ,1/8W,5% ,1206,SMT
RES;47K ,1/16W,1% ,0603,SMT
RES;47K ,1/16W,5% ,0603,SMT
RES;47K ,1/16W,5% ,0603,SMT
RES;487K ,1/16W,1% ,0603,SMT
RES;5.6K ,1/16W,5% ,0603,SMT
RES;51 ,1/16W,5% ,0603,SMT
RES;51 ,1/8W,5% ,1206,SMT
RES;510K ,1/16W,5% ,0603,SMT
RES;56 ,1/16W,5% ,0603,SMT
RES;560K ,1/16W,5% ,0603,SMT
RES;560K ,1/4W ,5% ,1206,SMT
RES;59K ,1/16W,1% ,0603,SMT
RES;6.2K ,1/16W,5% ,0603,SMT
RES;6.8K ,1/16W,1% ,0603,SMT
RES;6.98K,1/8W ,1% ,0805,SMT
RES;680 ,1/16W,5% ,0603,SMT

Location
PR1
R26
R18,
PR510
PR505
R59,R60
R128,R134,R185,R189
PR3,R139,R205
R154,R218,R219,R531
R1,2
PR501,PR504
PR21,R227,R228,R248
R1,PR511,519
PR14
R143,R158,R169
R69
R9,10
PR503,PR515
R84,85
R242,R243
R29
PR12
PR506
R29,R32,R45
R30
R113,R147,R8,R9

-106-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(9)
Part Number
271013683301
271002683301
271071750101
271002822301
271071806211
271071976311
561566570042
271611000301
271571000301
271571100301
271611104301
271611103301
271621103303
271611151301
271611102301
271611222301
271611220301
271611330301
271571330301
271611472301
271621472303
271621433301
271621473301
271621560301
271611750301
271621822301

Description
RES;680K ,1/4W ,5% ,1206,SMT
RES;68K ,1/8W,5% ,0805,SMT
RES;75 ,1/16W,1% ,0603,SMT
RES;8.2K ,1/10W,5% ,0805,SMT
RES;80.6K,1/16W,1% ,0603,SMT
RES;976K ,1/16W,1% ,0603,SMT
REVISED PAGE;EN,6020,NO.1
RP;0*4 ,8P ,1/16W,5% ,0612,SMT
RP;0*8 ,16P ,1/16W,5% ,1606,SM
RP;10*8 ,16P ,1/16W,5% ,1606,SM
RP;100K*4,8P ,1/16W,5% ,0612,SMT
RP;10K*4 ,8P ,1/16W,5% ,0612,SMT
RP;10K*8 ,10P,1/16W,5% ,1206,SMT
RP;150*4 ,8P ,1/16W,5% ,0612,SMT
RP;1K*4 ,8P ,1/16W,5% ,0612,SMT
RP;2.2K*4,8P ,1/16W,5% ,0612,SMT
RP;22*4 ,8P ,1/16W,5% ,0612,SMT
RP;33*4 ,8P ,1/16W,5% ,0612,SMT
RP;33*8 ,16P ,1/16W,5% ,1606,SM
RP;4.7K*4,8P ,1/16W,5% ,0612,SMT
RP;4.7K*8,10P,1/16W,5% ,1206,SMT
RP;43K*8 ,10P,1/16W,5% ,1206,SMT
RP;47K*8 ,10P,1/16W,5% ,1206,SMT
RP;56*8 ,10P,1/16W,5% ,1206,SMT
RP;75*4 ,8P ,1/16W,5% ,0612,SMT
RP;8.2K*8,10P,1/16W,5% ,1206,SMT

Location
R25
R21
R14,R76
R20
PR25
PR16
RP87,RP9,RP97
RP11,14,47-49
RP15,RP16,RP17,RP18
RP41,RP81
RP38,RP56,RP67
RP52,RP53,RP55,RP57
RP25
RP59
RP8
RP92
RP44
RP23,RP26,RP35,RP60
RP28,RP7
RP54,RP58,RP68,RP73
RP80,RP82,RP83,RP84
RP90
RP1-3,10,13,19,21
RP22,RP501
RP40,RP43,RP45,RP72

Part Number
345667000002
345666600011
565166650001
371102610405
371102030303
371102010601
340666500001
340665700040
346666500003
346666530004
346666500002
333050000014
561866570001
561860000022
561860000028
361200003025
361200003025
346667120001
342665700015
370102610602
370102610602
370102611601
370102610401
370102610801
370102011501
370102010201

Description
Location
RUBBER;LCD,DOWN,6020+
RUBBER;PCB,FDD/HDD,TITAN
S/W;CD ROM,SYSTEM DRIVER,6120/60
SCREW;M2.6L4,K-HEAD(+),NIW
SCREW;M2L3,K-HEAD(+),NIW/NLK
SCREW;M2L6,FLT(+),NIW
SHIELDING ASSY;BOTTOM,6120
SHIELDING ASSY-1;HDD,6020
SHIELDING;CD ROM,6120
SHIELDING;ESD,VR,6120L
SHIELDING;PCMCIA,6120
SHRINK TUBE;600V,125',D1.5*20MM,
SINGLE PAGE;DOC/EC,6020
SINGLE PAGE;GN,NOTE FOR BATTERY&
SINGLE PAGE;PWR-60B-19A
SOLDER PASTE;RMA-010-FP
SOLDER PASTE;RMA-010-FP
SPACER;FC-PGA CPU,6133XN
SPC-SCREW;M2*L4.9,NIB,K-HD,6020
SPC-SCREW;M2.6 L6,NIB,K-HD,727
SPC-SCREW;M2.6 L6,NIB,K-HD,727
SPC-SCREW;M2.6*L16,NIB,K-HD
SPC-SCREW;M2.6L4,NIB,727,NLK
SPC-SCREW;M2.6L8,NIB,K-HD,NYLOCK
SPC-SCREW;M2L15,NIW,FLT(+),NL,73
SPC-SCREW;M2L2,NIW,K-HD,727

-107-

6120N N/B MAINTENANCE


9. SPARE PARTS LIST(10)
Part Number
370102020301
370102020301
370102020301
370103010405
370103010505
370103010604
340665700008
340665700007
346665700018
297120101005
297030105001
297040101003
225600000013
225600000012
340665700003
340665700002
442164900003
288227002001
288227002001
328222645001
288200144002
288200144002
288200144001
288200144001
288206612001
288206690001

Description
SPC-SCREW;M2L3,NIW,K-HEAD
SPC-SCREW;M2L3,NIW,K-HEAD
SPC-SCREW;M2L3,NIW,K-HEAD
SPC-SCREW;M3L4,NIW,K-HD,T0.3
SPC-SCREW;M3L5,FLNG/PAN(+),HD7,N
SPC-SCREW;M3L6,NIB,727,NYLOK
SPEAKER BOX ASSY;L,6020,ASM
SPEAKER BOX ASSY;R,6020,ASM
SUPPORTER;CD-ROM CONN,6020
SW;DIP,SPST,8P,50VDC,.1A,SMT,DHS
SW;PUSH BUTTON,SPSD,48V/.05A,SMT
SW;PUSH BUTTON,SPST,.1A,30V,2P,S
TAPE;60MM*50M,PP
TAPE;60MM*900M,PP
TILT UNIT;L,6020,PRT
TILT UNIT;R,6020,PRT
TOUCH PAD MODULE;TM41PDM220-2
TRANS;2N7002LT1,N-CHANNEL FET
TRANS;2N7002LT1,N-CHANNEL FET
TRANS;2SK2645-01MR,9A,600V,TO-22
TRANS;DTA144WK,PNP,SMT
TRANS;DTA144WK,PNP,SMT
TRANS;DTC144WK,NPN,SOT-23,SMT
TRANS;DTC144WK,NPN,SOT-23,SMT
TRANS;FDS6612A,N-MOSFET,.03OHM,S
TRANS;FDS6690A,N-MOSFET,.017OHM,

Location

SW2
SW1
SW1,2

PQ13,Q11,14,37,40,41
PQ501,507
Q5
PQ506
Q1
PQ10,PQ5,PQ502,PQ6
Q2
PQ502,503
PQ504,505

Part Number
288202222001
288203904010
288203906018
288204401001
288207002001
288207002001
288200352001
288202301001
288202302001
288204416001
288204435001
288204832001
288204603001
271911103902
346667000009
421666530001
421666500006
313001050040
313001050056
274011431408
274012457405
274012949401
274013276103

Description
TRANS;MMBT2222AL,NPN,TO236AB
TRANS;MMBT3904L,NPN,Tr35NS,TO236
TRANS;MMBT3906L,PNP,Tr35NS,TO236
TRANS;MMBT4401,NPN,SOT-23,3P
TRANS;NDC7002N,N-MOSFET,SSOT-6
TRANS;NDC7002N,N-MOSFET,SSOT-6
TRANS;NDS352P,DMOS,TO-236AB
TRANS;SI2301DS,P-MOSFET,SOT-23
TRANS;SI2302DS,N-MOSFET,SOT-23
TRANS;Si4416DY,N-MOSFET,.028OHM,
TRANS;SI4435DY,P-MOSFET,.035OHM,
TRANS;SI4832DY,N-MOSFET,.028OHM,
TRANS;SPB46N03L,30V46A,N-CH,TO26
VR;10K ,20%,.05W,XV0102GPH1N-93
WASHER;PLATE,TOUCHPAD,6020+
WIRE ASSY;HY14.1,LCD,6120L
WIRE ASSY;INVERTER,LCD,6120
XSFORMER;18U/17.5T/36.5T/.8D/.35
XSFORMER;PQ2620,LP=650uH,38/5/7
XTAL;14.318M,50PPM,32PF,7*5,4P,S
XTAL;24.576M,50PPM,16PF,7*5,4P,S
XTAL;29.498928MHZ,30PPM,20PF,4P,
XTAL;32.768KHZ,20PPM,12.5PF,CM20

Location
PQ509
PQ501,Q10,44,7,9
Q35
Q3
PQ7,PQ8
PQ1,2
Q20,Q502
Q30
PQ2,Q12,Q16,Q18,Q3
PU3,PU5
PQ508,510
PU4
PQ11
VR1

PT1
T14
X500
X1
X2
X5,X6

-108-

6120N N/B MAINTENANCE


10. SYSTEM BLOCK DIAGRAM & SCHEMATICS
X2
14.318MHZ

66/100MHZ
CPUCLK

W137
W137
CLOCK
CLOCK
Synthesizer
Synthesizer

14.318MHZ

U503
Celeron
PPGA 370
CPU

66/100MHZ
SDRAMCLK

33MHZ
PCI CLK

144PIN 3.3V
Expansion

48MHZ

W40S11
W40S11
SDRAM
Clock
SDRAM
Buffer Clock
Buffer

4MB
Video SGRAM

AGP VGA
Controller

AGP BUS

Intel
Intel
82443ZX
82443ZX

MTR

ATI_RAGE_LT
PRO

North
North
Bridge
Bridge

SO-DIMM Socket

X9
29.499MHZ

LCD

66MHZ

PCI BUS
CRYSTAL
CRYSTAL
CS4280
PCI

ZV BUS

33MHZ

FAX/
MODEM

CS4280
PCI
Audio
Drive
Audio Drive

AUDIO
CONNECTOR

Intel
Intel
PIIX4E
PIIX4E
South
Bridge
South Bridge

CDROM

X1
24.576MHZ

USB
PORT

CRYSTAL
CRYSTAL
CODEC
CODEC
CS4297
CS4297

33MHZ

X4
32.768KHZ

HDD

33MHZ
14.318MHZ
48MHZ USB CLK

PCCARD
PCCARD
Controller
Controller

TI

TI
PCI 1225
PCI 1225
PCCARD
Socket

8MHZ
ISA CLK

ISA BUS
X5
16MHZ

PC87570
K/B PC87570
Controller
K/B Controller

PS/2 KB

Printer
Port

NS
NS
PC97338
PC97338
Super I/O CTRL_
Super I/O CTRL_

PS/2
Mouse
24MHZ/48MHZ

Battery
Battery

Touch pad
Touch pad
ICON LED

ADM3311
ADM3311
RS232
RS232
Driver
Driver
COM
COM
PORT
PORT

FDD
FIR

System
System
BIOS
FlashBIOS
ROM
Flash ROM
VDD5
VDD5S
VMAIN
+3V
+5V
+12V

D/D Module

-109-

6120N N/B MAINTENANCE


13. SYSTEM BLOCK DIAGRAM & SCHEMATICS

MOTHER-BOATD
DC /DC

BOARD

-110-

6120 Mother BD
Page
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.

Description

Comments

Title
CPU Celeron Socket 370
North Bridge 443BX
SO-DIMM
On Board SDRAM
Synthesizer
PIIX4
IDE & FDD conn
VGA ATi Rage LTpro
VGA connector
SGRAM
Pccard controller TI1225
Pccard Socket
PCI Audio CS4280
AC97 CODEC CS4297
Audio Amp. TPA0202
Super I/O & RS232
H8 MC/KC
USB & Backlite conn & Port Replicator
Pull-up & BIOS
Power Peripheral
Modem & Battery Charger D/D conn

REV.

Description of Change

R00

Initial Design

Comments
Difference from 6020
1. CPU change to CELERON(PPGA Socket370)
2. Use BX chipset in Desktop mode
3. Add Core/Bus Ratio frequency select circuits
4. Add thermal translation
5. Connect SLP#(from CPU) to PIIX4 for sleep mode
( Mobile use quick start mode)
Power management
1. w/ AC---> POS(Ring wake up support)
PIIX4
SUSA#
active
H8
STR#, SUSBNS#
always high
2. w/o AC---> STR(No Ring wake up support)
System command to H8
H8
STR#
active
System prepare STR procedure(frame buffer content,
cardbus content,...), and after at least 500us
PIIX4
SUSA#,SUSB#
active
H8
SUSBNS#
active

R0A

DVT

Change from R00 to R0A


1. Only POS implemented, delete STR function
2. Connect GPO1 to CS4280 as PCIRST#
3. Fix LCDVCC supply circuit
4. Change SGRAM from 4MB to 8MB (total)
5. Change LCD connector from one(20pins) to
two parts(21pins & 30 pins)
6. Add EMI required parts

MTG8

MTG9

MTG3

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

MTG118_N_RD30X12

MTG118_N_RD30X12

MTG118_N_RD30X12

MTG6

MTG7

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

MTG118_N_RD30X12

EMI TEST
EMI TEST
EMI TEST
EMI TEST
EMI TEST-------PVT

Didn't tape out


Didn't tape out

R01

Change from R0F (8-layer)

Exchange R0A's power and GND plane.


Added 2 layer GND plane to R0A.
1. Move via away from port replicator
2. Move Q18 and L25 away from drill hole
3. D28 reverse
4. R177 change from 10K to 4.7K
5. On component side, the solder mask of CPU socket pin
cover 50% of pad ring to get better soldering
6. The damping of SGRAM data bus change to DFS
7. Add LDO regulator to supply +5V to modem (to reduse
modem noise)

6120L

modified from 6120R01

R00

factory request

Modify
1. CPU socket solder side solder mask cover 50% ring pad
2. modify PIO connector (bigger fix hole)
3. modify port replicator connector (pin shift right)
4. modify board edge( add one connectioon and cut HDD connector part)

costdown

1. change diode BAT54 to RLS4148(D3,13,21)


2. BX->ZX(add RP85,86,R244,245)
3. SMBUS data switch change fron U17 to
Q40,41,42,R239,240,241
4. remove SDRAM
U5~8,R26,27,C36,37,26~29,82~85
5. R166 10K->2.7K,R167 33->330
6. C115~118 10U->1U
7. remove U36,C307~309,RP85
8. C16,310 10U->100U
9. add R242,243,F3,F4
10. add SAMSUNG SGRAM

MTG118_N_RD30X12

GND
GND

GND

FD2
FD_DOT040

MTG5
ID5.5/OD8.5
MTG217NRD335_30X12

6120W

FD4
FD_DOT040

FD3
FD_DOT040

FD503
FD_DOT040

FD502
FD_DOT040

FD501
FD_DOT040

12
11
10

FD504
FD_DOT040

modified from 6120LR00

R00

3
2
1
4
5
6

FD1
FD_DOT040

GND

GND

R0B
R0C
R0D
R0E
R0F

Modify
1. Support PIII FC-PGA CPU
2. Change H8/F3434 to NS 87570
3. Add track point

I=5.5mm

7
8
9

O=8.5mm

GND

DRAWN

DESIGN CHECK

ISSUES
MITAC INTERNATIONAL CORP.
Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

1
8

of

24

VTT

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

C75
1U
0805
16V

A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3

CELERON PPGA 370-PIN SOCKET

A20M#
VCC_CMOS
FLUSH#
IGNNE#
CPUPRES#
PREQ#

Processor Pin Definition Comparison


=========================================
Pin
Celeron
Cm-128
Cm-256
----------------------------------------A29
RSV
RSV
DEP7#
A31
RSV
RSV
DEP3#
A33
RSV
RSV
DEP2#
AA33
RSV
RSV
VTT
AA35
RSV
RSV
VTT
AC1
RSV
RSV
A33#
AC37
RSV
RSV
RSP#
AF4
RSV
RSV
A35#
AG1
EDGCTRL
EDGCTRL
EDGCTRL
/VRSEL
/VRSEL
AH20
RSV
RSV
VTT
AH4
RSV
RSV
RESET#
AJ31
GND
BSEL1
BSEL1
AK16
RSV
RSV
VTT
AK24
RSV
RSV
AERR#
AL11
RSV
RSV
AP0#
AL13
REV
REV
VTT
AL21
REV
RSV
VTT
AM2
GND
RSV
RSV
AN11
RSV
RSV
VTT
AN13
RSV
RSV
AP1#
AN15
RSV
RSV
VTT
AN21
RSV
RSV
VTT
AN23
RSV
RSV
RP#
B36
REV
REV
BINIT#
C29
RSV
RSV
DEP5#
C31
RSV
RSV
DEP1#
C33
RSV
RSV
DEP0#
E23
RSV
RSV
VTT
E29
RSV
RSV
DEP6#
E31
RSV
RSV
DEP4#
G35
RSV
RSV
VTT
S33
RSV
RSV
VTT
S37
RSV
RSV
VTT
U35
RSV
RSV
VTT
V4
RSV
RSV
BERR#
W3
RSV
RSV
A34#
X4
RESET#
RESET#
RESET2#
X6
RSV
RSV
A32#
Y33
GND
RSV
CLKREF

BCLK
LOCK#

IN-TARGET PROBE SIGNAL


========================
PRDY#
GTL+ OUTPUT
PREQ#
CMOS INPUT
TCK
TAP INPUT
TDI
TAP INPUT
TMS
TAP INPUT
TRST#
TAP INPUT
TDO
TAP OUTPUT

STPCLK#
DEFER#
RESET#
THERMTRIP#
THERMDP
THERMDN
EDGCTRL
PWRGOOD
FERR#

BREAKPOINT SIGNAL
===================
BP[3:2]#
GTL+ I/O
BPM[1:0]# GTL+ I/O

TMS
TCK
TDI
TDO

COMPARISON OF VCC_CMOS PULL HIGH

RSVRD SLEWCTRL RSVRD


RSV50

==================================
SOCKET_370
MOBILE
---------------------------------IERR#
N.C.
4.7K
FERR#
220
4.7K
FLUSH#
500
4.7K
PREQ#
330
4.7K
STPCLK#
410
680
INIT#
330
1K
NMI
330
4.7K
INTR
330
4.7K
IGNNE#
330
4.7K
A20M#
330
4.7K
SMI#
410
4.7K
THERMTRIP#
220
NO
PWRGOOD
330
NO
SLP#
330
10K

**

FSB FREQ SELECT PIN


========================
BSEL1
BSEL0
FREQ
0
0
66MHz
0
1
100MHz
1
0
RESERVED
1
1
133MHz

RSV49
RSV48
RSV47
RSV46
RSV45
RSV44
RSV43
RSV42
RSV41
RSV40
RSV39
RSV38
RSV37
RSV36
RSV35
RSV34
RSV33
RSV32
RSV31
RSV30
RSV29
RSV28
RS27V
RSV26
RSV25
RSV24
RSV23
RSV22
RSV21
RSV20
RSV19
RSV18
RSV17
RSV16
RSV15
RSV14
RSV13
RSV12
RSV11
RSV10
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0

RSV38 RTTCTRL

SLP# IS NOT CONNECTED TO PIIX4E & PULL HIGH


10K OHM FOR QUICK START STATE (ON MOBILE MODULE)

TAP PULL HIGH OR LOW (NO USE)


===============================

TDI
TCK
TMS
TRST#

SOCKET_370
MOBILE
150(UP)
1K(DOWN)
150(UP)
1K(DOWN)
150(UP)
1K(DOWN)
680(DOWN) 1K(DOWN)

HITM#
HIT#

AD36
Z36
AE33
AB36
AE37
AG37
C37

C_INIT#

0 2 0603B_DFS
0 2
0603B_DFS
C_A20M#
C_A20M#
R54 1
0 2
0603B_DFS
FLUSH#
C_IGNNE#
C_IGNNE#

J37

PREQ#

W37
AK20

HCLKPII
HLOCK#

AG35

STPCLK#

AN19
X4

DEFER#
CPURST#

PREQ#

AN31
AH30
AN17
AJ33
AJ35
AH14
AN33

ADS#
SLP#
BPRI#
BSEL0
SMI#
BNR#
TRST#

AK32
AL33

TMS
TCK

AN35
AN37

TDI
TDO

E27
W35
AA33
AA35
AC37
N35
N37
N33
Q33
L33
Q35
Q37
S33
S35
S37
U35
U37
G37
A33
A31
A29
AL21
B36
G35
C33
C31
C29
E31
E29
E21
E23
F10
AL13
AL11
Y1
AK24
X6
X2
R2
V4
W3
AK30
AC1
AK16
AN11
AF4
AH20
AH4
AN15
AN13
AN21
AN23

R282
R51
R562

VID[1..4]

3,20

HA#3
HA#13
HA#16
HA#5

1
2
3
4
5

VCC_CORE
PWRGDCPU
20,21

HA#23
HA#19
HA#25
HA#21

1
2
3
4
5

HA#30
HA#27
HA#18
HA#24

1
2
3
4
5

HD#1
HD#4
HD#15
HD#6

1
2
3
4
5

HD#9
HD#14
HD#18
HD#12

1
2
3
4
5

HD#24
HD#7
HD#30
HD#13

1
2
3
4
5

110X8
10
9 HA#8
8 HA#11
7 HA#6
6 HA#9

RP24

20
20

ADS#
SLP#
BPRI#

3
6
3

SMI#
6
BNR#
3
TRST#
20
TMS
TCK

110X8
10
9 HA#12
8 HA#15
7 HA#28
6 HA#10

2 110 0603
2 1K 0603
2 110 0603

1
1
1

RP21

VCC_CMOS
1%
1%
1%

+2.5V_CPUIO

GND

110X8
10
9 HD#5
8 HD#8
7 HD#17
6 HD#10

RP10
R61
2.7K
0603

VCC_CMOS

110X8
10
9 HA#29
8 HA#26
7CPURST#
6 HD#0

RP13
TESTHI#

110X8
10
9 HA#22
8 HA#17
7 HA#31
6 HA#20

RP19

20
20

TDI 20
TDO 20

R227
47K
0603
B

110X8
10
9 HD#2
8 HD#3
7 HD#11
6 HD#20

PX4_FERR#
R64
0_NA
0603

C
Q9
MMBT3904L
E

6
HD#25
HD#35
HD#33
HD#26

RP6

110X8

1
2
3
4
5

10
9 HD#19
8 HD#16
7 HD#21
6 HD#23

VTT
RP5
FERR#
R71
2.7K
0603

HD#22
HD#38
HD#43
HD#34

1
2
3
4
5

HD#49
HD#51
HD#42
HD#45

1
2
3
4
5

HD#63
HD#59
HD#48
HD#52

1
2
3
4
5

3,5,6

HD#60
HD#50
HD#58
HD#53

1
2
3
4
5

FRQ_SEL

R228
47K
0603
CQ10
MMBT3904L
E

R82
0_NA
0603

2 CPURST#

110X8
10
9 HD#37
8 HD#36
7 HD#39
6 HD#44

RP3
9 BSEL100

110X8
10
9 HD#29
8 HD#31
7 HD#28
6 HD#32

RP4
VCC_CMOS

R283
ONLY FOR Cm-256
0
0603

110X8
10
9 HD#27
8 HD#41
7 HD#47
6 HD#40

RP2

110X8
10
9
8
7
6

HD#57
HD#55
HD#46
HD#54

110X8

BSEL0

Route GTL from BX to CPU


then to these terminations

R87
2.7K
0603

R285
150
0603

23

RESERVED FOR 1.5V VCC_CMOS

RP25

C334
4.7U
1206
10%

1
2
3
4
5

10
9
8
7
6
4.7K*8

PREQ#
SLP#
C_INIT#

8 STPCLK#
7 FLUSH#
SMI#
6
5

1
2
3
4

MITAC INTERNATIONAL CORP.


150*4
1206

1206

Title
6120W/N - MOTHER BD

VID2
VID3
VID4

PWRGDCPU

GND
3

10
9 HREQ#2
8 BPRI#
7 HREQ#4
6 HREQ#1
RP32

6
3

110X8

1
2
3
4
5

1
1
VID[1..4]

VID1

110X8
10
9 RS#0
8 HIT#
7 HITM#
6 RS#1

RP31
HA#4
HA#14
BNR#
HA#7

5
3

THERMDP
THERMDN
51

10
9 HD#62
8 HD#56
7 HD#61
6 PRDY#

VCC_CMOS

C_NMI
C_INTR
C_IGNNE#
C_A20M#

4.7K*4
1206

C108
0.1U
20
0603
50V

DEFER#
CPURST#

R69 1
PWRGDCPU
FERR#

1
2
3
4
5
RP30

STPCLK#

AG1
AK26
AC35

VCC_CMOS
VCC_CMOS

RP29
CLKREF

HREQ#[0..4]

3 HREQ#[0..4]

0603

GND
R284
150
0603

8
7
6
5

GND

110
RP1

HREQ#0 1
DEFER# 2
HREQ#3 3
HLOCK# 4
5

20
GND

+2.5V_CPUIO
+3V
RP28

0603

+2.5V_CPUIO

VCC_CMOS
20

HCLKPII
HLOCK#

AH28
AL31
AL29

CLKREF

1
2

1
2

1
2

1
2

C134
0.1U
0603
50V

C60
0.1U
0603
50V

RS#2
DRDY#
DBSY#
HTRDY#

HITM#
3
VTT
HIT#
3

R58 1
R53 1

0_NA
0603
C57
0.1U
0603
50V

2
110
R84

ADS#
SLP#
BPRI#
BSEL#
SMI#
BNR#
TRST#

GTL+ PIN NO PULL HIGH


IN DEMO SCHEMATICS
=======================
BP[3:2]#
BPM[1:0]#
BPRI#
GTL+ INPUT

C_INIT#

AL23
AL25

HITM#
HIT#

AG33
AE35

VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57
VCC56
VCC55
VCC54
VCC53
VCC52
VCC51
VCC50
VCC49
VCC48
VCC47
VCC46
VCC45
VCC44
VCC43
VCC42
VCC41
VCC40
VCC39
VCC38
VCC37
VCC36
VCC35
VC34C
VCC33
VCC32
VCC31
VCC30
VCC29
VCC28
VCC27
VCC26
VCC25
VCC24
VCC23
VCC22
VCC21
VCC20
VCC19
VCC18
VCC17
VCC16
VCC15
VCC14
VCC13
VCC12
VCC11
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCC0

BPM#1
BPM#0

BP#3
BP#2

BR#0

RS#2
RS#1
RS#0

INIT#
IERR#

R272

C135
0.1U
0603
50V

BREQ#0 1

U503

2
1

C79
1U
0805
16V

R85

VCC_1.5
VCC_2.5

1
2
3
4

C101
1U
0805
16V

D63
D62
D61
D60
D59
D58
D57
D56
D55
D54
D53
D52
D51
D50
D49
D48
D47
D46
D45
D44
D43
D42
D41
D40
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

C109
1U
0805
16V

DBSY#
DRDY#

PLL2
PLL1

TRDY#
PRDY#

R14
75
0603
1%

R13
150
0603

C133
1U
0805
16V

C132
1U
0805
16V

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

C131
1U
0805
16V

AM4
AK34
AF34
AD32
AB34
Z32
AA37
X34
Y35
P34
V32
T34
R32
R36
M32
K34
H36
K32
H32
V36
B34
B30
B26
B22
B18
B14
B6
B10
F22
F26
F30
F34
E9
E5
E17
E13
D6
D20
D24
D28
D32
D36
C3
F14
K2
N5
J5
F4
F2
W5
S5
T2
P2
AH24
AF2
AE5
AB2
AA5
AH36
AH32
AJ29
AJ25
AJ21
AJ17
AJ13
AJ9
AJ5
AK2
AM32
AM28
AM24
AM20
AM16
AM12
AM8

E35
C35

E37
G33

AN29

AK28
AH22
AH26

U33
W33

L35
J35

C130
1U
0805
16V

AD4
AA3
Z4
AK6
AA1
Y3
AF6
AB4
AB6
AE3
AJ1
AC3
AG3
Z6
AE1
AN7
AL5
AK14
AL7
AN5
AK10
AH6
AL9
AH10
AL15
AN9
AH8
AH12
AK8

C129
1U
0805
16V

3 HA#[3..31]

HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3

C128
1U
0805
16V

HA#[3..31]

C119
1U
0805
16V

GND

C120
1U
0805
16V

C153
10U_NA
1210
10V
1210_1812

C77
1U
0805
16V

C24
10U_NA
1210
10V
1210_1812

C74
1U
0805
16V

C9
0.1U
0603
50V

C55
1U
0805
16V

C50
0.1U
0603
50V

C54
1U
0805
16V

C6
0.1U
0603
50V

C56
1U
0805
16V

C8
0.1U
0603
50V

C58
1U
0805
16V

C161
0.1U
0603
50V

F16
E25
A27
A25
C17
C23
A19
C27
C19
C21
A23
D16
A13
C25
C13
A17
A15
A21
C11
A11
A7
D12
D14
C15
D10
D8
A9
C9
B2
C7
C1
F6
C5
J3
A3
A5
F12
E1
E3
K6
G3
F8
G1
L3
H6
P4
R4
H4
U3
N3
L1
Q1
M4
Q3
P6
S1
J1
T6
S3
U1
M6
N1
T4
W1

C59
1U
0805
16V

1
1
C4
0.1U
0603
50V

C10
0.1U
0603
50V

C150
0.1U
0603
50V

C7
0.1U
0603
50V

C162
0.1U
0603
50V

C158
0.1U
0603
50V

1
2
C

C86
0.1U
0603
50V

C72
0.1U
0603
50V

C107
0.1U
0603
50V

RESERVED FOR TERMINATION DECOUPLING

HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#24
HD#23
HD#22
HD#21
HD#20
HD#19
HD#18
HD#17
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#10
HD#9
HD#8
HD#7
HD#6
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0

C125
4.7U
1206
16V

R34
VSS79
X36
VSS78
P32
VSS77
AD34
VSS76
X32
VSS75
AB32
VSS74
AC33
VSS73
Z34
VSS72
Y37
VSS71
Y33
VSS70
M34
VSS69
P36
VSS68
H34
VSS67
K36
VSS66
V34
VSS65
T32
VSS64
T36
VSS63
A37
VSS62
B28
VSS61
B32
VSS60
B20
VSS59
B24
VSS58
B4
VSS57
B8
VSS56
B12
VSS55
AF32
VSS54
B16
VSS53
F20
VSS52
F28
VSS51
F24
VSS50
E7
VSS49
F36
VSS48
F32
VSS47
E11
VSS46
E19
VSS45
E15
VSS44
D2
VSS43
D4
VSS42
AF36
VSS41
D18
VSS40
D22
VSS39
D26
VSS38
D30
VSS37
D34
VSS36
G5
VSS35
L5
VSS34
H2
VSS33
M2
VSS32
Q5
VSS31
U5
VSS30
V2
VSS29
AG5
VSS28
Y5
VSS27
AD2
VSS26
AC5
VSS25
Z2
VSS24
AH34
VSS23
AH2
VSS22
AJ31
VSS21
AJ27
VSS20
AJ23
VSS19
AJ19
VSS18
AJ3
VSS17
AJ15
VSS16
AJ11
VSS15
AJ7
VSS14
AK36
VSS13
AK4
VSS12
AL3
VSS11
AL1
VSS10
AM34
VSS9
AM30
VSS8
AM26
VSS7
AM22
VSS6
AM18
VSS5
AM14
VSS4
AM10
VSS3
AM6
VSS2
AM2
VSS1
AN3
VSS0

VTT

AL27
AN27

C64
4.7U
1206
16V

ADS#

AJ37
VID3
AL37
VID2
AM36
VID1
AL35
VID0

HD#[0..63]

3 HD#[0..63]

AN25
A35

DBSY#
DRDY#

C126
4.7U
1206
16V

VCC_CORE

AL17
REQ#4
AL19
REQ#3
AH18
REQ#2
AH16
REQ#1
AK18
REQ#0

3 DBSY#
3 DRDY#

C92
4.7U
1206
16V

MENDOCINO
PICD1
PICD0

3 HTRDY#
20 PRDY#

HTRDY#
PRDY#

L37
M36

J33

PICD1

0603

PICCLK

150

C127
4.7U
1206
16V

GND

5 PICCLK

LINT1/NMI
LINT0/INTR

150 0603
R33
1
2

AK22
VREF7
AK12
VREF6
AD6
VREF5
V6
VREF4
R6
VREF3
K4
VREF2
F18
VREF1
E33
VREF0

PICD0

C62
4.7U
1206
16V

PLL1
PLL2

PICD0
PICD1

R30
1

C63
4.7U
1206
16V

VTT

C_NMI

VCC_CMOS

C71
4.7U
1206
16V

C_INTR

C_NMI

C105
4.7U
1206
16V

C_INTR

20

C65
4.7U
1206
16V

20

C356
10U
1206
16V PLL2

RS#0
RS#1
RS#2

1
2

C98
22U
1812
10V
20%

22UH 10%
3225

RS#[0..2]

3 RS#[0..2]

PLL1

BREQ#0

3 BREQ#0

L12
1

VCC_CORE

VCC_CORE

20,21

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

2
8

of

24

C198
1000P
0603
+80-20%

GND

HA#[3..31]

2 HA#[3..31]

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

2
2
2
2
2
2
2
2
2
2
2

BREQ#0
ADS#
BPRI#
BNR#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#
HREQ#[0..4]

RS#[0..2]

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2

B26
K21
H26
H24
L23
J26
K23
L24
L22
K22
H25
J22
J23
K24
K25
J25
K26
L26
L25
B23

BREQ0#
ADS#
BPRI#
BNR#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
RS0#
RS1#
RS2#
CPURST#

2,20 CPURST#

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MB0
MB1
MB2
MB3
MB4
MB5
MB6
MB7
MB8
MB9
MB10
MB11
MB12
MB13

R42 1
10K

MB12

Q35
MMBT3906L
R208
B
1
2
10K
0603

P16
R12
R15
T11
T13

VCC3V
VCC3W
VCC3X
VCC3Y
VCC3Z

+3V

FW82443ZX

R86

11,19
13,19
19,21
19

E7
D7
E10
E8
E9
A6
C7
F10
D8
D10
AE3
D6
B6

P_GNT0#
P_GNT1#
P_GNT2#
P_GNT3#

0603 6,11,19 P_REQ0#


6,13,19 P_REQ1#
6,19,21 P_REQ2#
R78
19 P_REQ3#
1
2
JT27
1
10K 0603
6,19 PHLDA#
6,19 PHOLD#
G_SBA[0..7]
8,19 G_PIPE#

10K_NA

8,19 G_SBA[0..7]

G_SBA0
G_SBA1
G_SBA2
G_SBA3
G_SBA4
G_SBA5
G_SBA6
G_SBA7

R105
1

2
10

DCLKO 5

0603

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13

RP14 1 0*8_NA
2
3
4
5
6
7
8
RP11 1 0*8_NA
2
3
4
5
6
7
8

16 RPX8MAB#0
MAB#1
15
MAB#2
14
MAB#3
13
MAB#4
12
MAB#5
11
MAB#6
10
MAB#7
9
16 RPX8MAB#8
MAB#9
15
MAB10
14
MAB#11
13
MAB#12
12
MAB13
11
10
9
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

MB10

16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9

MAB#0
MAB#1
MAB#2
MAB#3
MAB#4
MAB#5
MAB#6
MAB#7
MAB#8
MAB#9
MAB10
MAB#11
MAB#12
MAB13

8,19 G_FRAME#
8,19 G_DEVSEL#
8,19 G_IRDY#
8,19 G_TRDY#
8,19 G_STOP#
8,19 G_PAR
8,19 G_REQ#
8,19 G_GNT#

RP85
0*8 RPX8
RP_16P8R_4016

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

RP86
0*8 RPX8
RP_16P8R_4016

RP_16P8R_4016

MAB#[0..9]
MAB10 4
MAB#11 4
MAB#12 4
MAB13 4

MAB#[0..9] 4

RP_16P8R_4016

4
4
4
4
4
4
4
4

+3V
R74 1
10K_NA
R77 1
10K_NA
R47 1
10K_NA
R34 1
10K_NA

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8

8 G_C/BE#[0..3]

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

G_C/BE#[0..3]

STRAP0(MAB#6): INTERNAL PULL LOW


H:MOBILE GTL+ L:DESKTOP GTL+

AB5
AE2
AD3
AD2
AD1
AC3
AC1
AB4
AB1
AA5
AA3
AA4
AA2
AA1
Y5
Y3
W1
V2
W2
U5
V1
U4
U3
U1
T3
T4
T2
T1
U6
R3
R4
R2
AB2
Y4
V4
U2
N5
P5

R103
18
0603

STRAP1(MAB#7): INTERNAL PULL LOW


H:AS 430TX L:NORMAL

2
0603
2
0603
2
0603
2
0603

M3
K1
M2
M1
N2
P2
P4
P3
R1
W3
W5
V5
W4
Y1
Y2
L5
L3

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#(NC)
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#(TM2)
WSC#(NC)
PHLDA#
PHOLD#
PIPE#
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC/BE0#
GC/BE1#
GC/BE2#
GC/BE3#
GCLKIN
GCLKO

2
0603

STRAP2(MAB#9): INTERNAL PULL LOW


H:AGP DISABLE L:AGP ENABLE

8 CLKAGP

TESTIN#
V3S_BX

HCLKBX 5
PCLKBX 5

D13

+5V
2

R114

+3V

1K
0603

A
RLS4148

C195
2

0.1U
50V
0603

GND

VTT

R76
75
0603
1%
1
C90

C148

0.1U
50V
0603

0.1U
50V
0603

R46
150
0603

C151

C89
0.1U_NA
50V
0603

0.1U
50V
0603

GND

GND

RP27
MECC_2 1
MECC_3 2
MECC_6 3
MECC_7 4
MECC_5 5
MECC_4 6
MECC_0 7
MECC_1 8
1

MECC_7
MECC_6
MECC_5
MECC_4
MECC_3
MECC_2
MECC_1
MECC_0
CKE00

CKE1 4
CKE2 4
CKE3 4

10*8_NA

RPX8
16
15
14
13
12
11
10
9

2
10
0603

1
SCASA# 4

MECC[0..7]

MECC[0..7] 4

MECC2
MECC3
MECC6
MECC7
MECC5
MECC4
MECC0
MECC1

CKE0 4

R52

JT530
JT529

SRASA# 4

JT528

WEA# 4
CSA#3
CSA#2
CSA#1
CSA#0

4
4
4
4

FW82443ZX

MITAC INTERNATIONAL CORP.


Title

STRAP4(MAB#11): INTERNAL PULL HIGH


H:IN-ORDER QUEUE DEPTH MAX L:NO PIPELINE

6120W/N - MOTHER BD

GND
2

TOUCHPAD_9

VTT

STRAP5(MAB#12): INTERNAL PULL LOW


DRIVED BY CPU H:100MHZ L:66MHZ
R38 1
2
10K_NA 0603

As short as possible

SUS_STAT1# 6
1
JT3
TOUCHPAD_9

R110
18
0603

STRAP3(MAB10): INTERNAL PULL LOW


H:QUICK START MODE L:STOP CLOCK MODE

2
0603
MB11

BXPWROK 20
CRESET# 20
JT1
CLKRUN# 6,11,19,21
1

R102 1
0_NA

6,11,13,19,21 DEVSEL#
6,11,13,19,21 FRAME#
6,11,13,19,21 IRDY#
6,11,13,19,21 TRDY#
6,11,13,19,21 STOP#
6,11,13,21 PAR
6,8,11,12,13,21 PCIRST#
6,11,13,19,21 SERR#
19 PCILOCK#
6,11,13,21 C/BE0#
6,11,13,21 C/BE1#
6,11,13,21 C/BE2#
6,11,13,21 C/BE3#

AF3
AD4
AE23
M26
AC4
M25
N23
B2
C2
M23
E16
M24
F17
C18
AF26
AF13
AF1
AD22
AD18
AD9
AD5
AB25
AB24
AB15
AB12
AB3
AA21
AA19
AA8
AA6
W21
W6
V24
V3
T15
T12
R22
R16
R14
R13
R11
R5
P26
P15
P14
P13
P12
N24
N15
N14
N13
N12
N1
M22
M16
M14
M13
M11
M5
L15
L12
J24
J3
H21
H6
F21
F19
F8
F6
E24
E15
E12
E3
C22
C9
C5
A26
A14
A1
Y22
AA25
AD12
AF11
AA26
AA23
AA10
AE11
AC22
AF23
AE24
AD23
AC23
AF24
AB13
AF12
AA17
AF16
AB23
AC26
AC24
AD26
AD24
AE25
AC12
AE12
AE16
AD15
AC15
AE15
AF15
AB14

F20
G6
G21
F7
F9
F18
M12
J6
J21
L11
L13
L14
M15
N11
N16
N22
N26
P1
V6
B1
P11

PWROK
SUSTAT1#(NC)
RESVB
CRESET#
CLKRUN#
TESTIN#
HCLKIN
PCLKIN
REFVCC5
GTLREFA
GTLREFB
VTT0
VTT1
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
MECC7(NC)
MECC6(NC)
MECC5(NC)
MECC4(NC)
MECC3(NC)
MECC2(NC)
MECC1(NC)
MECC0(NC)
CKE0
CKE1
CKE2
CKE3
CKE4(NC)
CKE5(NC)
SCAS1#(NC)
SCAS0#
SRAS1#(NC)
SRAS0#
RCSB5#(NC)
RCSB4#(NC)
RCSB3#
RCSB2#
RCSB1#
RCSB0#
WEB#(NC)
WEA#
RCSA5#(NC)
RCSA4#(NC)
RCSA3#
RCSA2#
RCSA1#
RCSA0#

VCC3A
VCC3B
VCC3C
VCC3D
VCC3E
VCC3F
VCC3G
VCC3H
VCC3I
VCC3J
VCC3K
VCC3L
VCC3M
VCC3N
VCC3O
VCC3P
VCC3Q
VCC3R
VCC3S
VCC3T
VCC3U

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
SERR#
PLOCK#
C/BE0#
C/BE1#
C/BE2#
C/BE3#

VCC3AA
VCC3AB
VCC3AC
VCC3AD
VCC3AE
VCC3AF
VCC3AI
VCC3AJ
VCC3AK
VCC3AL
VCC3AM
VCC3AN
VCC3AO
VCC3AP

K6
K2
K4
K3
K5
J1
J2
H2
H1
J5
H3
H5
H4
G1
G2
G4
D1
D3
D2
C1
A2
C3
B3
D4
E5
A4
D5
B4
B5
A5
E6
C6
F3
E2
E1
F5
F4
G5
A3
F1
F2
J4
G3
E4
C4

U16C
T14
T16
L16
AA18
AA20
AE1
AE26
AF2
AF14
V21
Y6
Y21
AA7
AA9

MB9
CPURST# 2,20

GND

+3V

MB7

R112
100
0603
1%

C196
1000P
0603
+80-20%

GND

MB6
2,5,6 FRQ_SEL

R111
150
0603

MDR[0..63] 4

FW82443ZX

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

MDR[0..63]
MDR0
MDR1
MDR2
MDR3
MDR4
MDR5
MDR6
MDR7
MDR8
MDR9
MDR10
MDR11
MDR12
MDR13
MDR14
MDR15
MDR16
MDR17
MDR18
MDR19
MDR20
MDR21
MDR22
MDR23
MDR24
MDR25
MDR26
MDR27
MDR28
MDR29
MDR30
MDR31
MDR32
MDR33
MDR34
MDR35
MDR36
MDR37
MDR38
MDR39
MDR40
MDR41
MDR42
MDR43
MDR44
MDR45
MDR46
MDR47
MDR48
MDR49
MDR50
MDR51
MDR52
MDR53
MDR54
MDR55
MDR56
MDR57
MDR58
MDR59
MDR60
MDR61
MDR62
MDR63

U16B

AD[0..31]

6,11,13,21 AD[0..31]

G_ST0 8
G_ST1 8
G_ST2 8
G_RBF# 8,19
G_ADSTBA 8,19
G_ADSTBB 8,19
G_SBSTB 8,19
DCLKWR/RD 5

L4
L2
L1
M4
AC2
T5
N3
AB22
N4
AD25
AF4
AE4
AF5
AD6
AE6
AB7
AC7
AF7
AB8
AB9
AC9
AE9
AB10
AC10
AF10
AD11
Y24
Y25
W23
W24
W26
W25
V26
U24
U23
T22
T23
T26
R24
R25
P23
N25
AC5
AE5
AB6
AC6
AF6
AD7
AE7
AC8
AD8
AF8
AE8
AF9
AD10
AE10
AB11
AC11
Y23
Y26
W22
V22
V23
V25
U22
U25
U26
T24
T25
U21
R23
R26
P24
P25
AB21
AF17
AB16
AE17
AC17
AF18
AE19
AF19
AC18
AC19
AE20
AD20
AF21
AC21
AF25
AD16
AC16
AD17
AB17
AE18
AD19
AB18
AB19
AF20
AC20
AB20
AE21
AD21
AF22
AD13
AC13
AC25
AB26
AE14
AC14
AA22
AA24
AE13
AD14
P22

ST0
ST1
ST2
RBF#
ADSTBA
ADSTBB
SBSTB
DCLKRD
AGPREFV
DCLKWR
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DCLKO
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAB0(NC)
MAB1(NC)
MAB2(NC)
MAB3(NC)
MAB4(NC)
MAB5(NC)
MAB6(STRAP0)
MAB7(STRAP1)
MAB8(NC)
MAB9(STRAP2)
MAB10(STRAP3)
MAB11(STRAP4)
MAB12(STRAP5)
MAB13(NC)
CDQA0#
CDQA1#
CDQA2#
CDQA3#
CDQA4#
CDQA5#
CDQA6#
CDQA7#
CDQB1#(NC)
CDQB5#(NC)
RESVC

+3V

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
RESVA
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HA30
HA31

B22
D22
E21
A22
D21
C21
A21
C20
B21
E20
A20
E19
B20
E18
D20
D19
D18
C19
B19
A18
A19
B18
C17
E17
D17
B17
C16
A17
C15
B16
D16
A16
B15
A15
D14
D15
B13
C14
E14
D13
A13
D12
B12
B14
C13
E13
D11
A12
B11
A11
B7
C12
C8
B10
A10
A9
A7
E11
D9
C11
C10
B8
A8
B9
AE22
G25
H22
G23
H23
G24
F26
G26
G22
F22
F23
F24
F25
E23
E26
E25
D25
D26
B25
C26
A25
C25
A24
D24
C23
B24
C24
A23
E22
D23

1
C103
1000P
0603
+80-20%
2

1
C87
1000P
0603
+80-20%
2

1
C172
1000P
0603
+80-20%
2

1
2

+3V

2 RS#[0..2]

C197
0.1U
0603
50V

GND

2 HREQ#[0..4]

1
C106
0.1U
0603
50V

1
2

1
2

+3V

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

C88
0.1U
0603
50V

U16A
HD#[0..63]

2 HD#[0..63]

C170
0.1U
0603
50V

ZX
install RP85,86
NA
NA
NA
NA

BX
install RP11,14
install RP27
Avaliable
install R102
install R86

Memory Address
Mecc[0..7]
CKE4,CSA#4
SUSTAT1#
PREQ4#

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

3
8

of

24

+3V

+3V

144 PIN SODIMM SOCKET

J4

MD[0..63]

+3V

MDR31
MDR63
MDR62
MDR30
MDR61
MDR29
MDR28
MDR60
MDR27
MDR58
MDR57
MDR26
MDR25
MDR56
MDR55
MDR23
MDR24
MDR54
MDR59
MDR22
MDR53
MDR52
MDR51
MDR20
MDR21
MDR19
MDR18
MDR50
MDR49
MDR17
MDR16
MDR48
MDR15
MDR47
MDR46
MDR14
MDR45
MDR44
MDR13
MDR12
MDR43
MDR11
MDR10
MDR9
MDR41
MDR42
MDR40
MDR39
MDR8
MDR7
MDR38
MDR37
MDR6
MDR5
MDR36
MDR4
MDR3
MDR35
MDR34
MDR2
MDR33
MDR32
MDR0
MDR1

RP15
10*8
RPX8

RP16
10*8
RPX8

RP17
10*8
RPX8

RP18
10*8
RPX8
B

RP33
10*8
RPX8

RP34
10*8
RPX8

RP36
10*8
RPX8

RP39
10*8
RPX8

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9

MD31
MD63
MD62
MD30
MD61
MD29
MD28
MD60
MD27
MD58
MD57
MD26
MD25
MD56
MD55
MD23
MD24
MD54
MD59
MD22
MD53
MD52
MD51
MD20
MD21
MD19
MD18
MD50
MD49
MD17
MD16
MD48
MD15
MD47
MD46
MD14
MD45
MD44
MD13
MD12
MD43
MD11
MD10
MD9
MD41
MD42
MD40
MD39
MD8
MD7
MD38
MD37
MD6
MD5
MD36
MD4
MD3
MD35
MD34
MD2
MD33
MD32
MD0
MD1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

MD0
MD1
MD2
MD3

MD[0..63]

MD4
MD5
MD6
MD7
DQMA0
DQMA1

3 DQMA0
3 DQMA1

MAB#0
MAB#1
MAB#2

3 MAB#0
3 MAB#1
3 MAB#2

MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MECC0
MECC1

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

5 SDRAMCLK0
SRASA#
WEA#
CSA#0
CSA#1

3 SRASA#
3 WEA#
3 CSA#0
3 CSA#1

MECC2
MECC3
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MAB#6
MAB#8

3 MAB#6
3 MAB#8

MAB#9
MAB10

3 MAB#9
3 MAB10

DQMA2
DQMA3

3 DQMA2
3 DQMA3

MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31

SMBDATA0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

MD32
MD33
MD34
MD35

MAB#0
MAB#1
MAB#2

DQMA4
DQMA5

MD8
MD9
MD10
MD11

DQMA4 3
DQMA5 3

MAB#3
MAB#4
MAB#5

MAB#3 3
MAB#4 3
MAB#5 3

MD12
MD13
MD14
MD15

MD40
MD41
MD42
MD43

MECC0
MECC1

MD44
MD45
MD46
MD47

5 SDRAMCLK2

MECC4
MECC5

SRASA#
WEA#
CSA#2
CSA#3

3 CSA#2
3 CSA#3

CKE0

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

DQMA0
DQMA1

MD36
MD37
MD38
MD39

MECC2
MECC3

CKE0 3

SCASA#
CKE1
MAB#12
MAB13

SCASA# 3
CKE1 3

MD16
MD17
MD18
MD19

SDRAMCLK1 5

MD20
MD21
MD22
MD23

MECC6
MECC7
MD48
MD49
MD50
MD51

MAB#6
MAB#8
MAB#9
MAB10

MD52
MD53
MD54
MD55

DQMA2
DQMA3

MAB#7
MAB#11

MAB#7 3
MAB#11 3

MAB#12
MAB13

MD24
MD25
MD26
MD27

MAB#12 3
MAB13 3

DQMA6
DQMA7

MD28
MD29
MD30
MD31

DQMA6 3
DQMA7 3

MD56
MD57
MD58
MD59

SMBDATA1

MD60
MD61
MD62
MD63

MD32
MD33
MD34
MD35

DQMA4
DQMA5
MAB#3
MAB#4
MAB#5
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MECC4
MECC5
CKE2

GND

CKE2 3

SCASA#
CKE3
MAB#12
MAB13

CKE3 3
SDRAMCLK3 5

MECC6
MECC7
B

MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MAB#7
MAB#11
MAB#12
MAB13
DQMA6
DQMA7
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
SMBCLK 5,6

DIMM144P/0.8MM
DIMM-AMP-C353870

+3V

MD36
MD37
MD38
MD39

GND
C

SMBCLK 5,6
1

MD[0..63]

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

MD4
MD5
MD6
MD7

MDR[0..63]

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

MD0
MD1
MD2
MD3

+3V

J3

3 MDR[0..63]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

R240
100K
0603

DIMM144P/0.8MM/H4
DIMM-AMP-97-25850-001
GND

R241
100K
0603B
SMBDATA0/1

SMBDATA0/1 6

GND

G
SMBDATA1

S
D
S

Q40 2N7002
SMBDATA
MECC[0..7]

SMBDATA 5,6

SMBDATA0

D
S

MECC[0..7] 3

MECC0
MECC1
MECC4
MECC5
MECC2
MECC3
MECC6
MECC7

S
Q41
G 2N7002
+3V

R239

==>

SMBDATA0

==>

SMBDATA1

10K
0603
2

SMBDATA0/1

Q42
DTC144WK

GND

C189
1U
0603B
2

C187
0.1U
0603B
2

C185
0.1U
0603B
2

C183
0.1U
0603B
2

C181
0.1U
0603B

1
C179
0.1U
0603B
2

C177
0.1U
0603B
2

C175
0.1U
0603B
2

C173
1U
0603B

C190
1U
0603B

C188
0.1U
0603B

C186
0.1U
0603B

C184
0.1U
0603B

C182
0.1U
0603B

+3V

C180
0.1U
0603B

C178
0.1U
0603B

C176
0.1U
0603B

1
2

1
2

C174
1U
0603B

+3V

MITAC INTERNATIONAL CORP.


Title
GND

GND

6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

4
8

of

24

+2.5V_CPUIO
L18

(+3VS)
+3V

C260
2.2U
1206

CLOCK SYNTHESIZER AND DRIVER

C248
0.1U
0603B

0 0805C
C259
10U_NA
1206
10V

GND
GND
L17
R162 1

2 18

0603B

R163 1

2 18

0603B

HCLKPII 2
HCLKBX 3
1

C247
0.1U
0603B

C254
10P/NA
0603B

GND

C253
10P/NA
0603B

GND

C219
10P
0603B

W137_SUSA#

17

0_NA
0603

CPU_STOP#
PCI_STOP#

GNDL
GNDPCI
GND48
GND
GNDREF

PD#

D19
RLZ2.4B_NA

GND

GND

GND

C211
10P_NA
0603B

C208
10P_NA
0603B

GND

R164 1

2 33

0603B

14MPIIX4 6

R171
10K
0603B

C255
10P_NA
0603B

R151
10K
0603B

C210
10P_NA
0603B

+3V

C0G

C209
10P_NA
0603B

R165
10K_NA
0603B

W137
SSOP28A
GND

GND

C207
10P_NA
0603B

+3V
C314
10P_NA
0603B

C0G

PICCLK 2

R166
22K
0603B

Don't install R542,R246,247 for ZX


GND

PCLKBX 3
PCLKMODEM 21
PCLKAUDIO 13
PCLKCARD 11

2 220 0603B

22
7
15
21
1

PCLKPIIX4 6

R167 1

27
26

REF0/SEL48#*
REF1/SPREAD#*

0603B
0603B
0603B
0603B

SEL100/66#
48MHZ
*TS#/48/24MHZ

C220
10P
0603B

R247

18
20

33
33
33
33

6 CPU_STP#
6 PCI_STP#

14.318M_TXC7X5

0603
2

0603B

2
2
2
2

1
1
1
1

R542
0_NA
1

2 33

R124
R123
R121
R120

3
2
4

1
1

16
13
14

2,3,6 FRQ_SEL

1M
0603B
X500
1

X1
X2

R125 1

4
5
6
9
10
11

2
3

PCICLK_F
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

VDDREF

23
24

28

GND

R126
2

GND
CPUCLK0
CPUCLK1

VDDPCI
VDD48
VDD

GND

8
12
19

VDDL

25

R161
1K
0603

GND
U22
C224
0.1U
0603B

C221
0.1U
0603B

BEAD_120Z/100M
L16 0603B
2

+2.5V_CPUIO

+3V

C218
0.1U
0603B

C240
0.1U
0603B

C244
10P
0603B

C242
4.7U
1206

0
C3130805C
10P_NA
0603B

GND
2 33

0603B

R149 1

2 33

0603B

USB_48MHZ 6
IO_48MHZ 16

C237
10P_NA
0603B

R142 1

6,8,17,18,20,23,24 SUSA#

C235
10P_NA
0603B

GND

GND

(+3VS)
+3V
L14
2
1

0
0805C

C199
0.1U
0603B

GND

GND

C200
0.1U
0603B

(+3VS)
+3V

U21

L15

C204
10P
0603B

C203
10P
0603B

13
1
5
10
19
24
28

C215
10P
0603B

C229
10P
0603B

C217
0.01U
0603B

C201
0.1U
0603B

C202
0.1U
0603B

2
C

C206
4.7U
1206

0
0805C

C216
0.1U
0603B

GND

9
20
GND
14
15

VDDIIC
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
BUF_IN
OE
SDATA
SCLOCL

2
0603
1

6,8,17,18,20,23,24 SUSA#

R246

4
4
4
4

GND

+3V

R89
4.7K
0603B

R215

R97
4.7K
0603B
2

SDRAMCLK3
SDRAMCLK2
SDRAMCLK1
SDRAMCLK0

DON'T INSTALL R51,53 IF ZX IS USED

(+3VS)
+3V

0_NA
0603

DCLKWR/RD 3

2 0 0603B
2 0 0603B
2 0 0603B
2 0 0603B

W40S11-02
SSOP28A

S11_SUSA#

2 0 0603B

R129 1
R130 1
R131 1
R132 1

10

R106 1

SDR3
SDR4
SDR2
SDR6

SDR1

4
8
12
17
21
25
16

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSSIIC

R235
3 DCLKO

2
3
6
7
22
23
26
27
11
18

SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9

4,6 SMBDATA

10K_NA
0603
2

4,6 SMBCLK

JL508
SUSCLK_32K

32K_CARD 11

D
2

D
S

0_NA
0603

JP_NET
JP_NET15

Q36
2N7002_NA

6 SUSCLK

R222

JL509
32K_PWRMX 12

JP_NET
JP_NET15

GND

R216

JL510
VGA_32K 8

0
0603

JP_NET
JP_NET15
MITAC INTERNATIONAL CORP.
Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

5
8

of

24

(+3VS)
+3V

AD[0..31]

R133

D15
K

2
C239
1U
0603B

RLS4148
MLL34B

GND
SD[0..15]

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

+3VS_USB

17,19 SCI#

T12
Y13
V13
U13
W14
T14
Y15
LA23
LA22
LA21
LA20
LA19
LA18
LA17

W19
Y19
W18
Y18
V17
Y17
T16
W16
V1
T1
Y2
W2
T2
U2
W3
V3
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0

J16
VREF

N16
R16

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC/USB

VCC/SUS0
VCC/SUS1

B1
C1
E1
D1
A2
B2
C2
E2
B3
C3
E3
D3
A4
B4
C4
E4
E6
D6
A7
B7
C7
D7
A8
B8
E8
D8
A9
B9
C9
D9
A10
B10
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

A3
IDSEL

C8
C6
D4
D2
C/BE#0
C/BE#1
C/BE#2
C/BE#3

gpi20
gpi21

9,19 LCD_ID2
11,19 CARD_ACT
JT510
JT523
11,12 CARD_SUS#
1
7 FDD_MODE
19 MODEM_OFF#

==>

0 = SMBDATA0 ; 1 =SMBDATA1

==>

IRMD0
1
0
0
1

IRMD1

FUNTION

0
0
1
1

SHUTDOWN
FULL DISTANCE POWER
2/3 DISTANCE POWER
1/3 DISTANCE POWER

DACK0#
DACK1#
DACK2#
DACK3#
DACK5#
DACK6#
DACK7#
DREQ0
DREQ1
DREQ2
DREQ3
DREQ5
DREQ6
DREQ7
TC
XOE#
XDIR#
BIOSCS#
KBCCS#
MCCS#
PCS0#
PCS1#
USBP1+
USBP1USBP0+
USBP0OC0#
OC1#

7 SDD[0..15]
7 SDCS3#
7 SDCS1#
7 SDA0
7 SDA1
7 SDA2

1
1
gpo27
gpo28
gpo29

PIORDY
PDIOW#
PDIOR#
PDDREQ
PDDACK#
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDCS3#
PDCS1#
PDA0
PDA1
PDA2
G20
F16
F17
F18
G19
F20
E18
E20
D18
D20
C20
B20
A20
A19
B19
C19
D19
D17
E19
E17
F19
H16
H17
G16
G18
G17

SIORDY
SDIOW#
SDIOR#
SDDRQ
SDDACK#
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDCS3#
SDCS1#
SDA0
SDA1
SDA2

RTCALE
RTCCS#
RTCX1
RTCX2

V4
U4
W5
T5
Y6
V6
Y7
V7
U7
W8
T8
Y9
V9
U9
W10
T10
Y11
W11
T11
U11
Y12
V15
U15
W4
U3
T7
U10
Y1
W7
V12
Y3
W12
W1
Y5
T4
T3
Y4

SDD[0..15]

SA[0..19]

JT35
1

SA[0..19] 16,17,19

MEMCS16# 19
MEMR# 17,19
MEMW# 17,19
JT32
1

JT519
1

JT520

gpi0

FRQ_SEL 2,3,5
REFRESH# 19
IOCS16# 19
ZEROWS# 16,19
SBHE# 19
RSTDRV 16
IOR# 16,17,19
IOW# 16,17,19
IOCHRDY 16,17,19
AEN 16,17

U14
W6
Y10
V5
T15
V16
W17
W15
U6
V2
U5
Y16
U16
U17

DACK0# 16
DACK1# 16
DACK2# 16
DACK3# 16

JT522
1
JT526
1
JT527

DREQ0
DREQ1
DREQ2
DREQ3
DREQ5
DREQ6
DREQ7

V10

16,19
16,19
16,19
16,19
19
19
19

TC 16
gpo23
gpo22

M4
M3
M2
K1
N4
L4
N5

JT516
1
JT517
BIOSCS# 17
KBCS# 19
MCCS# 19
PCS0# 19

JT518

F1
H2
G2
H3
J1
J2

USBP1+ 18
USBP1- 18
USBP0+ 18
USBP0- 18
USB_OC0# 18
USB_OC1# 18

VCC_RTC

L16
gpo25
gpo24

L1
K2

RS232_OFF# 16
SPK_OFF 15

N19
R20
X5

PIIX4E
BGA324
FW82371EBSL2MY

PDA2
PDA1
PDA0
PDCS1#
PDCS3#
PDD[0..15]

SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

PDD15
PDD14
PDD13
PDD12
PDD11
PDD10
PDD9
PDD8
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

7 SIORDY
7 SDIOW#
7 SDIOR#
7 SDDREQ
7 SDDACK#

gpi19

18,19 DOCK_IN

SDD15
SDD14
SDD13
SDD12
SDD11
SDD10
SDD9
SDD8
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

GND
gpi16
gpi17
gpi18

19 MID0
19 MID1
19 MID2

JT511

MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
MAIN
MAIN
MAIN
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN

gpi1
gpi13
gpi14
gpi15

9,19 LCD_ID0
9,19 LCD_ID1
19 GPI15

X
X
VGA_SUS#
CD_RSTDRV#
CD_PWR#
HDD_PWR#
HDD_RSTDRV#
FDD_PWR#
X
X
GNTB#
SMBDATA0/1
IRMD0
IRMD1
H8_12V
SUSB#
SUSC#
CPU_STP#
PCI_STP#
X
SUS_STAT1#
SUS_STAT2#
X
X
SPK_OFF
RS232_OFF#
KBCS#
CARD_SUS#
ATI_STDBY#
FDD_MODE
MODEM_OFF#

VCC(RTC)

NC0
NC1
NC2
NC3
NC4
NC5

gpo9
1
gpo10
gpo11

SMBALERT#
RI#

GPOUT
FUNCTION
PWR
=============================
GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
GPO8
GPO9
GPO10
GPO11
GPO12
GPO13
GPO14
GPO15
GPO16
GPO17
GPO18
GPO19
GPO20
GPO21
GPO22
GPO23
GPO24
GPO25
GPO26
GPO27
GPO28
GPO29
GPO30

D16
B16
C16
A16
A17
E15
B15
D14
C14
A14
C13
A13
C12
D12
B13
D13
B14
E14
A15
C15
D15
C18
B18
C17
B17
A18

PWROK
SPKR
TEST#
CONFIG1
CONFIG2
APICACK#
APICCS#
APICREQ#
REQA#
REQB#
REQC#
GNTA#
GNTB#
GNTC#

BATLOW#

P19
L2
J3
L5
K3
K4
H1
H4
H5
G3

JT29
JT31
4 SMBDATA0/1

BATLOW#
CPU_STP#
EXTSMI#
LID
PCI_STP#
PWRBTN#
RI#
RSMRST#
SMBALERT#
SMBCLK
SMBDATA
SUSA#
SUSB#
SUSC#
SUS_STAT1#
SUS_STAT2#
THRM#
ZZ/

GPIN
FUNCTION
PWR
=============================
FRQ_SEL
MAIN
GPI1
SCI#
RESUME
KBD_US/JP#
GPI2
MAIN
GPI3
REQB#
MAIN
CRT_IN#
GPI4
MAIN
GPI5
MID3
MAIN
GPI6
X
RESUME
GPI7
SERIRQ
MAIN
GPI8
THRM#
MAIN
GPI9
MB/ID0
RESUME
RESUME
GPI10
GPI11
MB/ID1
RESUME
WAKEUP#
GPI12
RESUME
GPI13
LCD_ID0
MAIN
LCD_ID1
GPI14
MAIN
GPI15
GPI15
MAIN
GPI16
MID0
MAIN
GPI17
MID1
MAIN
GPI18
MID2
MAIN
GPI19
DOCK_IN
MAIN
LCD_ID2
GPI20
MAIN
GPI21
CARD_ACT
MAIN

FDD_PWR# 7
HDD_RSTDRV 7
HDD_PWR# 7
CD_PWR# 7
CD_RSTDRV 7
VGA_SUS# 8,19
AUDIO_RST# 13
U24

SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

MEMCS16#
MEMR#
MEMW#
SMEMR#
SMEMW#
SYSCLK
BALE
IOCHK#
REFRESH#
IOCS16#
ZEROWS#
SBHE#
RSTDRV
IOR#
IOW#
IOCHRDY
AEN

IDSEL: AD18

M16
M5
R5
J4
N3
N18

gpi9
U19
19 MB/ID0
gpo17
R1
5 CPU_STP#
V20
17,19 EXTSMI#
gpi10
P16
19 GPI10
gpo18
R2
5 PCI_STP#
+3V
R217
U20
19 PWRBTN#
P18
17,19 WAKEUP#
1
2
M17
20
RSMRST#
gpi11
R212 10K_NA
0
0603
N17
19 MB/ID1
1
2
R19
4,5 SMBCLK
0603
D24
BAT54_NA
T20
4,5 SMBDATA
1
3
W20
5,8,17,18,20,23,24 SUSA#
1
2 0_NA
V19
21 SUSB#
R201
U18
17 SUSC#
gpo20 T17
PX4SUSB#
3 SUS_STAT1# gpo21
Due to SUSB# is low when reset,
1
T18
JT524
gpi8
H19
drive this pin by H8 GPO.
17,19 THRM#
1 gpo19
K16
reserve PIIX4 SUSB#
JT514
M18
17,20 PWROK
K17
14 SPKR
V18
19 PIIX4_TEST#
R141 1
2 100K 0603B
R17
C
+3V
R148 1
2 100K 0603B
R18
gpo12
J17
16 IRMD0
gpo13
H18
16 IRMD1
gpi5
K18
19 MID3
gpi2 M1
KBD_US/JP#
GND
17,19 KBD_US/JP#
gpi3
N2
19 REQB#
gpi4
P3
9 CRT_IN#
N1
P2
P4

PIIX4

IRQ0/GPO14
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IQR15
IRQ8#
IRQ12/M
SERIRQ
PIRQA#
PIRQB#
PIRQC#
PIRQD#

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS/USB

gpi6

H20
J20
T9
W9
U8
V8
Y8
U1
U12
W13
V14
Y14
Y20
T13
J19
R3
R4
P5
G1

SLP#
CPURST
FERR#
IGNNE#
INIT
INTR
A20GATE
NMI
SMI#
STPCLK#
RCIN#
A20M#

D10
E7
E13
J9
J10
J11
J12
K9
K10
K11
K12
L9
L10
L11
L12
M9
M10
M11
M12
J5

17,19 IRQ1
16,19 IRQ3
16,19 IRQ4
16,19 IRQ5
16,19 IRQ6
16,19 IRQ7
16,19 IRQ9
16,19 IRQ10
16,19 IRQ11
7,19 IRQ14
7,19 IRQ15
17 IRQ8#
17,19 IRQ12
11,19 SERIRQ
8,11,19 PIRQA#
11,19,21 PIRQB#
13,19 PIRQC#
19 PIRQD#

K20
M19
K19
L17
L18
L19
P1
L20
P20
J18
N20
M20

SUSCLK
CLK48
OSC
PCICLK

GPO0
GPO8
GPO27
GPO28
GPO29
GPO30

R174 0 0603
1
2
1

JT30
2 PX4_FERR#
USE SLEEP MODE INSTEAD OF
20 IGNNE#
QUICK START MODE
2 C_INIT#
20 INTR
17 A20GATE
20 NMI
2 SMI#
2 STPCLK#
17,19 RCIN#
20 A20M#

REQ0#
REQ1#
REQ2#
REQ3#

G4
T19
G5
F2
F3
F4

P17
L3
V11
D11

5 SUSCLK
5 USB_48MHZ
5 14MPIIX4

2 SLP#

E10
A11
B11
C11

JT512

5 PCLKPIIX4

GND

3,11,19 P_REQ0#
3,13,19 P_REQ1#
3,19,21 P_REQ2#
8,19 VGA_REQ#

GPI1
GPI13
GPI14
GPI15
GPI16
GPI17
GPI18
GPI19
GPI20
GPI21

card bus
pci audio
modem
agp

TRDY#
STOP#
SERR
PHLDA#
PHOLD#
PCIRST#
PAR
IRDY#
FRAME#
DEVSEL#
CLKRUN#

C5
D5
A6
A12
B12
A1
B6
B5
A5
E5
C10

C214
47P_NA
0603

E9
E11
E12
E16
F5
F6
F14
F15
G6
P15
R6
R7
R15
T6
K5

0603B_DFS

SD[0..15] 16,17,19

gpo7
gpo6
gpo5
gpo4
gpo3
gpo2
gpo1

+3V
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

C/BE3#
C/BE2#
C/BE1#
C/BE0#

R136
100
0603B

(+3VS)
+3V L22
BEAD_DFS

7
7
7
7
7

32.768KHZ
CM200_MC306
R184
1
2
1M_NA
0603B
C283
18P
0603B

VREF_5VS

0603

1
1K
0603B

AD18

2 0

R122

(+5VS)
+5V

3,11,13,21 AD[0..31]
3,11,13,21 C/BE3#
3,11,13,21 C/BE2#
3,11,13,21 C/BE1#
3,11,13,21 C/BE0#
3,11,19,21 CLKRUN#
3,11,13,19,21 DEVSEL#
3,11,13,19,21 FRAME#
3,11,13,19,21 IRDY#
3,11,13,21 PAR
3,8,11,12,13,21 PCIRST#
3,19 PHOLD#
3,19 PHLDA#
3,11,13,19,21 SERR#
3,11,13,19,21 STOP#
3,11,13,19,21 TRDY#

GND

GND

C282
18P
0603B

PDD[0..15] 7
PDDACK# 7
PDDREQ 7
PDIOR# 7
PDIOW# 7
PIORDY 7

+3V

+3V

VCC_RTC

C266
0.1U
0603B

C222
0.1U
0603B

C238
0.1U
0603B

C287
0.1U
0603B

C303
0.1U
0603B

C226
0.1U
0603B

C243
0.1U
0603B

+3VS_USB

GND

GND

GND

C274
0.1U
0603B
MITAC INTERNATIONAL CORP.
Title
6120W/N - MOTHER BD

GND

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

6
8

of

24

(+5VS)
+5V

terminating resistors should be place close to PIIX4E


+12V

PRIMARY IDE & FDD CONNECTOR


D

R100
1M
0603B

6 FDD_PWR#

RP66
RDDP11
RDDP3
RDDP12
RDDP2
RDDP13
RDDP1
RDDP14
RDDP0

2
6 PIORDY

hdd
D5

+5VS_HDD
R8
1

2
680
0603B

PIDEACT#

CL-190G
LED_CL190

1
A2
D6
CL-190G
LED_CL190

DRV0# 16
INDEX# 16
DIR#

DIR# 16

MTR0# 16

RDDP8
RDDP9
RDDP10
RDDP11
RDDP12
RDDP13
RDDP14
RDDP15

pull hi to +5vs_cdrom
CD_RST#

6 CD_RSTDRV

PIDE_PU
PIOCS16#
pd diag
RDAP2
RCS3P#

Q19
DTC144WK
SOT23AN_1

R205
470
0603B
C27
10P
0603

GND

GND

GND
DSKCHG 16

RPDDREQ
RPDIOW#
RPDIOR#
PIORDY
RPDDACK#
RIRQ14
RDAP1
RDAP0
RCS1P#
PIDEACT#

GND

R94
1K
0603B

R9
680
0603B

HDD_RST#
RDDP7
RDDP6
RDDP5
RDDP4
RDDP3
RDDP2
RDDP1
RDDP0

+5VS_HDD

RP33X8
RP_16P8R_4016

GND

C22
10P
0603

RPDDACK#
RPDDREQ
RPDIOW#
RPDIOR#
RDAP0
RDAP2
RCS1P#
RCS3P#

59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

GND

16 HDSEL#
16 RDATA#
16 WPROT#
16 TRK0#
16 WGATE#
16 WDATA#
16 STEP#
6 FDD_MODE

60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

6 PDIOW#
6 PDIOR#
6 PDA0
6 PDA2
6
PDCS1#
0603B
6 PDCS3#
R143
5.6K

HDSEL#
RDATA#
WPROT#
TRK0#
WGATE#
WDATA#
STEP#
FDD_MODE

6 PDDACK#
6 PDDREQ

C292
1U
0603B

GND2
GND1

J515

RP70
16
15
14
13
12
11
10
9

+5VS_FDD
1

GND

RP33X8
RP_16P8R_4016

1
2
3
4
5
6
7
8

L23
BEAD_120Z/100M
0805C
1

16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

PDD11
PDD3
PDD12
PDD2
PDD13
PDD1
PDD14
PDD0

6 PDD11
6 PDD3
6 PDD12
6 PDD2
6 PDD13
6 PDD1
6 PDD14
6 PDD0

HDD_RST#
Q17
DTC144WK
SOT23AN_1

6 HDD_RSTDRV

+5VS_FDD

GND

C293
0.1U
0603B

RP33X8
RP_16P8R_4016

pull hi to +5vs_hdd

Q16
SI2302DS
SOT23_FET

D
S

G
Q15
DTC144WK
SOT23AN_1

RDDP15
RDDP7
RDDP8
RDDP6
RDDP9
RDDP5
RDDP10
RDDP4

16
15
14
13
12
11
10
9

RP63

1
2
3
4
5
6
7
8

PDD8
PDD6
PDD9
PDD5
PDD10
PDD4

6 PDD8
6 PDD6
R169 6 PDD9
5.6K 6 PDD5
6 PDD10
0603B 6 PDD4

PDD15

6 PDD15

32

10k pull dn
PDD7

6 PDD7

GND

GND

CONN_AMP11201-6_60

+5VS_HDD

GND
+5VS_HDD

(+5VS)

C284
1U
0603B

RP33X4
RPSOA_8C

GND
GND

RP38

+5V

HDD_RST#
PIOCS16#
SIOCS16#
CD_RST#

SI2302DS
SOT23_FET
+12V
2

C286
G
0.1U
0603B

C26
10P
0603

R98

G Q14
2N7002
SOT23_FET
+5VS_CDROM

RIRQ14
RDAP1
RDAS1
RIRQ15

S
8
7
6
5

Q12

RP44

D
S
D

D
S

6,19 IRQ14
6 PDA1
6 SDA1
6,19 IRQ15

D
S

Q11
2N7002
SOT23_FET 1
2
3
4

G
D

RP10KX4 RPSOA_8C
8
+5VS_HDD
7
6
5
+5VS_CDROM

1
2
3
4

1M 0603B

Q13
DTC144WK
SOT23AN_1

HDD_PWR# 6

RP65
SDD8
SDD9
SDD7
SDD10
SDD6
SDD11
SDD5
SDD12

6 SDD8
6 SDD9

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

RDDS8
RDDS9
RDDS7
RDDS10
RDDS6
RDDS11
RDDS5
RDDS12

14 CDROM_LEFT

GND
GND
CDROM_RIGHT 14

Add via to GND per inch

RP33X8
RP_16P8R_4016

R178
10K
0603B

6 SDD10
6 SDD6
6 SDD11
6 SDD5
6 SDD12

10k pull dn
6 SDD7

GND

CDROM_GND 14
J513

RP62

6 SDDREQ

+5VS_CDROM
16
15
14
13
12
11
10
9

RDDS4
RDDS13
RDDS3
RDDS14
RDDS2
RDDS15
RDDS1
RSDDREQ

1
2
3
4
5
6
7
8

R150
1K
0603B
SIORDY

6 SIORDY

RP33X8
RP_16P8R_4016

R158
5.6K
0603B

RSDIOW#

SDD4
SDD13
SDD3
SDD14
SDD2
SDD15
SDD1

6 SDD4
6 SDD13
6 SDD3
6 SDD14
6 SDD2
6 SDD15
6 SDD1

CDROM_LEFT
GND
CD_RST#
RDDS7
RDDS6
RDDS5
RDDS4
RDDS3
RDDS2
RDDS1
RDDS0

RIRQ15
RDAS1
RDAS0
RCS1S#
SIDEACTS#

RP60

SDD0

6 SDD0
6 SDIOR#
6 SDIOW#
6 SDDACK#
6 SDA2
6 SDA0
6 SDCS3#
6 SDCS1#

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

RDDS0
RSDIOR#
RSDIOW#
RSDDACK#
RDAS2
RDAS0
RCS3S#
RCS1S#

SIDE_PU

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26

A1 CDROM_RIGHT
CDROM_GND
A2
RDDS8
A3
RDDS9
A4
RDDS10
A5
RDDS11
A6
RDDS12
A7
RDDS13
A8
RDDS14
A9
RDDS15
A10
RSDDREQ
A11
RSDIOR#
A12
A13
RSDDACK#
A14
SIOCS16#
A15
A16
RDAS2
A17
RCS3S#
A18
A19
A20
A21
A22
A23
A24
A25
A26

fdd pull high

+5VS_FDD
RP73

SECONDARY IDE CONNECTOR

INDEX#

1
2
3
4
5

10
9 DSKCHG
8 RDATA#
7 WPROT#
6 TRK0#
RP4.7KX8
RPSOE_10

GND

GND
FM/26PX2/.5MM

RP33X8
RP_16P8R_4016

+5VS_CDROM

Q18
(+5VS)

L25

CL-190G
LED_CL190

R139
470
0603B

1
K

C236
G
0.1U
0603B
1

GND
Q21
DTC144WK
SOT23AN_1

680
0603B

D4

C223
BEAD_120Z/100M
1U
0603B 0805C

R147

D
S

2
cdrom
+5VS_CDROM

GND

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26

+5V

SI2302DS
SOT23_FET
+12V
2

R140 1M 0603B

CD_PWR# 6

GND

GND

MITAC INTERNATIONAL CORP.


Title
6120W/N- MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

7
8

of

24

+3V
+5V

SHORT-SMT4
U13
3

VOUT

VIN
GND

2
1

CHECK CURRENT

C96

G_SBA[0..7]
G_RBF#
G_ADSTBA
G_ADSTBB
G_SBSTB
1

G_SBA[0..7]
G_RBF#
G_ADSTBA
G_ADSTBB
G_SBSTB

4.7U_NA
1206

10U_NA
1206

3,19
3,19
3,19
3,19
3,19

TC55RP3302EMB_NA
SOT89N
C97

R65

V_AVDD

RP20
8 GLOCLAMP
VSS1
7
6
5

2
2

1
2
3
4
V_A2GND

0*4_NA
1206
INSTALL FOR MOBILITY

GND

VSS1
C142
0.01U
0603B

JP_NET
JP_NET20

GND

JT9
JT8

JP_NET
JP_NET20

GND

JT7

C141
0.01U
0603B

C140
0.1U
0603B

1
C116
1U
0805
16V

JL33

GLOCLAMP
VSS1
VSS1

P/PA_GND
LPVDD

BEAD_120Z/100M
0805C

1
1

C212
0.1U
0603B

C117
1U
0805
16V

JL34

L9

1
1

P/PAVDD

BEAD_120Z/100M
0805C

+5V

C139
0.1U
0603B

JP_NET
JP_NET20
1

LP_GND

3
1

R63

Q8
DTC144WK
2

+3V
R118 10K

10K
0603

JT13

0603B

C1

V_AVDD
V_A2VDD
P/PAVDD

D2
P1
K17
H4
H3

2
XTALIN
XTALOUT

VGA_32K
1

5 VGA_32K

R60
442_1%
0603B

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ZVPORT0
ZVPORT1
ZVPORT2
ZVPORT3
ZVPORT4
ZVPORT5
ZVPORT6
ZVPORT7
ZVPORT8
ZVPORT9
ZVPORT10
ZVPORT11
ZVPORT12
ZVPORT13
ZVPORT14
ZVPORT15
ZVPORT16
ZVPORT17
ZVPORT18

LCDTMG3
LCDTMG2
LCDTMG1
LCDTMG0
LCDD0
LCDD1
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD8
LCDD9
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD16
LCDD17
LCDD18
LCDD19
LCDD20
LCDD21
LCDD22
LCDD23
LCDD24
LCDD25
LCDD26
LCDD27
LCDD28
LCDD29
LCDD30
LCDD31
LCDD32
LCDD33
LCDD34
LCDD35
PVDD
AVDD
A2VDD
PAVDD
LPVDD
LPVDDR
CLKRUN#
XTALIN
XTALOUT
R2SET
SYNC
BLON
F32K
RSET

STAND_BYB
STP_AGPB
SUSPENDB
AGP_BUSYB
BIASON
C
Y
COMP
DIGON

V_AGND

V_A2GND
V_A2GND

+3V

JT10

TV_CRMA
TV_LUMA

VMCKE

VMCLK

VMCLK 10

VCS#1 10
VCS#0 10
VWE# 10
VDSF 10
VRAS#0 10
VCAS#0 10
VMA10 10

VMCKE 10

XTALIN

XTALOUT

R67

1M
0603B
X2
1

29.498928MHZ
TXC7X5

3
2
4

C146
18P
0603B

GND

GND

C145
18P
0603B

+3V
2 10K 0603B

+3V

C205
1U
0603B

C137
0.01U
0603B

C163
0.01U
0603B

C213
0.1U
0603B

C192
0.1U
0603B

C171
0.1U
0603B

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD

+3V

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02

LP_GND
GND

33

V_AGND
P/PA_GND

0603B
2

TV_CRMA 9
TV_LUMA 9
TV_COMP 9
FPVCC 9

GND
1

R83
VMMCLK 1
VCS#1
VCS#0
VWE#
VDSF
VRAS#0
VCAS#0
VMA10

SUSA# 5,6,17,18,20,23,24
VGA_SUS# 6,19
AGP_BUSY# 19

ATI_RAGE_LTPRO
BGA328

+3V
GND

R62

VDQM#[0..7] 10

VMMD48
VMMD48
16
1
VMMD49
VMMD49
15
2
VMMD50
VMMD50
14
3
VMMD51
VMMD51
13
4
VMMD52
RP50
VMMD52
12
5
VMMD53
0*8
VMMD53
11
6
VMMD54
RPX8
VMMD54
10
7
VMMD55 RP_16P8R_4016_DFS
VMMD55
9
8
VMMD56
VMMD56
16
1
VMMD57
VMMD57
15
2
VMMD58
VMMD58
14
3
VMMD59
VMMD59
13
4
VMMD60
RP51
VMMD60
12
5
VMMD61
0*8
VMMD61
11
6
VMMD62
RPX8
VMMD62
10
7
VMMD63 RP_16P8R_4016_DFS
VMMD63
9
8
JT24
1
VMA0
VMMA0
VMMA0
16
1
VMA1
VMMA1
VMMA1
15
2
VMMA2
VMMA2
RP26
VMA2
14
3
VMA3
VMMA3
VMMA3
RP33X8
13
4
VMMA4
VMMA4
RP_16P8R_4016
VMA4
12
5
VMMA5
VMMA5
VMA5
11
6
VMMA6
VMMA6
VMA6
10
7
VMMA7
VMA7
VMMA7
9
8
VMMA8
R88 33
VMMA8
1
2 0603B VMA8
VMMA9
VMMA9
R99 33
1
2 0603B VMA9
VMRAS#0
RP_16P8R_4016
16
1
VMCAS#0
VMCS#1
15
2
VMMCLK
RP23
VMCS#0
14
3
VMWE#
RP33X8
VMWE#
13
4
VMCS#0
VMDSF
12
5
VMCS#1
VMRAS#0
11
6
VMDSF
VMCAS#0
10
7
VMMA10
VMMA10
9
8
VMCS#3
VMCS#3 10
VMDQM#0
VDQM#0
VMDQM#0 16
1
VMDQM#1
VMDQM#1 15
VDQM#1
2
VMDQM#2
VMDQM#2 14
RP35
VDQM#2
3
VMDQM#3
VMDQM#3 13
RP33X8
VDQM#3
4
VMDQM#4
RP_16P8R_4016
VMDQM#4 12
VDQM#4
5
VMDQM#5
VMDQM#5 11
VDQM#5
6
VMDQM#6
VMDQM#6 10
VDQM#6
7
VMDQM#7
VMDQM#7
VDQM#7
9
8
R73 1
33
0603B
2
JT14
1
JT16
1
JT15
1
JT18
1
JT17
1
JT21
+3V
1
JT20
1
JT19
1
JT23
1
JT22
1
R66 1
2 10K 0603B
JT508
1
JT507
1
JT26
1
JT25
1
DDCK
DDCK 9
DDDA
DDDA 9
HSYNC
HSYNC 9
VSYNC
VSYNC 9
RED
RED 9
GREEN
GREEN 9
BLUE
BLUE 9

Y2
C15
Y3
B15
W1
N2
N1
N3
V3

R59
442_1%
0603B

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
RBF#
ADSTB0
ADSTB1
SBSTB
PCI33EN

C138
0.1U
0603B

C144
0.1U
0603B

R70
0_NA
0603

ST0
ST1
ST2

C169
0.1U
0603B

C164
0.01U
0603B

2
1

INSTALL FOR MOBILITY

C136
0.01U
0603B

H19
E2
D1
N4
P2
Y1
W2
D3

GND
+3V

C159
1U
0603B

V2
V1
U4
U3
G4
F3
F2
E1
F1
G3
G2
G1
H1
H2
J3
J2
J1
K4
K3
K2
K1
L1
L2
L3
L4
M1
M2
M3
P3
P4
R1
R2
R3
R4
R5
T1
T2
T3
T4
U1

P/PAVDD

LPVDD
LPVDD

18 ENABKL_VGA

+3V

1
1
1
1

V_AGND

C115
1U
0805
16V

JL35

GND
2

TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKOUTTXCLKOUT+
JT2
JT4

TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKOUTTXCLKOUT+

V_A2VDD

BEAD_120Z/100M
0805C

L10

C143
0.1U
0603B

JP_NET
JP_NET20

GND
2

JL511

L8

C118
1U
0805
16V

BEAD_120Z/100M
0805C

9
9
9
9
9
9
9
9

A19
B18
A17
C17
E16
B16
C16
A15
H18
C13
F17
C20
V4

JT5
JT11
JT506
JT6

GND

GND

G_SBA0
G_SBA1
G_SBA2
G_SBA3
G_SBA4
G_SBA5
G_SBA6
G_SBA7

0603B

GND

L11

H16
H17
H20

VDQM#[0..7]

JS1
1

G_ST0
G_ST1
G_ST2

VMA[0..9] 10

3 G_ST0
3 G_ST1
3 G_ST2

VMD[0..63] 10

VMA[0..9]

PIRQA#
G_PIPE#
G_FRAME#
G_IRDY#
G_TRDY#
G_DEVSEL#
G_STOP#
G_PAR
G_GNT#
G_REQ#

PIRQA#
G_PIPE#
G_FRAME#
G_IRDY#
G_TRDY#
G_DEVSEL#
G_STOP#
G_PAR
G_GNT#
G_REQ#

T5,U13,U8

VMD0
VMD1
VMD2
VMD3
VMD4
VMD5
VMD6
VMD7
VMD8
VMD9
VMD10
VMD11
VMD12
VMD13
VMD14
VMD15
VMD16
VMD17
VMD18
VMD19
VMD20
VMD21
VMD22
VMD23
VMD24
VMD25
VMD26
VMD27
VMD28
VMD29
VMD30
VMD31
VMD32
VMD33
VMD34
VMD35
VMD36
VMD37
VMD38
VMD39
VMD40
VMD41
VMD42
VMD43
VMD44
VMD45
VMD46
VMD47
VMD48
VMD49
VMD50
VMD51
VMD52
VMD53
VMD54
VMD55
VMD56
VMD57
VMD58
VMD59
VMD60
VMD61
VMD62
VMD63

6,11,19
3,19
3,19
3,19
3,19
3,19
3,19
3,19
3,19
3,19

M10,M11,M12,M9,R7,T15

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8

3,6,11,12,13,21 PCIRST#

K12,K9,L10,L11,L12,L9

16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9

G_REQ#

BAW56
SOT23N

J11,J12,J5,J9,K10,K11

VMMD0
VMMD1
VMMD2
VMMD3
VMMD4
VMMD5
VMMD6
VMMD7
VMMD8
VMMD9
VMMD10
VMMD11
VMMD12
VMMD13
VMMD14
VMMD15
VMMD16
VMMD17
VMMD18
VMMD19
VMMD20
VMMD21
VMMD22
VMMD23

6,19 VGA_REQ#

E12,E9,F15,F7,G6,J10

VMMD0
VMMD1
VMMD2
VMMD3
VMMD4
RP37
VMMD5
0*8
VMMD6
RPX8
VMMD7 RP_16P8R_4016_DFS
VMMD8
VMMD9
VMMD10
VMMD11
VMMD12
RP42
VMMD13
0*8
VMMD14
RPX8
VMMD15 RP_16P8R_4016_DFS
VMMD16
VMMD17
VMMD18
VMMD19
VMMD20
RP46
VMMD21
0*8
VMMD22
RPX8
VMMD23 RP_16P8R_4016_DFS

AGP_BUSY#

GND:

Y11
U12
V12
W12
Y12
V13
W13
Y13
U14
V14
W14
Y14
U15
V15
W15
Y15
U16
V16
W16
Y16
V17
W17
Y17
W18
Y18
W19
Y19
Y20
W20
V19
V18
V20
U20
U19
U18
U17
T20
T19
T18
T17
R16
R20
R19
R18
R17
P20
P19
P18
P17
N16
N20
N19
N18
N17
M20
M19
M18
M17
L20
L19
L18
L17
K20
K19
W5
T6
Y7
W7
V7
U7
Y8
W8
V8
Y9
W9
U5
Y6
V6
W4
W3
Y4
V5
W6
U2
V9
U9
Y10
W10
V10
U10
V11
W11
Y5
A1
A2
B2
A3
B3
A4
B4
C4
A5
B5
C5
D5
E5
A6
B6
C6
D6
E3
F4
C3
C2
B1

VMD[0..63]

U18
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
ROMCS#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
RAS#0
CAS#0
OE#0
OE#1
CS#0
CS#1
DSF
CS#2
CS#3
DQM#0
DQM#1
DQM#2
DQM#3
DQM#4
DQM#5
DQM#6
DQM#7
CKE
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
HSYNC#
VSYNC#
R
G
B

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
CPUCLK
RESET#
INTR#
PIPE#/IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
GNT#
REQ#

D14

B11
A11
C11
D12
C12
A12
B12
D13
A13
E14
C14
D14
A14
A18
D15
B14
D18
C19
E17
E18
D20
B20
F18
F19
G18
G19
F20
D17
J20
G16
G20
F16
B13
E15
E20
C18
J19
G17
K16
E19
D19
A20
B19
D16
B17
A16
J18
J17

PVSS
PAVSS
A2VSS1
A2VSS2
AVSS1
AVSS2
LPVSSR1
LPVSSR2
LPVSS
VDDP1
VDDP2
VDDP3
VDDP4
VDDP5
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR

3 CLKAGP

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

F5
K18
M4
M5
D4
E4
G5
L5
J4
J16
E11
F14
E13
G15
E10
H6
K5
L16
T10
U11
E8
F6
H5
T9
N5
P15
P6
T12
T14
T7

G_C/BE#[0..3]

3 G_C/BE#[0..3]

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31
G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

ZV_Y[0..7] 12
ZV_UV[0..7] 12
ZV_HREF 12
ZV_VSYNC 12
ZV_PCLK 11,12

U6
T8
T16
T13
T11
R6
R15
P5
P16
M16
D11
D10
C10
B10
A10
D9
C9
B9
A9
D8
C8
B8
A8
E7
D7
C7
B7
A7
E6

ZV_PCLK
ZV_VSYNC
ZV_HREF
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4
ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
ZV_Y7
ZV_Y6
ZV_Y5
ZV_Y4
ZV_Y3
ZV_Y2
ZV_Y1
ZV_Y0

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

ZV_Y[0..7]
ZV_UV[0..7]

0603

2 2.2K_NA

R117 1

+3V

Sheet

8
8

of

24

(+3VS)
+3V

+12V

+5V

R28
1M
0603B

2 BEAD_130Z/100M
2 BEAD_130Z/100M

0603B
0603B

TV_LUMA 8
TV_CRMA 8

C505
100P
0603B

RP22
RP75X4
RPSOA_8

GND
L24
120Z/100M
2012

C507
100P
0603B

8
7
6
5

0
0805C

R2
100K
0603B

GND

GND

C3
100P
0603B

R236
0
0603

8 TXCLKOUT+
8 TXCLKOUT-

SW2
HDS404E

8 TXOUT2+
8 TXOUT25
6
7
8

CRTGND

8 TXOUT18 TXOUT1+

2 BSEL100
+5V

L1

BEAD_120Z/100M_NA
0805C

8 TXOUT0+
8 TXOUT0-

C2
1000P_NA
0603B

TXCLKOUT+
TXCLKOUT-

TXOUT2+
TXOUT2TXOUT1TXOUT1+
TXOUT0+
TXOUT0-

GND

MINISMDC110_NA
POLYSW_MINISMDC110

F1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

VCC_CMOS

D_CRT_IN#

1K
0603B

R3

6 CRT_IN#

J2

LCD_ID0
LCD_ID1
LCD_ID2

6,19 LCD_ID0
6,19 LCD_ID1
6,19 LCD_ID2

GND
1

AVGND

4
3
2
1

L518

(+3VS)
+3V
2

C506
100P
0603B

C510
100P
0603B

FXC
MH1174-F6S

1
2
3
4

GND1
GND2

GND1
GND2

Q4
GND
DTC144WK
SOT23AN_1

8 FPVCC
L515 1
L517 1

3
TV_COMP 8

1
2
3
4

1
2
3
4

Q3
SI2302DS
SOT23_FET

C33
0.22U
0603B

18 D/CRMA

Q37
2N7002

D
S

D
S

D
18 D/LUMA

J509

R233
10K
0603B

CRTGND

GND1
GND2

J505
16
L512 1

2 BEAD_130Z/100M

0603B

L511 1

2 BEAD_130Z/100M

0603B

L510 1

2 BEAD_130Z/100M

0603B

RED
GREEN
BLUE

RED 8
GREEN 8
BLUE 8

GND
GND
J6

5
6
7
8

1
2
3
4

1
9
2
10
3
11
4
12
5
13
6
14
7
15
8

HDR/MA/.625/21P
FI-WE21P-HF
JAE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

RP501
RP75X4
RPSOA_8

CA502

8
7
6
5

47PX4
RPSOA_8C

4
3
2
1

TXOUT0TXOUT0+

17
CRTGND
VGA
CRTGND
SUYIN
7535S-15G2T-05
2

D_VSYNC

L508 1

2 BEAD_130Z/100M

0603B

33

0603B

HSYNC 8
33

VSYNC 8
Q24

(+5VS)
+5V

2 BEAD_130Z/100M

G
S

DDCK 8

TXCLKOUTTXCLKOUT+

2N7002 D

0603B

D
S

2 BEAD_130Z/100M

DDDA 8

L506 1

5
6
7
8

TXOUT2TXOUT2+
R72
4.7K
0603

Q25

R505
4.7K
0603

CA501

2N7002

+5V

GND1
GND2
GND3
GND4

47PX4
RPSOA_8C

R506
4.7K
0603
2

0603B

R92
4.7K
0603

D
S

L507 1

FROM VGA CHIP

0603B

0603B

2 BEAD_130Z/100M

R507

D_DDCK

TXOUT1+
TXOUT1-

+5V
R508
L509 1

CRTGND
D_HSYNC

GND

FA504
4
3
2
1

D_DDDA

CRTGND

18 D/BLUE
18 D/DDDA
18 D/DDCK
18 D/GREEN
18 D/CRT_IN#
18 D/VSYNC
18 D/RED
18 D/HSYNC

1
2
3
4

120OHM/100MHZ
BLUE
8
D_DDDA
7
D_DDCK
6
GREEN
5

1
2
3
4

8
7
6
5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND1
GND2
GND3
GND4
MA/30P/0.5MM

GND

D_CRT_IN#
D_VSYNC
RED
D_HSYNC

5
6
7
8

FA501
120OHM/100MHZ
RPSOA_8D

CA2
47PX4
RPSOA_8C

4
3
2
1

JL502
JP_NET
JP_SMT4_DFS
JL503

NEAR PORT REPLICATOR


GND
MITAC INTERNATIONAL CORP.
Title

JP_NET
JP_SMT4_DFS
CRTGND

6120W/N - MOTHER BD
GND

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

9
8

of

24

RP87
1
2
3
4

8 VMCS#3

VMA_10
VMA_9
VMA_8
VCS#3

8
7
6
5

SAMSUNG 8MB SGRAM


+3V

+3V

+3V

+3V

0*4
1206
RP88

1
R138
10K_NA
0603B

R81
10K_NA
0603B
2

ETRONTECH 8MB SGRAM


2

8
7
6
5

R137
10K_NA
0603B
2

1
2
3
4

VCS#1
VMA10
VMA9
VMA8

R101
10K
0603B

VCS1#
VMA_10
VMA_9
VMA_8

8
8
8
8

VMD41
0*4_NA
1206

VMD47
VMD48
VMD49

VMD[0..63]

8 VCS#0
8 VRAS#0
8 VCAS#0
8 VWE#

VMCKE

54

VCS#0

28

VRAS#0

27

VCAS#0

26

VWE#

25

R79
10
0603B
VMCLK

8 VMCLK

VDQM#3

57

VDQM#2

24

VDQM#1

56

VDQM#0

23

55

VDSF

8 VDSF

53

CKE
CS
RAS
CAS
WE
DQM3
DQM2
DQM1
DQM0
CLK
DSF

VCCQ1
VCCQ2
VCCQ3
VCCQ4
VCCQ5
VCCQ6
VCCQ7
VCCQ8
VCC1
VCC2
VCC3
VCC4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSS1
VSS2
VSS3
VSS4

SGRAM_512K*32-100
PQFP100F_EIAJ

2
8
14
22
59
67
73
79
15
35
65
96
5
11
19
62
70
76
82
99
16
46
66
85

+3V

VMCLK 1

R229
10
0603B

VMCKE

54

VCS#0

28

VRAS#0

27

VCAS#0

26

VWE#

25

VDQM#7

57

VDQM#6

24

VDQM#5

56

VDQM#4

23

55
VDSF

53

CAS
WE
DQM3
DQM2
DQM1
DQM0
CLK
DSF

+3V

C124
0.1U
0603B

C104
0.1U
0603B

C156
0.1U
0603B

C166
0.1U
0603B

C193
1U
0603B

+3V

GND

GND

2
1
2

C358
0.1U_NA
0603
50V

GND

C154
0.1U
0603B

1
2

1
2

1
2

1
2

C155
0.1U
0603B

RAS

2
8
14
22
59
67
73
79
15
35
65
96
5
11
19
62
70
76
82
99
16
46
66
85

VMD63
VMD62
VMD61
VMD60
VMD59
VMD58
VMD57
VMD56
VMD55
VMD54
VMD53
VMD52
VMD51
VMD50
VMD49
VMD48
VMD47
VMD46
VMD45
VMD44
VMD43
VMD42
VMD41
VMD40
VMD39
VMD38
VMD37
VMD36
VMD35
VMD34
VMD33
VMD32

1
2
C357
0.1U_NA
0603
50V

GND
C167
0.1U
0603B

CS

VCCQ1
VCCQ2
VCCQ3
VCCQ4
VCCQ5
VCCQ6
VCCQ7
VCCQ8
VCC1
VCC2
VCC3
VCC4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSS1
VSS2
VSS3
VSS4

84
83
81
80
78
77
75
74
21
20
18
17
13
12
10
9
72
71
69
68
64
63
61
60
7
6
4
3
1
100
98
97

R274
220_NA
0603

1
2

+3V

C123
0.1U
0603B

CKE

SGRAM_512K*32-100
PQFP100F_EIAJ

GND

R273
220_NA
0603

C194
0.1U
0603B

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
A8

DIO31
DIO30
DIO29
DIO28
DIO27
DIO26
DIO25
DIO24
DIO23
DIO22
DIO21
DIO20
DIO19
DIO18
DIO17
DIO16
DIO15
DIO14
DIO13
DIO12
DIO11
DIO10
DIO9
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0

36
37
38
39
40
41
42
43
44
VCS#3
45
86
+3V
87
88
89
90
R116 91
0_NA 92
0603 93
94
95
VCS1# 52
58
VMA_8
30

A10
A9
A7
A6
A5
A4
A3
A2
A1
A0

VDQM#[7..0]

8 VDQM#[7..0]

C191
1U
0603B

29
51
50
49
48
47
34
33
32
31

VMA_10
VMA_9
VMA7
VMA6
VMA5
VMA4
VMA3
VMA2
VMA1
VMA0

VMD31
VMD30
VMD29
VMD28
VMD27
VMD26
VMD25
VMD24
VMD23
VMD22
VMD21
VMD20
VMD19
VMD18
VMD17
VMD16
VMD15
VMD14
VMD13
VMD12
VMD11
VMD10
VMD9
VMD8
VMD7
VMD6
VMD5
VMD4
VMD3
VMD2
VMD1
VMD0

1
2

8 VMCKE

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
A8

84
83
81
80
78
77
75
74
21
20
18
17
13
12
10
9
72
71
69
68
64
63
61
60
7
6
4
3
1
100
98
97

36
37
38
39
40
41
42
43
44
VCS#3 45
86
+3V
87
88
89
90
R80 91
0_NA 92
0603 93
94
95
VCS1# 52
58
VMA_8
30

U20
DIO31
DIO30
DIO29
DIO28
DIO27
DIO26
DIO25
DIO24
DIO23
DIO22
DIO21
DIO20
DIO19
DIO18
DIO17
DIO16
DIO15
DIO14
DIO13
DIO12
DIO11
DIO10
DIO9
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0

VMA7
VMA6
VMA5
VMA4
VMA3
VMA2
VMA1
VMA0

A10
A9
A7
A6
A5
A4
A3
A2
A1
A0

8 VMA[0..7]

29
51
50
49
48
47
34
33
32
31

U14
VMA_10
VMA_9
VMA7
VMA6
VMA5
VMA4
VMA3
VMA2
VMA1
VMA0

VMA[0..7]

8 VMD[0..63]

GND

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

10
8

of

24

+3V

12 B_CD1#
12 B_CD2#
12 BCE1#
12 BCE2#
12 BOE#
12 BIORD#
12 BIOWR#
12 BWE#
8,12 BWP
12 BBVD1
12,13 BBVD2
12 BWAIT#
12 BRDY
12 BVS1
12 BVS2
12 BREG#
12,13 BINPACK#
12 BRESET

1
2
3
4
5

10
9
8
7
6

A_CD1#
A_CD2#
AVS1
AVS2

RP43KX8
RPSOE_10

CARD_VCCB

RP72
10
9
8
7
6

BCA14
BCA15
BWP
BCA20

BCD[0..15]

BCD[0..15] 12
BCA[0..25]

CARD_VCCB

BINPACK#
BBVD2
BRESET

1
2
3
4
5

10
9
8
7
6
RP43KX8
RPSOE_10

12 ACD[0..15]

BBVD1
BRDY
BWAIT#

12 AINPACK#
12 AREG#
12 ARDY
12 AWAIT#
12 ABVD2
12 ABVD1
12 AWP
12 ARESET
12 AWE#
12 AIOWR#
12 AIORD#
12 AOE#
12 AVS2
12 AVS1
12 ACE2#
12 ACE1#
12 A_CD2#
12 A_CD1#

ACA25
ACA24
ACA23
ACA22
ACA21
ACA20
ACA19
ACA18
ACA17
ACA16
ACA15
ACA14
ACA13
ACA12
ACA11
ACA10
ACA9
ACA8
ACA7
ACA6
ACA5
ACA4
ACA3
ACA2
ACA1
ACA0

121
118
116
114
111
109
107
105
103
112
115
108
106
117
100
95
102
104
119
123
125
126
128
131
132
133

AIOWR#
AIORD#

ACD[0..15]

12 ACA[0..25]

ACD15
ACD14
ACD13
ACD12
ACD11
ACD10
ACD9
ACD8
ACD7
ACD6
ACD5
ACD4
ACD3
ACD2
ACD1
ACD0

127
130
135
136
137
138
139
124
110
101
99
98
122
134
97
94
140
82
93
91
89
87
84
147
145
142
92
90
88
85
83
146
144
141

AWAIT#

ACA[0..25]

A_INPACKB/A_CRE
A_REG#/A_CCBE3
A_READY/A_CINT#
A_WAIT#/A_CSERR
A_BVD2/A_CAUDIO
A_BVD1/A_CSTSCH
A_WP/A_CLKRUN#
A_RESET/A_CRST#
A_WE#/A_CGNT#
A_IOWR#/A_CAD15
A_IORD#/A_CAD12
A_OE#/A_CAD11
A_VS2#/A_CVS2
A_VS1#/A_CVS1
A_CE2#/A_CAD10
A_CE1#/A_CCBE0#
A_CD2#/A_CCD2#
A_CD1#/A_CCD1#
A_D15/A_CAD8
A_D14/A_RSVD
A_D13/A_CAD6
A_D12/A_CAD4
A_D11/A_CAD2
A_D10/A_CAD31
A_D9/A_CAD30
A_D8/A_CAD28
A_D7/A_CAD7
A_D6/A_CAD5
A_D5/A_CAD3
A_D4/A_CAD1
A_D3/A_CAD0
A_D2/A_RSVD
A_D1/A_CAD29
A_D0/A_CAD27

C/BE3#
C/BE2#
C/BE1#
C/BE0#
PAR
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
IDSEL
REQ#
GNT#
PRST#
SUSPEND#
RI_OUT#PME#
SPKROUT
LATCH
DATA
PCLK
CLOCK
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

TI 1225
MULTIFUNCTION PIN:
MFUNC0:INTA# ; PCI INTERRUPT SIGNAL
MFUNC1:INTB# ; PCI INTERRUPT SIGNAL
MFUNC2:ZV_STAT ; ZOOM VIDEO STATUS OUTPUT
MFUNC3:IRQ AND OPTIONAL PCI ; SERIAL INTERRUPT STREAM
MFUNC4:RI_OUT# ; RING-INDICATE OUTPUT
MFUNC5:CARD_ACT ; SOCKET 0 OR SOCKET 1 ACTIVITY
MFUNC6:CLKRUN# ; PCI CLOCK CONTROL SIGNAL

IDSEL :AD19
SERIAL IRQ/PARALLEL PCI INTERRUPT:
INDEX -- 92h
CONTENTS -- 64H

A_A25/A_CAD19
A_A24/A_CAD17
A_A23/A_CFRAME#
A_A22/A_CTRDY#
A_A21/A_CDEVSEL
A_A20/A_CSTOP#
A_A19/A_CBLOCK#
A_A18A/A_RSVD
A_A17/A_CAD16
A_A16/A_CCLK
A_A15/A_CIRDY#
A_A14/A_CPERR
A_A13/A_CPAR
A_A12/A_CCBE2#
A_A11/A_CAD12
A_A10/A_CAD9
A_A9/A_CAD14
A_A8/A_CCBE1#
A_A7/A_CAD18
A_A6/A_CAD20
A_A5/A_CAD21
A_A4/A_CAD22
A_A3/A_CAD23
A_A2/A_CAD24
A_A1/A_CAD25
A_A0/A_CAD26

U25

55
53
51
49
47
45
42
40
37
48
50
43
41
52
34
29
36
39
54
57
59
60
62
65
66
67

B_RESET/B_CRST#
B_INPACK/B_CREQ
B_REG#/B_CCBE3#
B_VS2#/B_CVS2
B_VS1#/B_CVS1
B_READY/B_CINT#
B_WAIT#/B_CSERR
B_BVD2/B_CAUDIO
B_BVD1/B_CSTSCH
B_WP/B_CLKRUN#
B_WE#/B_CGNT#
B_IOWR#/B_CAD15
B_IORD#/B_CAD13
B_OE#/B_CAD11
B_CE2#/B_CAD10
B_CE1#/B_CCBE0#
B_CD2#/B_CCD2#
B_CD1#/B_CCD1#
B_D15/B_CAD8
B_D14/B_RSVD
B_D13/B_CAD6
B_D12/B_CAD4
B_D11/B_CAD2
B_D10/B_CAD31
B_D9/B_CAD30
B_D8/B_CAD28
B_D7/B_CAD7
B_D6/B_CAD5
B_D5/B_CAD3
B_D4/B_CAD1
B_D3/B_CAD0
B_D2/B_RSVD
B_D1/B_CAD29
B_D0/B_CAD27

58
61
63
56
68
69
70
71
72
73
46
35
33
32
30
28
74
16
27
25
23
20
18
81
79
77
26
24
21
19
17
80
78
76

8.2K*8 1206 5%

RP82

BCA[0..25] 12

BCA0
BCA1
BCA2
BCA3
BCA4
BCA5
BCA6
BCA7
BCA8
BCA9
BCA10
BCA11
BCA12
BCA13
BCA14
BCA15
BCA16
BCA17
BCA18
BCA19
BCA20
BCA21
BCA22
BCA23
BCA24
BCA25

1
2
3
4
5

BCD0
BCD1
BCD2
BCD3
BCD4
BCD5
BCD6
BCD7
BCD8
BCD9
BCD10
BCD11
BCD12
BCD13
BCD14
BCD15

BCA19
BCA21
BCA23
BCA22

B_A25/B_CAD19
B_A24/B_CAD17
B_A23/B_CFRAME#
B_A22/B_CTRDY#
B_A21/B_CDEVSEL
B_A20/B_CSTOP#
B_A19/B_CBLOCK#
B_A18/B_RSVD
B_A17/B_CAD16
B_A16/B_CCLK
B_A15/B_CIRDY#
B_A14/B_CPERR3
B_A13/B_CPAR
B_A12/B_CCBE2#
B_A11/B_CAD12
B_A10/B_CAD9
B_A9/B_CAD14
B_A8/B_CCBE1#
B_A7/B_CAD18
B_A6/B_CAD20
B_A5/B_CAD21
B_A4/B_CAD22
B_A3/B_CAD23
B_A2/B_CAD24
B_A1/B_CAD25
B_A0/B_CAD26

RP80
B_CD1#
B_CD2#
BVS1
BVS2

PCIREQ#/GNT# : 0
PCIINT# : A,B

C/BE3#
C/BE2#
C/BE1#
C/BE0#
PAR
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#

162
192
203
5
202
200
199
198
197
196
195
193
182
169
168
166
156
163
149
150
152
180
151
161
160
159
158
157
155
154
170
171
173
174
176
177
165
179
183
184
185
186
188
189
190
191
204
205
206
208
172
2
3
4
6
8
9
10
11
12
14
15

C/BE3# 3,6,13,21
C/BE2# 3,6,13,21
C/BE1# 3,6,13,21
C/BE0# 3,6,13,21
PAR 3,6,13,21
SERR# 3,6,13,19,21
PERR# 13,19,21
STOP# 3,6,13,19,21
DEVSEL# 3,6,13,19,21
TRDY# 3,6,13,19,21
IRDY# 3,6,13,19,21
FRAME# 3,6,13,19,21
R56 1

P_REQ0#
P_GNT0#
PCIRST#
CARD_SUS#

2 100

0603B

AD19

AD19 3,6,13,21

P_REQ0# 3,6,19
P_GNT0# 3,19
PCIRST# 3,6,8,12,13,21
CARD_SUS# 6,12
CARD_PME# 20

CARDSPK#
SER_LATCH
SER_DATA
PCLKCARD
32K_CARD
CLKRUN#

CARDSPK# 14
SER_LATCH 12
SER_DATA 12
PCLKCARD 5
32K_CARD 5
CLKRUN# 3,6,19,21
CARD_ACT 6,19
CARD_RI# 16
SERIRQ 6,19

SERIRQ
1

JT28

R153
PIRQA#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

2 0/NA

0603B

PIRQB# 6,19,21

PIRQA# 6,8,19

CARD_VCCA

RP84
AWP
ABVD1
ABVD2

1
2
3
4
5

10
9 ARESET
8 AINPACK#
7 ARDY
6 AWAIT#
RP43KX8
RPSOE_10

CARD_VCCA

ACA15
ACA22

178
VCCP1
1
VCCP

VCCI

VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCC
201
187
175
164
143
113
86
64
31
7

148

207
194
181
167
153
129
96
75
44
22
13

38
VCCB
120
VCCA

GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1

RP83
AD[0..31]

1
2
3
4
5

AD[0..31] 3,6,13,21

PCI1225PDV
PQFP208B

10
9
8
7
6

ACA19
ACA14
ACA20
ACA21

RP43KX8
RPSOE_10

+3V

C232
0.1U
0603B

1
C234
0.1U
0603B

1
C251
0.1U
0603B

C241
0.1U
0603B

C273
0.1U
0603B

1
C272
0.1U
0603B

GND

1
2

+3V

CARD_VCCA

CARD_VCCB
GND

C233
0.1U
0603B

GND
GND

1
C279
0.1U
0603B

1
C300
0.1U
0603B

1
C302
0.1U
0603B

1
C246
0.1U
0603B

+3V

C270
0.1U
0603B

MITAC INTERNATIONAL CORP.


Title
6120W/N- MOTHER BD

GND
1

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

11
8

of

24

PCCARD SOCKET
A

ACA[0..25]

11 ACA[0..25]

BCA[0..25]

U504
ACD[0..15]

11 ACD[0..15]

11 A_CD1#

ACD7
ACD15
ACE1#
ACE2#
ACA10
AVS1
AOE#
AIORD#
ACA11
AIOWR#
ACA9
ACA17

11 ACE1#
11 ACE2#
11 AVS1
11 AOE#
11 AIORD#
11 AIOWR#

ACA8
ACA18
ACA13
ACA19
ACA14
ACA20
AWE#
ACA21
ARDY
CARD_VCCA
CARD_VCCA
VPPAOUT
VPPAOUT

11 AWE#

11 ARDY
CARD_VCCA
VPPAOUT
ACA16

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72

A_CD1#
ACD3
ACD11
ACD4
ACD12
ACD5
ACD13
ACD6
ACD14

2 R18547

0603B
ACA22
ACA15
ACA23
ACA12
ACA24
ACA7
ACA25
ACA6
AVS2
ACA5
ARESET
ACA4
AWAIT#
ACA3

ZV-PORT CONNECT
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8,11
13
11,13
11,13

11 AVS2

BCA9
BCA17
BCA8
BCA18
BCA13
BCA19
BCA14
BCA20
BCA21
BCA22
BBCA16
BCA23
BCA15
BCA24
BCA12
BCA25
BCA10
BCA11
BWP
BCA7
BINPACK#
BBVD2

ZV_Y0
ZV_Y1
ZV_Y2
ZV_Y3
ZV_Y4
ZV_Y5
ZV_Y6
ZV_Y7
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_HREF
ZV_VSYNC
ZV_PCLK
ZV_SCLK
ZV_LRCLK
ZV_DATA

11 ARESET
11 AWAIT#

AINPACK#
ACA2
AREG#
ACA1
ABVD2
ACA0
ABVD1
ACD0
ACD8
ACD1
ACD9
ACD2
ACD10
AWP
A_CD2#

11 AINPACK#
11 AREG#
11 ABVD2
11 ABVD1

11 AWP
11 A_CD2#

GND3
GND4

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
GND3
GND4

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
GND1
GND2

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72

BCA[0..25] 11

BCD[0..15]
B_CD1#
BCD3
BCD11
BCD4
BCD12
BCD5
BCD13
BCD6
BCD14
BCD7
BCD15
BCE1#
BCE2#
BCA10
BVS1

BCD[0..15] 11

B_CD1# 11

BCE1# 11
BCE2# 11
BVS1 11

BOE#
BIORD#
BCA11
BIOWR#
BCA9
BCA17
BCA8
BCA18
BCA13
BCA19
BCA14
BCA20

BOE# 11
BIORD# 11
BIOWR# 11

BWE#
BCA21
BRDY
CARD_VCCB
CARD_VCCB
VPPBOUT
VPPBOUT
BBCA16
BCA22
BCA15
BCA23
BCA12
BCA24
BCA7
BCA25
BCA6

BWE# 11

BRDY 11
CARD_VCCB
VPPBOUT
0603B 47

R1891

BVS2
BCA5
BRESET
BCA4
BWAIT#
BCA3
BINPACK#
BCA2
BREG#
BCA1
BBVD2
BCA0

2 BCA16

BVS2 11
BRESET 11
BWAIT# 11
BINPACK# 11,13
BREG# 11
BBVD2 11,13

BBVD1
BCD0
BCD8
BCD1
BCD9
BCD2
BCD10
BWP
B_CD2#

BBVD1 11

BWP 8,11
B_CD2# 11

GND1
GND2

FM/72P/.6MM/H3MM
ICRD_BERG73213_002
GND

GND

POWER SWITCH MATRIX

CARD_VCCA
U33

C276
0.1U
0603B

C277
0.1U
0603B

+5V

GND

GND

GND

GND

C285
0.1U
0603B

C291
1U
0805C

GND

GND

1
2

C290
1U
0805C

1
C301
2.2U
1206

C298
2.2U
1206

VPPBOUT

GND

GND

GND

C165
0.1U
0603B

CARD_VCCB

3V1
3V2
3V3
12V1
12V2
5V1
5V2
5V3
GND

23
20
21
22
25
6
26
27
28
29
14

VPPAOUT

15
16
17
7
24
1
2
30
12

+12V

BVPP
BVCC1
BVCC2
BVCC3
VDD
NC1
NC2
NC3
NC4
NC5
NC6

8
9
10
11

C306
0.1U
0603B

+3V

AVPP
AVCC1
AVCC2
AVCC3

2 0_NA
0603B

DATA
CLOCK
LATCH
APWR_GD
BPWR_GD
OC/

R204 1

6,11 CARD_SUS#

3
4
5
13
19
18

11 SER_DATA
5 32K_PWRMX
11 SER_LATCH

C160
0.1U
0603B

GND

PCIRST# 3,6,8,11,13,21

TPS2216
SSOP30

GND

R203 1

2 0_NA

+3V

0603B
MITAC INTERNATIONAL CORP.
Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

12
8

of

24

+5V
(+3VS)
+3V

L6
BEAD_120Z/100M
0805C

(+3VS)
+3V

C40
0.1U
0603B

C114
0.1U
0603B

C47
0.1U
0603B
JL16
JP_NET
JP_NET15

C113
0.1U
0603B

GND

C112
0.1U
0603B

C110
0.1U
0603B

C102
0.1U
0603B

C111
0.1U
0603B

C42
0.1U
0603B

1
2

C81
0.1U
0603B

C41
0.1U
0603B

C38
1000P
0603B

GND

(+3VS)
+3V

C100
0.1U
0603B

C78
0.1U
0603B

C70
0.1U
0603B

GND

C/BE0#
C/BE1#
C/BE2#
C/BE3#

16
17
18
19
NC0
NC1
NC2
NC3

INTC#
P_REQ1#
P_GNT1#
REQB#
GNTB#

(+5VS)
+5V

RP7
RP4.7KX4
RPSOA_8

CS4280
PQFP128A_0.5MM

JT505
JT503

consumer digital audio


GND

zv data
zv sclk
zv lrclk

5
6
7
8

GND
1
1

R57
10K
0603

18
18
18
18

CA4
5600PX4
RPSOA_8C

1
1
1

JT502
JT504
JT501

D/JAB1
D/JAB2
D/JBB1
D/JBB2

JAB1
JAB2
JBB1
JBB2
4
3
2
1

18
18
18
18

R31
4.7K
0603B

GND

AD[0..31] 3,6,11,21

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

5
6
7
8

59
60
61
62
107
ABITCLK2
ASDOUT2
ASYNC2
ARST2#
ASDIN2

EGPIO0
EGPIO1
EGPIO2
EGPIO3/ASCLK
EGPIO4/ASFCLK
EGPIO5/ASDI
EGPIO6/ASDO
EGPIO7
EGPIO8

12
27
75
78
90
95
91
94
CVDD1
CVDD0
CVDD2
CVDD3
CVDD4
VDD5REF
CRYVDD
CRYGND

IDSEL:AD20

115
121
1
7
30
38
48
57

3,6,11,21
3,6,11,21
3,6,11,21
3,6,11,21

CRYSTAL CS4280

56
55
54
53
52
51
50
49
45
44
43
42
41
40
37
36
11
10
9
6
5
4
3
2
125
124
123
120
119
118
117
116

4
3
2
1

AD[0..31]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

TEST
NC6
NC5
NC4

0603B

5 PCLKAUDIO
3,19 P_GNT1#
3,6,19 P_REQ1#
3,6,11,19,21 FRAME#
3,6,11,19,21 IRDY#
3,6,11,19,21 TRDY#
3,6,11,19,21 DEVSEL#
3,6,11,19,21 STOP#
11,19,21 PERR#
3,6,11,19,21 SERR#
3,6,11,21 PAR
2

PME#
INTA#
RST#
PCICLK
PCI_GNT#
PCI_REQ#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
IDSEL
CBE0#
CBE1#
CBE2#
CBE3#

U11

65
22
21
20

108
109
110
111
112
113
15
24
25
28
31
32
33
34
127
46
35
14
126

20 AUDIO_PME#
6,19 PIRQC#

JAB1/SDO2
JAB2/SDO3
JBB1/LRCLK
JBB2/MCLK
JACX
JBCX
JACY
JBCY
MIDIIN
MIDIOUT

ZLRCLK
ZSCLK
ZSDATA
SPDIFI
SPDIFO

100

70
71
72
73
66
68
67
69
74
77

ABITCLK/SCLK
ASDOUT
ASDIN
ASYNC/FSYNC
ARST#

80
81
82
83
84

R55

96
97
98
99
100

SDIN2/GPIO
VOLUP/XTALI
VOLDN/XTALO
EECLK/GPOUT/PCR
EEDAT/GPIO2/PCG
EEPDIS

2
SHORT-SMT1
R232
1
2
0_NA
0603

3,6,11,21 AD20

0603B

88
92
93
101
102
23

3,6,8,11,12,21 PCIRST#

0603B

1 33

18 JAB1
18 JAB2
18 JBB1
18 JBB2
JACX
JBCX
JACY
JBCY
MIDIIN
MIDIOUT

JP17
6 AUDIO_RST#

1 33

GND0
GND1
GND2
GND3
GND4

26
13
76
79
89

R21

PCIGND0
PCIGND1
PCIGND2
PCIGND3
PCIGND4
PCIGND5
PCIGND6
PCIGND7

R20

PCIVDD3
PCIVDD4
PCIVDD5
PCIVDD6
PCIVDD7
PCIVDD0
PCIVDD1
PCIVDD2

8
29
39
47
58
114
122
128

GND

14 ABITCLK
14 ASDOUT
14 ASDIN
14 ASYNC
14 ARST#

85
86
87
103
104
105
106
63
64

/ - Second AC'97 codec interface, for DOCKING


|
|

ZV_DATA 11,12
ZV_SCLK 12
ZV_LRCLK 11,12

1
2
3
4

D/JACX 18
D/JACY 18
D/JBCX 18
D/JBCY 18

RP2.2KX4
RPSOA_8
CA5
5600PX4
RPSOA_8C

5
6
7
8

4
3
2
1

GND

RP8
8
7
6
5

JACX
JACY
JBCX
JBCY

(+5VS)
+5V
1

GND

R18
4.7K
0603B

2 33

0603B

R22

2 33

0603B

D/MIDIIN 18
D/MIDIOUT 18
C31
220P
0603B

R23

C32
220P
0603B

MIDIIN
MIDIOUT

GND
MITAC INTERNATIONAL CORP.
Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

13
8

of

24

+5V
JP4
2

1
JP
0603B_DFS

C122
2

1
2
2

JP
<1st Part Field>

2
4.7K
0603B

4.7K
0603B
C530
1U
0603B

L3 1
L5191

AUX/L
AUX/R
LINE/OUT/L

GND

LINE/OUT/R

C93 0.1U
390P 0603B
0603B

40
43
44
45
46
47
48

GND

NC/FILT_R
ALT_LINE_OUT_L
NC/RX3D
ALT_LINE_OUT_R

0603B

CDROM_L

20

C536

1 0.22U

0603B

CDROM_R

19

C73

1 0.22U

0603B

16

C539

2 0.1U

0603B

17

C538

2 0.1U

0603B

14

C541

2 0.1U

0603B

15

C540

2 0.1U

0603B

1
C529
100P
0603B

BEAD_600Z/100M
0603B

CONN_SMKLGY2313
PHONE-JACK-LGY2313_0
CAGND
L28
BEAD_600Z/100M
0603B

CDROM_GND

35

AOUT_L 15

36

AOUT_R 15

13

C80

2 0.1U

0603B

37

C44

2 0.1U

0603B

R45
C542
0.01U
0603B

MODEM_MIC 21

39

C531

2 0.1U

0603B

41

C537

2 0.1U

0603B

29

C46

30

C45

D/LINE_OUT_L 18

1
R530
10K
0603B

AFLT1
AFLT2
REFFLT

2 1U

0603B

2 1U

0603B

VREFOUT

27
28

C48
0.1U
0603B

C49
0.1U
0603B

MODEMSPK 21

6.8K 1%
0603B

D/LINE_OUT_R 18
R40

NC
NC
NC
NC/CS0
NC/CS1
NC/CHAIN_IN
NC/CHANI_CLK

0
0603

CDROM_R

CDROM_RIGHT 7

CDROM_L

CDROM_LEFT 7

C43
2.2U
1206

R44

CS4297_48
PQFP48_0.5MM

R43

R39

100K
0603

100K
0603

0603B

NC/CX3D

GND1

6 SPKR

1 0.22U

34

0603B

1 0.22U

33

2 0.1U

C526 0.1U 2

C76

C532 0.1U 2

C535

18

0603
0

32

AGND2

MONO/OUT

AGND1

11

C533 0.1U 2

NC/FILT_L

42

31

26

2
0.1U
0603B

C
Q7
EMMBT3904L
MMBT3904L-SOT23

C95

C534 0.1U 2

GND2

R49
10K
0603B C94
1
2

R50
10K
0603B
11 CARDSPK#

PHONE

GND

(+3VS)
+3V

(+3VS)
+3V

C69

22

J502

PC/BEEP

C99
22P
0603B

XTL/OUT
VIDEO/R

C91
22P
0603B

12
3
2
4 24.576MHZ
24.576M-TXC7X5

21

0603B
X1

3
5
4
2
1

L504

1M
1

VIDEO/L

LINE_IN/R

CD/R
CD/GND

XTL/IN

LINE_IN/L

0603B

2
R48

0603B

2 0.1U

CDROM_GND
GNDGND

R536 1
AGND
LINE_IN/R

CDROM_GND 7
2
0_NA
0603

L13

R29

2 6.8K 1%

0603B

R32

2 6.8K 1%

0603B

D/LINE_IN_R

18

D/LINE_IN_L 18

LINE_IN/L

+
MIC_WM034B
MICROPHONE-WM034BY

CS4297

1
2

C17
47P_NA
0603B

CD/L

MIC1
0603B
0603B

MIC2

2 0.1U

MIC1

C53

RESET#
SDATA/OUT
SDATA/IN
SYNC
BIT/CLK

C61

24

11
5
8
10
6

13 ARST#
13 ASDOUT
13 ASDIN
13 ASYNC
13 ABITCLK

23

LINE/IN/L

273000130006
2 BEAD_600Z/100M
2 BEAD_600Z/100M

U9

LINE/IN/R

R35

2
25

38
AVDD2

AVDD1

VDD2

VDD1

GND

+5V
JP5

GND

1
C525
0.1U
0603B

1
JP
<1st Part Field>

C152
1U_NA
0603B

330K_NA
0603B

1
2

C527
0.1U
0603B

1
2

1
2

1
2

C545
0.1U
0603B

8
7
6
5

ADP3301AR-5_NA
SO8

R529
C544
0.1U
0603B

IN0
IN1
ERR
SD

R75
2

C543
10U
1206

JP6

OUT0
OUT1
NR
GND

GND

L520
BEAD_120Z/100M
0805C

1
2
3
4

C121
10U 16V
1210

2
L521
0
0805C

U15

(+3VS)
+3V

+12V

0.01U_NA
0603B

VA

1
A

2
R528
10K
0603B

BEAD_120Z/100M
0805C

R526
10K
0603B

GND
AGND

R226
1

2
0_NA
0805C
GND

AGND

R509

2
0_NA
0805C
GND

AGND

MITAC INTERNATIONAL CORP.


Title
6120W/N- MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

14
8

of

24

1
C508
1
2

R511
1

1U
0603B

2
10K
0603B

C509
2

5P_NA
0603B
R512
2
15K
0603B

14 AOUT_R

AOUT_R

C528
2

1
C511
1
2

2.2U
1206

R513
1

0.1U
0603B

C512
2

5P_NA
0603B
R514
1
2

2
10K
0603B

33K
0603B

VR1
10K
8
7
3

14 AOUT_L

AOUT_L

C524
2
2.2U
1206
1
C518
1
2

R522
1

0.1U
0603B

2
10K
0603B

C519
2

5P_NA
0603B
R519
2

33K
0603B

1
C522
1
2

R523
1

1U
0603B

C523
2
(+5VS)
+5V

5P_NA
0603B
R524
1
2

2
10K
0603B

15K
0603B

L516
BEAD_120Z/100M
0805C

2
30
31
32
33
34

BAV70LT1

R230
100K
0603B

NC0
NC1
NC2

1
12
13
24

C521
0.1U
0603B

C21
100U 16V
CPWX6.6
C

2
17
23

SHUTDOWN
G6
G7
G8
G9
G10

C520
0.1U
0603B

GND0
GND1
GND2
GND3

SE/BTL#
HP/LINE#
MUTE IN
MUTE OUT

LOUT+ 21
LOUT- 21

18
7

G1
G2
G3
G4
G5

25
26
27
28
29

C12
100U 16V
CPWX6.6

C25
100U 16V
CPWX6.6

TPA0202_GND
TSSOP24_TPA0102

1
GND

L BYPASS
R BYPASS

ROUT+ 21
ROUT- 21

3
10

RVDD
LVDD

22
15

L OUT+
L OUT-

18 D/HP_IN

14
16
11
9

C513
0.1U
0603B

LLINE IN
LHP IN

R OUT+
R OUT-

6 SPK_OFF

C517
1U
0603B

0_NA
0603
D27

6
19
C516
1U
0603B

R231
1

RLINE IN
RHP IN

4
5

21
20

U3

R515
100K
0603B
BEAD_600Z/100M
L502 1
2 0603B

R517
VA 1

2
BEAD_600Z/100M
L503 1
2 0603B

C503
100P
0603B

C504
100P
0603B

L501BEAD_600Z/100M
1
2 0603B

CONN_SMKLGY2313
PHONE-JACK-LGY2313_0

R15
1K
0603B

1
R1
1K
0603B

J501
3
5
4
2
1

100K
0603B

CAGND

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

15
8

of

24

HP

FIR MODULE HSDL-3600#007

+3VS_FIR

SUPER I/O

(+3VS)
+3V
1

CFG0=LOW (DEFAULT):

16 BIT ADDRESS DECODE

CFG1=HIGH (10K PULL-HIGH):

5 IO_48MHZ

11-BIT ADDRESS/COM2
1

1
2
3
4
5
6
7
8
9
10

R501 4.7 1206

RDATA# 7
WDATA# 7
WGATE# 7
HDSEL# 7
DIR# 7
STEP# 7
TRK0# 7
INDEX# 7
DSKCHG 7
WPROT# 7
MTR0# 7

JP_NET
JP_SMT4_DFS

R503
4.7K_NA

FIR_GND

2
CFG0

+5V
26

RLS4148

GND

P_STB#

D1

U1

D/SLIN#

28

D/AFD#

P_LPD2

27

D/ERR#

P_LPD4
P_LPD5

D/SLIN#
P_LPD3

26

P_LPD7

D/LPD6

25

P_LPD6

24

P_LPD5

D/LPD5

5
23

P_LPD4

D/LPD4

22
D/LPD3

21

D/SLCT

20

D/LPD2

19

P_LPD3

P_LPD2

10

D/LPD1

11

D/BUSY

12

D/LPD0

13

D/STB#

14

(+3VS)
+3V

C288
0.1U
0603B

18

P_LPD1

17

P_LPD0

D/SLCT

16

P_STB#

15

D/ACK#

PIO
7536S-25G2T
SUYIN

27
C330
10P_NA
0603B
PIO_GND

L26

PACS1284-02Q/T
QSOP28

PIO_PNF#
COM1RI#
COM1DSR#

BEAD_120Z/100M
0805C
PIO_GND

RP10KX4
RPSOA_8

L27

1
C

GND

BEAD_120Z/100M
0805C

GND

MDC

+3V
1

+3V

D/PE

PIO_GND

PIO_GND

+3V

D/BUSY
C332
10P_NA
0603B

J506

C271
0.1U
0603B

P_LPD7

C333
10P_NA
0603B

RP67
1
2
3
4

P_LPD6

D/ACK#

D/PE

8
7
6
5

C331
10P_NA
0603B

D/LPD7

D/LPD0 18
D/LPD1 18
D/LPD2 18
D/LPD3 18
D/LPD4 18
D/LPD5 18
D/LPD6 18
D/LPD7 18
D/SLIN# 18
D/STB# 18
D/AFD# 18
D/INIT# 18
D/ACK# 18
D/ERR# 18
D/SLCT 18
D/PE 18
D/BUSY 18

D/INIT#

D/LPD0
D/LPD1
D/LPD2
D/LPD3
D/LPD4
D/LPD5
D/LPD6
D/LPD7
D/SLIN#
D/STB#
D/AFD#
D/INIT#
D/ACK#
D/ERR#
D/SLCT
D/PE
D/BUSY

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

D/AFD#
P_LPD0
D/ERR#
P_LPD1

DRV0# 7

D/INIT#
92
91
90
89
87
86
85
84
79
93
76
78
83
77
80
81
82

GND

0603B

CS0#/SIRQI2
DRV2#/SIRQI3
TC
DACK0#
DACK1#
DACK2#
DRQ0
DRQ1
DRQ2

33
37
36
32
39
38
35
45
30
34
44
41
42
43
46
50

PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
SLIN#/STEP#
STB#/WRITE#
AFD#/DSTRB#
INIT#/DIR#
ACK#/DR1#
ERR#/HDSEL#
SLCT/WGATE#
PE/WDATA#
BUSY/WAIT#

RD#
WR#
IOCHRDY
CS1#/ZWS#
IRQ3
IRQ4
IRQ5/ADRATE0
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12/DSR2#
IRQ15/SIRQI1

VDDB
VSSB

GND1
HSDL-3600
FIR_HSDL3600_007
JL507

IRRXA

irtx

11
FIR_GND

D0
D1
D2
D3
D4
D5
D6
D7

48
40

(+3VS)
+3V

49
47
4
53
52
3
54
31
2

PIO_PNF#

6 TC
6 DACK0#
6 DACK1#
6 DACK2#
6,19 DREQ0
6,19 DREQ1
6,19 DREQ2

IRRXA
1

R502 4.7 1206

VCC
AGND
FIR_SEL
MD0
MD1
NC
GND
RXD
TXD
LEDA

IRMODE

6,19 DREQ3

COM1RXD
COM1TXD
COM1RTS#
COM1DTR#
COM1CTS#
COM1DSR#
COM1DCD#
COM1RI#

VSSE

17
16
51
1
99
98
96
95
94
55
56
57
66
58

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
TRK0#
INDEX#
DSKCHG#
WP#
MTR0#
MTR1#/IDLE
DR0#
DR1#/PD
DENSEL/ADRATE1
DRATE0/MSEN0

VSSD

15
14
13
12
11
10
9
8

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11/R12#
A12/DTR2#
A13/CTS2#
A14/RTS2#
A15/DCD2#

73
71
72
69
70
74
75
68
6
65
63

59

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

MR
AEN

88

28
27
26
25
24
23
22
21
20
19
29
60
61
62
64
67

SIN1
BOUT1/SOUT1
RTS1#/BADDR0
DTR1#
CTS1#
DSR1#
DCD1#
RI1#
IRSL1
SIN2/IRRX1
BOUT2/SOUT2

VDDC
VSSC

SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SD[0..7]

6 DACK3#

0.47U
0805

IRMODE
IRMD0
IRMD1

6 IRMD0
6 IRMD1

X1(CLKIN)

97
7

5
100
18

SA[0..15] 6,17 AEN

6,17,19 IOR#
6,17,19 IOW#
6,17,19 IOCHRDY
6,19 ZEROWS#
6,19 IRQ3
6,19 IRQ4
6,19 IRQ5
6,19 IRQ6
6,19 IRQ7
6,19 IRQ9
6,19 IRQ10
6,19 IRQ11

C501
2

JP_NET
JP_SMT4_DFS
U501

6 RSTDRV

6,17,19 SD[0..7]

1206

FIR_GND
U29
PC93338VJG
PQFP100_0.5MM

GND

6,17 SA[0..15]

+3VS_FIR
JL506

10U

+3VS_FIR

C5
33P
0603
25V

C502
2

+3V

6
24

2
4

COM1RTS#
COM1TXD
COM1DTR#

7
8
9

COM1DCD#
COM1DSR#
COM1RXD
COM1CTS#
COM1RI#

10
11
12
13
14

+3V

R7
100K
0603B

V-

1
GND
25

C2+
C2-

T1OUT
T2OUT
T3OUT

T1IN
T2IN
T3IN

R1IN
R2IN
R3IN
R4IN
R5IN

R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
SD
EN/

C3+

C3-

22
21
20

D_RTS#
D_TXD
D_DTR#

GND
19
18
17
16
15
28

D_DCD#
D_DSR#
D_RXD
D_CTS#
D_RI#
1

26

C13
0.1U
0603B

JL504
FA2
D_RI#
D_DTR#
D_CTS#
D_TXD

120OHM/100MHZ
RPSOA_8C
8
7
6
5

1
2
3
4

8
7
6
5

1
2
3
4

J507
5
9
4
8
3
7
2
6
1

FA3
D_RTS#
D_RXD
D_DSR#
D_DCD#
2

C18
0.1U
0603B

120OHM/100MHZ
RPSOA_8C

ADM3311ARU
TSSOP_SSOP28
4
3
2
1

Q1
DTC144WK
SOT23AN_1

V+

C1-

27

23
5

C1+

C23
0.1U
0603B

JP_NET
JL505
10
11

JP_SMT4_DFS

JP_NET

JP_SMT4_DFS

SIO_GND

GND

SIO_GND
9P/2.775MM-MA
SUYIN
7534P-09G2-05

5
6
7
8

D3

CA504

CA503

100PX4
RPSOA_8C

100PX4
RPSOA_8C

4
3
2
1

R6
100K
0603B

C14
0.1U
0603B

+3V

RLS4148

6 RS232_OFF#

D/RI# 18
D/DTR# 18
D/CTS# 18
D/TXD 18
D/RTS# 18
D/RXD 18
D/DSR# 18
D/DCD# 18

C20
0.1U
0603B

5
6
7
8

CARD_RI# 11

0.1U
0603B

C19
0.1U
0603B

U2
2

C11

BAW56
SOT23N

VCC

Q2
DTC144WK
SOT23AN_1

MODEM_RI# 21

GND

D2

pull high
17 RI#

R5
100K
0603B
2

R4
100K
0603B

MITAC INTERNATIONAL CORP.


GND

Title

RS232/SIO
1

6120W/N - MOTHER BD

SIO_GND
Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02

GND
2

Sheet

16
8

of

24

U37

CL-190G LED_CL190
1 270 0603 D8 A
K

18 AC_POWER#
18 BATT_POWER#
18 BATT_R#
18 BATT_G#
TP1
E-mail

CL-190G LED_CL190

1
2
3
4
5

1
BLADJ

18 BLADJ

K/M_DATA
M_DATA

TP505
TP506
reserved
+5V

10K*8_NA
1206

21 VADJ_1
21 VADJ_2
21 CHARGING
19 TRIS
20 VDD5_SW

R300
1

2
1

21,24 PWR_ON

1
1

C344
10P
0603

TP/T_DATA 21
TP/T_CLK 21

4.7K
0603

R248
47K
0603

VADJ_1
VADJ_2
CHARGING
TRIS
ENV1
ENV0

99
100
101
102
103
104

M_DATA
K/M_DATA

57
59

M_CLK
K/M_CLK

58
60

10K

0603
TP/T_DATA
TP/T_CLK
0603

10K

+5V

95
96
97
98

GND
VDD5

GND
VCC_ECRTC

2 10K_NA 0603
2 10K_NA 0603

VDD5

ENV1
ENV0

R253 1

2 10K 0603

R302 1
R249 1

VDD5

C345
0.1U
0603
16V

19 ROM_CS#
19 ROM_WR#

HMR
EC_PWROK

164
165

VBAT
EC_PFAIL
EC_AVREF
ROM_CS#
ROM_WR#

28
79
80
105
112

VCC

RESET#

HMR

PC0
PC1
PC2
PC3/EXINT0
PC4/EXINT11
PC5/EXINT15
PC7/PSDAT3
PC6/PSCLK3

PSDAT1
PSDAT2

PG4WR1
PG3/SEL1
PG2/CLK
PG0/SELIO

PSCLK1
PSCLK2
HMR
HPWRON
VBAT
PFAIL
VREF
SEL0/HRMS
WR0

IRQ12
IRQ11
IRQ8
IRQ1
HIOR
HIOW

THRM_CLK 20

SD[0..7]

SD[0..7] 6,16,19

+3V

+3V
1

+5V

BIOSCS#
MEMR#
MEMW#

G
S

R400
10K
0603

R288
10K
0603

EC_ECSMI#

A
RLS4148

EXTSMI# 6,19

D29
EC_WAKE_UP# K
AEN 6,16
ROM_RD# 19
IOCHRDY 6,16,19

A
RLS4148

WAKEUP# 6,19

D31
VCMOS

VDD5

EC_A20GATE

A
RLS4148

A20GATE 6

U7

+5V

VCC

6,20 PWROK

EC_PWROK
2

4
2

GND

L526

AHCT1G08DBV
SOT25

BEAD_120Z/100M
0805C

GND

R531
470K
0603

BIOSCS# 6
MEMR# 6,19
MEMW# 6,19

71
72
73
74
75
76
77
78

RI#
BAT_CLK R297 1
BAT_DATA R298 1
FAN_ON#
ADEN#
EC_A20GATE
EC_RCIN#
POWERBTN

61
62
63
64
65
68
69
70

EC_WAKE_UP#
EC_THRM#
EC_ECSMI#
BATT_DEAD#
EC_PME#
SUSC#
TP/T_DATA
TP/T_CLK

113
106
107
110

KBD_JP/US#
SUSA#
COVER_SW#

153
154
155
156

EC_IRQ12
EC_SCI#
EC_IRQ8#
EC_IRQ1

158
159

IOR#
IOW#

VTTL

D28
2

157
162
163

D
S

KO15
KO14
KO13
KO12
KO11
KO10
KO9
KO8
KO7
KO6
KO5
KO4
KO3
KO2
KO1
KO0

D
Q46
2N7002

THRM# 6,19
PME# 20
RCIN# 6,19
THRM_DATA 20

1
2

1
2

1
2

1
2
43
44
45
46
87
88
89
90
131

91
AVCC

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

23
67
108
161
VCC0
VCC1
VCC2
VCC3

PH5/ISE
PH4/PLI
PH3/PFS
PH2/BST2/TRIS
PH1/BST1/ENV1
PH0/BST0/ENV0

37
38
39
40
41
42
47
48
49
50
51
52
53
54
55
56

D
Q45
2N7002

VDD5
R281 1

2 1K 0603

RI# 16
2 10K_NA 0603
2 10K_NA 0603
VDD5

Q502
SI2301DS
SOT23_FET

ADEN# 20,21
R518

+5V
R301
10K_NA
0603

SUSC# 6

SW1

C515
1000P
0603B

R275
47K
0603

R299

2 2
6

1
5

1K
0603B
SMT-1-01
SW_FJKSMT1_01

1
2
3

2
10K
0603

GND

ST/MA-3
CONN_DF13V_3

GND

L525
BEAD_120Z/100M
0805C

R276
1
R277
SUSA# 5,6,8,18,20,23,24
1
R250 1
R251 1
R252 1
R254 1

J511

2 0 0603
2 0 0603
2 0 0603
2 0 0603

2 0_NA 0603

KBD_US/JP# 6,19

2 0

LID# 18,19

0603

GND

IRQ12 6,19
SCI# 6,19
IRQ8# 6
IRQ1 6,19

IOR# 6,16,19
IOW# 6,16,19

GND

R280
47K
0603

GND

SOT23

ECGND
BATT_DEAD#

GND

GND

EC_VDDA

GND

PB0/RING
PB1/SCL
PB2/SDA
PB3/TA
PB4/TB/EXINT10
PB5(GA20)
HRSTO(PB6)
PB7/SWIN

DA0
DA1
DA2
DA3

PC87570
PQFP176A

U35
ADM809_NA

PA0/HMEMCS
PA1/HMEMRD
PA2/HMEMWR

AEN
ROM_RD#
IOCHRDY

BAT_CLK

8
7
6
5

R11

13
111
14

1
2
3
4

EC_THRM#
EC_PME#
EC_RCIN#
BAT_DATA

D9 A

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

CL-190G LED_CL190
1 270 0603 D7 A
K

15
16
17
18
19
20
21
22

C359
0.1U_NA
0603
50V

GND
RP97
0*4
1206

1 270 0603

KBSOUT15
KBSOUT14
KBSOUT13
KBSOUT12
KBSOUT11
KBSOUT10
KBSOUT9
KBSOUT8
KBSOUT7
KBSOUT6
KBSOUT5
KBSOUT4
KBSOUT3
KBSOUT2
KBSOUT1
KBSOUT0

D0
D1
D2
D3
D4
D5
D6
D7
PF0/D8
PF1/D9
PF2/D10
PF3/D11
PF4/D12
PF5/D13
PF6/D14
PF7/D15

VDD5
24
12

VCC
GND

R10

137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152

EC_THRM#
EC_PME#
BAT_CLK
BAT_DATA
EC_RCIN#

EC_A20GATE

ROM_SD0
ROM_SD1
ROM_SD2
ROM_SD3
ROM_SD4
ROM_SD5
ROM_SD6
ROM_SD7
SCROLL_LOCK#
NUM_LOCK#
CAP_LOCK#
AC_POWER#
BATT_POWER#
BATT_R#
BATT_G#

KBSIN7
KBSIN6
KBSIN5
KBSIN4
KBSIN3
KBSIN2
KBSIN1
KBSIN0

1OE#
2OE#

15
16
19
20
23

SA[0..18] 6,16,19

ROM_SD[0..7]

HAEN
RD/HDEN
HIOCHRDY

SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18

R12

29
30
31
32
33
34
35
36

PD0/AD0
PD1/AD1
PD2/AD2
PD3/AD3
PD4/AD4
PD5/AD5
PD6/AD6
PD7/AD7

2B1
2B2
2B3
2B4
2B5

C343
33P
0603
25V

81
82
83
84
85
86
93
94

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7

32KX1/32CLKIN
32KX2

166
167
168
169
170
171
172
173
174
3
4
5
6
7
8
9
10
11
12

1
KI7
KI6
KI5
KI4
KI3
KI2
KI1
KI0

RP91

2
2

1
13

2A1
2A2
2A3
2A4
2A5

74CBTD3384_NA
TSSOP24
SA[0..18]
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
PA3/HA16
PA4/HA17
PE0/HA18

ADC0_V5
ADC1_V3
ADC2_VCORE
ADC3_V2.5
BAT_VOLT
BAT_TEMP
2 0 0603

GND

PS/2 PORT PUL HIGH

R401
1
1
R402

ECGND

R650 1
TP503
Reserve for 2nd battery

2
1 RI#
2 BATT_DEAD#
3
4
5
VDD5

47K*8
1206

0603
0603
0603

21,22 BAT_TYPE

32.768KHZ

C342
10P
0603

VDD5

2 22
2 22
2 22

+3V

M_CLK
K/M_CLK

14
17
18
21
22

6,19 THRM#
20 PME#
20 THRM_DATA
20 THRM_CLK
6,19 RCIN#

1B1
1B2
1B3
1B4
1B5

+3V
R260 VCC_CORE
120K VTT
0603

R294 1
R295 1
R296 1

25
27

NC11
NC12
NC13
NC14
NC15

32KX1
32KX2

X6

10
9
8
7
6

R287
100K_NA
0603

1A1
1A2
1A3
1A4
1A5

132
133
134
175
176

GND

R293

KI0
KI1
KI2
KI3

RP90

+5V

ECGND

PC87570

AGND

KBD_US/JP# 6,19

C341
0.1U
0603
16V

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13/BE0
A14/BE1
PG1/A15/CBRD
PA5/A16
PA6/A17
PE1/A18/SHBM

92

R290
200K
0603

114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
135
136

GND0
GND1
GND2
GND3
GND4

2
11

100K
0603

20M
0603

10
9
8
7
6

ECGND

U34
ROM_SA0
ROM_SA1
ROM_SA2
ROM_SA3
ROM_SA4
ROM_SA5
ROM_SA6
ROM_SA7
ROM_SA8
ROM_SA9
ROM_SA10
ROM_SA11
ROM_SA12
ROM_SA13
ROM_SA14
ROM_SA15
ROM_SA16
ROM_SA17
ROM_SA18

R289

19 ROM_SD[0..7]

EC_PME#
ADEN#

0
0603

ECGND

+5V

GND

VDD5

GND

ROM_SA[0..18]

19 ROM_SA[0..18]

RP49
0*8
RPX8

47K*8_NA
1206

6 A20GATE

1
GND

24
26
66
109
160

RP48
0*8
RPX8

RP89
1
2
3
4
5

C340
0.1U_NA
0603
25V
20%

120Z/100M
2012

EC_AVREF

ECGND

GND

10
9
8
7
6

C339
0.1U
0603
25V
20%

20 VDD5_SW#

KI4
KI5
KI6
KI7

GND

JP_BEAD_DFS

GND

GND

VDD5

C338
0.22U
0603
16V

R206
0
0603

FPC/FFC/1MM/26P
ELCO-6200-26

C337
0.1U
0603
25V
20%

RP47
0*8
RPX8

C336
0.1U
0603
25V
20%

6,19 EXTSMI#
6,19 WAKEUP#

R286

L30

D
S

KO15
KO14
KO13
KO12
KO11
KO10
KO9
KO8
KO7
KO6
KO5
KO4
KO3
KO2
KO1
KI7
KI6
KI5
KI4
KI3
KI2
KI1
KI0
KO0
KBD_US/JP#

16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
2

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8

C335
0.1U
0603
25V
20%

2012

L31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

EC_VDDA
1

120Z/100M
J5

VDD5

EC_ECSMI#
EC_WAKE_UP#

EC_VDDA

L29
1

2
5
6
9
10

D
S

VDD5

3
4
7
8
11

Q44
MMBT3904L
B

BATT_DEAD 22

SOT23
D30

L2

BAV70LT1

C1
1000P
0603B

GND
BAT_VOLT
BAT_TEMP
BAT_CLK
BAT_DATA

2
1
2
3
4

KBD_GND

J503

8
7
6
5
120OHM/100MHZ
RPSOA_8C

1
2
3
4
5
6

1
2
3
4
5
6

K/M DATA
M DATA
K/M CLK
M CLK

KB / PS2

4
3
2
1

18 K/M_DATA
18 M_DATA
18 K/M_CLK
18 M_CLK

GND1
GND2
GND3
GND4

CA1
100PX4
RPSOA_8C

8
7
6
5

FA1

GND1
GND2
GND3
GND4

C346
0.1U
0603
25V
20%
ECGND

C347
0.1U
0603
25V
20%

RP92

1
2
3
4

BAT_V
BAT_T
BAT_C
BAT_D

21
21
21
21

22*4
1206

ECGND

CONN_FXCMH1176

MITAC INTERNATIONAL CORP.


Title

JL501

6120W/N - MOTHER BD

5
6
7
8

BEAD_120Z/100M
MINISMDC110-2
POLYSW_MINISMDC110 0805C

+5V

F2

KBD_GND
A

JP_NET
JP_SMT4_DFS

GND
C

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet
E

17

of

24

FA4
8
7
6
5

USB CONNECTOR

1
2
3
4
J1

L7
8 ENABKL_VGA

1 1K

1
2
3
4
5
6
7
8
9
10

0603B

17,19 LID#

FA5
AC_POWER#
BATT_PWR/F#
BATT_G#
BATT_R#

17 AC_POWER#
C51
BATT_PWR/F#
0.1U
17 BATT_G#
0603B
17 BATT_R#

R19

C15
1000P
0603B

C34
220P
0603B

BEAD_120Z/100M
0805C

C16
10U
1206
16V

120OHM/100MHZ
RPSOA_8D

BEAD_120Z/100M
0805C
C35
C52
220P
0.01U
0603B
0603B

8
7
6
5

1
2
3
4

HIROSE
ST/MA-10
DF13-10P-1.25V

17 BLADJ

1
R219
470K
0603

VMAIN

MINISMDC110-2
POLYSW_MINISMDC110

D/USB_PWR0

L4

F3
+5V

8
7
6
5

USB_GND
GND

L5
1

VDD5S

CA3
47PX4
RPSOA_8C

BEAD_120Z/100M
0805C

GND

U10B

1M
0603B

R225
15K
0603B

U10C

74AHC14_V
TSSOP14

74AHC14_V
TSSOP14

USB_GND

GND

C66
4.7U
1206
R24

GND
2

GND

1
GND

D
S

Q6
2N7002

R68
0_NA
0603

Q5
2N7002

D
S

L20
1

1
U10A
1

R182
15K
0603B

BATT_PWR/F#

R25

120Z/100M
2012

1
C263
47P
0603B

+3V

1
2

UB5112C-S1

L19
120Z/100M
2012

+3V

GND1
GND2

SUSA# 5,6,8,17,20,23,24

27
0603B

+3V

GND

GND1
GND2

14

74AHC14_V
TSSOP14

D/USBP0+

GND

1
2
3
4

6 USBP0+

J504
1
2
3
4

2
0805C
0
L514

14

D/USBP0-

2
27
0603B
R175

14

R176
1

6 USBP0-

C30
1000P
0603B

0805C
0
L513

1
2
3
4

R242
560K
0603

GND

C262
47P
0603B

120OHM/100MHZ
RPSOA_8D

GND

6 USB_OC0#

BATT_POWER#

GND

BATT_POWER# 17

2
180K
0603B

R168
1

6 USBP1-

D/USB_PWR1

6 USBP1+
1

R152
15K
0603B

R155
15K
0603B

C249
47P
0603B

1
1

GND
R243
560K
0603

D/USBP1+

27
0603B
C250
47P
0603B

C310
100U 16V
CPWX6.6

6 USB_OC1#

1
+

R218
470K
0603

D/USBP1-

2
27
0603B
R156

2
1

MINISMDC110-2
POLYSW_MINISMDC110

F4
+5V

GND

GND

CLR

CLK

L
H
H
H
H

X
L
^
^
^

A B

QA

QB

L
QA
H
L
L

L
QB
QAn
QAn
QAn

QC ... QH

GND

PORT REPLICATOR CONN.

X
X
H
L
X

X
X
H
X
L

L ... L
QC ... QH
QBn...QGn
QBn...QGn
QBn...QGn

FA503
1
2
3
4

16 D/CTS#

VDD5

16 D/AFD#

16 D/TXD
16 D/SLIN#
R520
470K_NA
0603B

16 D/RTS#

+3V

16 D/LPD6

16 D/RXD

Q501

6,19 DOCK_IN

16 D/LPD4
16 D/DSR#

R510
100K
0603B

MMBT3904L_NA

16 D/LPD2
16 D/DCD#
16 D/LPD0

C
DOCK_IN#

B
E

9 D/BLUE
9 D/DDDA
9 D/DDCK
9 D/GREEN

GND
9 D/VSYNC
9 D/RED
9 D/HSYNC

D/USB_PWR1

D/USB_PWR0

GND1
FA502
D/USBP0+
D/USBP0D/USBP1+
D/USBP1-

1
2
3
4

8
7
6
5

D_USBP0+
D_USBP0D_USBP1+
D_USBP1-

GND1

GND2

120OHM/100MHZ
RPSOA_8D

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

D/LINE_OUT_R 14
D/LINE_IN_R 14

D/LINE_IN_L 14
D/LINE_OUT_L 14
D/ACK# 16
K/M_CLK 17

4
3
2
1

16 D/DTR#
16 D/ERR#

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

D/BUSY 16
K/M_DATA 17

CA506
100PX4
RPSOA_8C

D/SLCT 16
M_CLK 17
D/INIT# 16
M_DATA 17
D/LPD7 16

5
6
7
8

16 D/PE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

D/LPD5 16
+5V

4
3
2
1

16 D/RI#

D/LPD3 16
CA505
100PX4
RPSOA_8C

D/LPD1 16
D/CRT_IN# 9
D/MIDIOUT 13

5
6
7
8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

16 D/STB#

8
7
6
5

D/MIDIIN 13
D/JAB2 13
D/JBB2 13
D/JAB1 13
D/JBB1 13
D/JACY 13
D/JBCY 13
D/JACX 13
D/JBCX 13
D/HP_IN 15

GND

D/LUMA 9
D

D/CRMA 9

GND2
J508

BERG-90784-80

120OHM/100MHZ
RPSOA_8D

MITAC INTERNATIONAL CORP.


GND

GND

Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

18
8

of

24

ISA PULL HIGH

PCI PULL HIGH

SYSTEM BIOS
SD[0..15]

SD[0..15] 6,16,17

RP55
(+3VS)
DEVSEL#
STOP#
PCILOCK#
TRDY#

+3V
3,6,11,13,21 DEVSEL#
3,6,11,13,21 STOP#
3 PCILOCK#
3,6,11,13,21 TRDY#

10
9
8
7
6

1
2
3
4
5

(+3VS)
SD3
SD2
SD1
SD0

+3V

+3V

10
9
8
7
6

SD4
SD5
SD6
SD7
(+3VS)

1
2
3
4
5

RP10KX8
RPSOE_10

17 ROM_SD[0..7]

RP76

P_GNT2# 3,21
P_GNT1# 3,13
IRDY# 3,6,11,13,21
PHOLD# 3,6

audio
IRDY#
PHOLD#
(+3VS)

ROM_SD[0..7]

ROM_SA[0..18]

+3V

RP4.7KX8
RPSOE_10

13
14
15
17
18
19
20
21

O0
O1
O2
O3
O4
O5
O6
O7

R279
ROM_SA18

0
1
2
3
4
5

PIRQA#
PIRQB#
PIRQC#
PIRQD#

(+3VS)

6,8,11
6,11,21
6,13
6

RP58
(+3VS)
SD12
SD13
SD14
SD15

+3V

+3V

RP10KX8
RPSOE_10

10
9
8
7
6

SD8
SD9
SD10
SD11
(+3VS)

1
2
3
4
5

32

(+3VS)
PHLDA#
card bus
modem

10
9
8
7
6

C349
0.1U
0603
25V
20%

+3V
2

16

card bus
audio
FRAME#

1
2
3
4
5

P_REQ0# 3,6,11
P_REQ1# 3,6,13
FRAME# 3,6,11,13,21
P_GNT3# 3

(+3VS)

VCC

VSS

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE#
OE#
WE#

ROM_SA0
ROM_SA1
ROM_SA2
ROM_SA3
ROM_SA4
ROM_SA5
ROM_SA6
ROM_SA7
ROM_SA8
ROM_SA9
ROM_SA10
ROM_SA11
ROM_SA12
ROM_SA13
ROM_SA14
ROM_SA15
ROM_SA16
ROM_SA17

12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
22
24

ROM_CS# 17
ROM_RD# 17

31

ROM_WR# 17

32P/PLCC/SMT
PLCC32

GND

RP52
+3V

VPP

VDD5

RP4.7KX8
RPSOE_10

3,6 PHLDA#
3,11 P_GNT0#
3,6,21 P_REQ2#
3 P_REQ3#

0603

3,6,11,21 CLKRUN#
3,6,11,13,21 SERR#
11,13,21 PERR#

10
9
8
7
6

2 ROMSA18

RP64
(+3VS)
CLKRUN#
SERR#
PERR#

+3V

ROM_SA[0..18] 17

U36
ROM_SD0
ROM_SD1
ROM_SD2
ROM_SD3
ROM_SD4
ROM_SD5
ROM_SD6
ROM_SD7

RP54
+3V
6 IOCS16#

+3V

(+3VS)
IOCS16#

RP10KX8
RPSOE_10

10
9
8
7
6

1
2
3
4
5

MEMR# 6,17
MEMW# 6,17
IOR# 6,16,17
IOW# 6,16,17
+3V
Shared Flash ROM Pull Highs

RP4.7KX8
RPSOE_10

SBHE#
RCIN#

6 SBHE#
6,17 RCIN#

MEMR#
MEMW#
IOR#
IOW#
(+3VS)

ROM_SD[0..7]

input pin pull high

ROM_SD[0..7] 17

GPIN PULL HIGH


RP71
B

+3V
6,16 IRQ10
6,16 IRQ7
6,16 IRQ6
6,16 IRQ5

RP53
+3V
gpi1

6,17 SCI#

gpi12

6,17 WAKEUP#

10
9
8
7
6

1
2
3
4
5

PIIX4_TEST# 6
PWRBTN# 6
EXTSMI# 6,17
LID# 17,18

(+3VS)
IRQ10
IRQ7
IRQ6
IRQ5

RP93

10
9
8
7
6

1
2
3
4
5

IRQ1
IRQ9
IRQ3
IRQ4
(+3VS)

IRQ1
IRQ9
IRQ3
IRQ4
+3V

VDD5

6,17
6,16
6,16
6,16

10
9
8
7
6

ROM_SD4
ROM_SD5
ROM_SD6
ROM_SD7

RP10KX8
RPSOE_10

+3V

1
2
3
4
5

ROM_SD0
ROM_SD1
ROM_SD2
ROM_SD3

VDD5

10K*8
1206

(+3VS)
+3V

RP10KX8
RPSOE_10

ROM_SA[0..18]

RP56
8
7
6
5

RP57
+3V
6,11 SERIRQ
6,17 THRM#
6,8 VGA_REQ#
6,11 CARD_ACT

(+3VS)
gpi7
gpi8
gpi21

10
9
8
7
6

1
2
3
4
5

gpi0
gpi15
gpi3 pc/pci audio
gpi2
(+3VS)

GPI15 6
REQB# 6
KBD_US/JP# 6,17

IRQ11
IRQ12
IRQ14
IRQ15

1
2
3
4

IRQ11
IRQ12
IRQ14
IRQ15

6,16
6,17
6,7
6,7
VDD5

RP10KX4
RPSOA_8

ROM_SA4
ROM_SA5
ROM_SA6
ROM_SA7

+3V
RP10KX8
RPSOE_10

10
9
8
7
6

RP68
pci pull high

RP75
+3V
LCD_ID0
LCD_ID1
LCD_ID2
DOCK_IN

6,9
6,9
6,9
6,18

(+3VS)
gpi13
gpi14
gpi20

10
9
8
7
6

1
2
3
4
5

DREQ5
DREQ6
DREQ7

6 DREQ5
6 DREQ6
6 DREQ7

VGA_SUS# 6,8
AGP_BUSY# 8

reqd#
(+3VS)

10
9
8
7
6

+3V

1
2
3
4
5

DREQ0
DREQ1
DREQ2
DREQ3

DREQ0
DREQ1
DREQ2
DREQ3

1
2
3
4
5

ROM_SA0
ROM_SA1
ROM_SA2
ROM_SA3

1
2
3
4
5

ROM_SA8
ROM_SA9
ROM_SA11
ROM_SA10

1
2
3
4

ROM_SA16
ROM_SA17

VDD5

10K*8_NA
1206

6,16
6,16
6,16
6,16

RP95
VDD5

ROM_SA12
ROM_SA13
ROM_SA14
ROM_SA15

RP4.7KX8
RPSOE_10

RP10KX8
RPSOE_10

10
9
8
7
6

VDD5

GND
(+3VS)
+3V

ROM_SA[0..18] 17

RP94

(+3VS)
+3V

10K*8_NA
1206

VDD5

RP81
8
7
6
5

1
2
3
4

gpi16
gpi17
gpi18
gpi5

MID0
MID1
MID2
MID3

RP59

6
6
6
6

RP96

8
7
6
5

RP100KX4
RPSOA_8

(+3VS)
+3V

1
2
3
4

IOCHRDY
MEMCS16#
REFRESH#
ZEROWS#

IOCHRDY 6,16,17
MEMCS16# 6
REFRESH# 6
ZEROWS# 6,16

8
7
6
5

6 KBCS#
6 MCCS#

10K*4_NA
1206

6 GPI10

gpi10

2
2

GND

GND

RP40

GND

10
9
8
7
6

+3V

2
R187
0
0603B

R192
0
0603B

Strap pins

AGP PULL HIGH


R245
0
0603B

H:MAB#
L:MAA(ZX)

6 MB/ID1

gpi11

6 MB/ID0

R186
0_NA
0603B

R191
0_NA
0603B
gpi9

VDD5

R244
10K_NA
0603B
2

(+3VS)
+3V

(+3VS)
+3V
1

RP1KX4
RPSOA_8

3,8
3,8
3,8
3,8

G_SBA0
G_SBA1
G_SBA2
G_SBA3

1
2
3
4
5

G_SBA4
G_SBA5
G_SBA6
G_SBA7

R255 1
R256 1
R257 1

2 10K_NA 0603 ROMSA18


2 10K_NA 0603 ROM_CS#
2 10K_NA 0603 TRIS

SHBM#
HRMS
TRIS

R258 1

2 10K

HDEN

R259 1

2 10K_NA 0603 ROM_WR#

0603 ROM_RD#

TRIS 17

3,8
3,8
3,8
3,8

+3V
RP8.2KX8
RPSOE_10

RP43
10
9
8
7
6

+3V
3,8 G_DEVSEL#
3,8 G_IRDY#
3,8 G_STOP#

1
2
3
4
5

G_FRAME# 3,8
G_TRDY# 3,8
G_ADSTBB 3,8

+3V
RP8.2KX8
RPSOE_10
JT515

PCS0# 6

MODEM_OFF# 6

RP45
10
9
8
7
6

+3V
JT509
JT521
JT34

3,8 G_RBF#
3,8 G_REQ#
3,8 G_GNT#

SA18 6,17

reqc#

G_ADSTBA 3,8
G_PIPE# 3,8
G_SBSTB 3,8

3,8 G_PAR

2
100K
0603B

MITAC INTERNATIONAL CORP.


GND

+3V

Title
6120W/N - MOTHER BD

RP8.2KX8
RPSOE_10

SA19 6

R104
1
2
3
4
5

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

19
8

of

24

VMAIN
F5
1

FUSE_1206
1A-1206
VDD5

Q30

U32

0
0603

C280
10U
1206
10V

LP2951-02BM
2

GND

VDD5SW

6
1
5
4

5VTAP
OUT
ERRGND

17 VDD5_SW

IN
SENSE
F/B
SHUTDN

D
S

8
2
7
3

R195

R181
100K
0603B

+5V
A

SI2301DS
SOT23_FET

R193
+3V
Q23

GND

VDD5_SW# 17

DTC144WK_NA

Q32
DTC144WK
SOT23AN_1

G
R154
470K
0603

GND
1

PME# 17

ADEN# 17,21

RLS4148
MLL34B

JP_NET
JP_NET15

VCC_CMOS

11 CARD_PME#

2 VDD5SW

PWROK 6,17

D500
JL27

100K
0603B

pull low at Q20

VDD5S

Q20
NDS352P
S
D

VDD5

Q22
DTC144WK
2 SOT23AN_1

+3V

GND

R135
1K
R146
0603
120_NA
0603
2

SHORT-SMT1

JP2
1
13 AUDIO_PME#

R127
1K
0603
2

VTT

J512
NOTE: This connector has NO SOLDER MASK
All terminations should be paced
less than 1" from connector

R145
240_NA 0603
2

R134 1
R128 1

PREQ# PULL UP AT CPU


R113
680
0603

VTT

GND

8
7
6
5

VCC_CMOS
RSMRST# 6

C225
0.1U
0603B

1
2
3
4

1K*4_NA
1206

RLS4148
MLL34B

RP9

RP12

R144
10K
0603B

D12
A

VCC_CMOS

K
3
VDD5

R115
150
0603

R119
330
0603

R109
R220
120_NA 330
0603
0603

GND

D10
BAV99
BAV99-SOT23

DF13-12P-1.25H_NA

PREQ# 2
PRDY# 2

+3V

JP_NET
JP_NET15

CPURST# 2,3
TCK 2
TMS 2
TDI 2
TDO 2
TRST# 2

0603
0603

ITP_PREQ#
ITP_PRDY# 1
2
R108
240_NA 0603

JL26

D16
RLS4148
MLL34B

2 47
2 47

ITP_DBRESET#
ITP_RESET#
ITP_TCK#
ITP_TMS#
ITP_TDI
ITP_TDO
ITP_TRST#

1
2
3
4
5
6
7
8
9
10
11
12

GND

1
2
3
4
5
6
7
8
9
10
11
12

JP_NET
JP_NET15

JL29
21 MODEM_PME#

1
2
3
4

VCC_ECRTC

8
7
6
5

GND

0*4
1206

VCC_RTC

+3V

D11
2
BAV70LT1

C67
1U
0603B

2
3

6 A20M#

5
6

6 IGNNE#

GND

2
1K
0603B

HDS404E_NA
GND

GND

11
10

6 INTR

14
13

6 NMI

U12
1
2
3
4

1B1
1B2

1A
2A
3A
4A

2B1
2B2

S
OE

3B1
3B2

VCC
4B1
4B2

4
7
9
12

C_A20M# 2
C_IGNNE# 2
C_INTR 2
C_NMI 2

GND

R36
1K_NA
0603
1%
2

BH-800.1K
BAT_B098

8
7
6
5

1
15
16

+5V

R37
1K_NA
0603
1%

C68
0.1U_NA
0603
50V
2

FST3257QSC_NA

CRESET# 3

3
1

SW501

1
R41

BT501

+3V
GND

PWRGDCPU 2,21

VCC

RESET#

Q34
DTC144WK
JL32
2

C157
2200P
0603
2

U27
ADM809

BXPWROK 3

2 THERMDN

1
R91
4.7K_NA
0603

3
4

5
9
13

VDD
ADD0
ADD1

D+
D-

ALERT
GND1
GND2
NC1
NC2
NC3

SDATA
SCLK
STBY

GND

2
10
6
11
12

THRM_DATA 17

14
15

ADM1021

R90
0
0603

** NEAR CPU
2

GND

R93

1
1

PWROK 6,17

TEST
TEST1

1
16

7
8

JP_NET
JP_NET10

GND

2 THERMDP
+3V

C168
0.1U
0603
50V

U19

THRM_CLK 17
2

SUSA# 5,6,8,17,18,23,24

R96
0
0603

0
0603

+3V

GND
SUSTAT1#

SUSTAT2#

SUSA#

SUSB#

SUSC#

VDD5

+5V51

VDD3

+12V

FULL ON

POS

STR

STD(SOFT OFF)
(ACIN OR BATTERY IN)
MECH OFF
(NO ACIN & NO BATT)

O / X
ADIN / BAT
X

+5V

+5VS

+3V
O

+3VS

CPU_IO

CPU_CORE

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

20
8

of

24

+3V
J514

3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13

GND

GND

+5V_1

120Z/100M
PC524 2012
10U
1210
10V

6 SUSB#
17 CHARGING
17,22 BAT_TYPE
ADINP_1

22 BATT1

17 BAT_C
PL7

BEAD_300Z/100M
T_CLK
0603B
15 ROUT+
PL6
15 ROUT1
2

2
120Z/100M
2012
PL8

+5V_1

+5V

120Z/100M
2012

NIMH 22
VADJ_1 17
VADJ_2 17
LI_OVP 22 PL503
ADINP_1
1
2

ADINP2 22

BAT_V 17
120Z/100M
LI/NIMH 22
2012
T_DATA

PC28
22U
1812
10V
20%

GND

PC526
0.1U
0603B
50V

1
GND

+12V

+3V

PL9
DISCHARG_C 22
+3V_1

PC30
0.1U
0603B
50V
VDD5S_P 22,23

GND

LOUT+ 15
LOUT- 15

17 BAT_D

HDR/FM/1.27MM/H5
BEAD_300Z/100M
0603B

PR505
4.99K
0603B
1%
BAT_T 17
PR18
20K
0603B
1%

PC521
0.1U
0603B
50V

0.6MM/H8.45
CONN_FX8CPSV4_60A

AD23
AD24
AD25
AD26
AD27
AD28
AD29

+3V_1

VMAIN

3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13
3,6,11,13

17,24 PWR_ON
22 SHUTDOWN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

AD23
AD24
AD25
AD26
AD27
AD28
AD29

AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22

GND
GND
PL10
2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22

AD3 3,6,11,13
AD4 3,6,11,13
AD5 3,6,11,13
AD6 3,6,11,13
AD7 3,6,11,13
AD8 3,6,11,13
AD9 3,6,11,13
AD10 3,6,11,13
AD11 3,6,11,13
AD12 3,6,11,13
AD13 3,6,11,13

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

16 MODEM_RI#
14 MODEMSPK
14 MODEM_MIC

AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13

PC525
0.1U
0603B
50V

P_GNT2#
P_REQ2#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
AD30
AD31

3,19 P_GNT2#
3,6,19 P_REQ2#
3,6,11,13 C/BE0#
3,6,11,13 C/BE1#
3,6,11,13 C/BE2#
3,6,11,13 C/BE3#
3,6,11,13 AD30
3,6,11,13 AD31

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR

3,6,11,13,19 FRAME#
3,6,11,13,19 IRDY#
3,6,11,13,19 TRDY#
3,6,11,13,19 DEVSEL#
3,6,11,13,19 STOP#
11,13,19 PERR#
3,6,11,13,19 SERR#
3,6,11,13 PAR
3,6,11,19 CLKRUN#

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

R234
1
10 0603

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

5 PCLKMODEM

PCLKMODEM

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

VMAIN
J510
AD0
AD1
AD2
MODEM_PME#
PIRQB#
PCIRST#

3,6,11,13 AD0
3,6,11,13 AD1
3,6,11,13 AD2
20 MODEM_PME#
6,11,19 PIRQB#
3,6,8,11,12,13 PCIRST#
2

GND
GND
+5V

JP_SMT1

JP11

JP_SMT1

R539
1

JP509

VDD5

VDD5_P 22

2
R540
0_NA
0805C_DFS

1
+5V

VDD5S

VDD5S_P 22,23

0_NA
0805

JP_SMT1

JP508

17,20 ADEN#

ADEN#_P 22

R541

JP_SMT1

JP12

+12V

0_NA
0805

C548
1U_NA
0805
16V

2,20 PWRGDCPU

PWRGDCPU_P 23

U502
2
4
5
8

1
1
2

TAP
ERROR

OUTPUT
SHUTDOWN
LP2986_NA

GROUND

6
GND
3
7
1

SO8
GND

C546
10U_NA
1206
10V

R537
270K_NA
0603

SENSE

INPUT

TP_VCCA

1
2

C547
1000P_NA
0603
+80-20%

FEEDBACK

+5V
R262

R538
100K_NA
0603

R261
330
0603

DS1267-10
SOL16

TPAGND

1
2

GND

28
19

13
14
15
16
17

U5
2
3
6
5
4

1IN1IN+
2IN2IN+
GND

1OUT
2OUT
VDD

1
21
22
23

7
8
1

26
25
24

TP2

TLC2262AID
SO8

TOUCHPAD_9

C353

TPAGND
TP_VCCA

R270
10K
0603

+5V

3
2
4
12MHZ

33P
0603
50V

RST
P1.5/INT0/D5
VCC
AVCC
P3.4/A4
P3.3/A3
P3.5/A5
P3.2/A2/A10

P1.0/ADC0/D0
P1.1/ADC1/D1
P1.2/ADC2/D2
P1.3/ADC3/D3
P1.4/ADC4/D4

P0.0/ASEL
P0.1/OE
P0.2

P1.6/INT1/D6
P1.7/T0/D7
P0.3
P3.6/A6
P3.7/A7
P0.4/PWMOUT

P3.0/A0/A8
P3.1/A1/A9

X2
X1

20
1
2
27
3

R278
1

0603
2
GND

8
7
6

TP/T_CLK
TP/T_DATA

TP/T_CLK 17
TP/T_DATA 17

T_CLK
T_DATA

5
4

GND

TPAGND

C355
1

C354

L33

TPM749DB
SSOP28

1M
0603
X7
1

BEAD

TPAGND
D

11

R269

R271 680K
0603

L32
1

2
33P
0603
50V

TP/T_DATA

10
1
TPAGND

AVSS

J7

16
11
4
12
3
14
10
8

U6

VSS

Y
GND
X
V+

VCC
L0
L1
H0
H1
SOUT
COUT
GND

1
2
3
4
5

RST
DQ
CLK
VB
W1
W0
NC
NC1

TP/T_CLK

0_NA
0603

R268 680K
0603

U4

T_DATA

18

33P
0603
1 50V

6
9
7
1
5
13
2
15

GND
R267
220K
0603

C352
1

00-6227-005-100-800
KYOCERA
FPC/FFC-5

TPAGND

1M
0603

1
0_NA
0603
R266

C351
0.1U
0603
50V

12

R265

C350
1U
0805
16V

R264
10K
0603

1M
0603

R263

GND
C

C348
4.7U
1206
16V

GND

T_CLK

33P
0603
50V

BEAD_DFS
GND
TPAGND

GND

GND
MITAC INTERNATIONAL CORP.
Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

21
8

of

24

VDD5_P 21
ADINP2 21

V1 1

2
K

PD1
RLZ24D
MLL34B

SFPJ-73
DC2010

17,21 BAT_TYPE

1
PR22
1M
0603B
1%

PR510
2.2M
0603B

LI/NIMH 21

PC520
0.1U
0603
50V

PR1
4.7K
0805C

PC2
0.1U
0603B
50V

5
PT1
3
50UH

PU503B
LMV393M
SSOP8
5

PC1 1
0.1U
0603B2
50V

PWR-3P

1
PR506
100K
0603B

PD9

VMAIN
6.5A/32VDC
1206

L3

PL11
120Z/100M
2012

K
SFPJ-73
DC2010

GND

GND

PR514
1M
0603B
1%

PC27
0.1U
0603
50V
2

PC29
0.01U
0603

GND

+ PC523
100U
25V

N1

L1

VDD5S_P 21,23

PD10
A

2
PL2
120Z/100M
2012

PF1

AC_IN
L2

GND

VDD5S_P 21,23

PR26
226K
0603B
1%

PU503A
LMV393M
3 SSOP8

1
VDD5_P 21

ADEN#_P 21

DISCHARG_C 21

PQ502

D
S

G
1

DTC144WK
SOT23AN_1

PQ13
2N7002
SOT23_FET

2
AC_IN

GND

PR511
100K
0603B

PR23
2.2M
0603B

GND

VMAIN

PQ501

MMBT3904L
B
SHUTDOWN 21

PQ12
SCK431CSK-5

PC25
0.1U
0603B
50V

PR19
324K
0603

PR25
80.6K
0603B
1%

PC26
0.1U
0603
50V
2

C245
0.1U
0603
50V

1
4

2
1

PC23
1U
1206
25V

PR20
1M
0603B
1%

1K
0603

PR16
10K
0603B

17 BATT_DEAD

PR512
20K
0603B
1%

PR507

PU504A
LMV393M
3 SSOP8

PR17
100K
0603B

VDD5S_P 21,23

GND

PC22
0.1U
0603
50V

GND
GND
GND
VDD5S_P 21,23
BATT1 21
1
1
6

PD8
A

PR509
130K
0603
1%

PC21
0.1U
0603
50V

K
NIMH 21
2

BAS32L

PC24
0.1U
0603B
50V

1
PR508
32.4K
0603
1%

PC522
1U
1206
25V

7
21 LI_OVP

PU504B
PR513
LMV393M
1.21K
SSOP8
0603 1%
5
1
2

1M
0603B
1%

PR21
47K
0603B

PR24
1

3
2
1

PL501
120Z/100M_NA
2012
2

3
2
1

PJ501

PL1
120Z/100M
2012

GND

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD
Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

22

of

24

PC502
+

PC503
+

330U
6.3V
20%

330U
6.3V
20%

330U
6.3V
20%

PC501
+

PC506
+ 220U
7343
4V

1
2

PC507
+ 220U
7343
4V

PC504
+ 220U
7343
4V

PC505
+ 220U
7343
4V

120Z/100M
2012

1
1

PC508
+ 220U
7343
4V

PL12

PC33
0.01U
0603

VCC_CORE

VMAIN

GND

5
6
7
8

GND

GND

GND

PL3

PC535
10U
1210
25V
20%

1
PU2
2

PL514
C3

2
120Z/100M
2012
PC7
1000P
0603

1
PR5
10K
0603
1%

1
PR9
118K
0603
1%

PR12
59K
0603

PR14
30.1K
0603
1%
2

JP505

PR7
237K
0603
1%

PR6
102K
0603
1%

C5

C4

BAT54_NA

PC533
10U
1210
10V

1
2

+ PC515
220U
4V

+ PC517
330U
4V
+-20%

+ PC513
330U
4V
+-20%

PC18
0.1U
0603
50V

PC11
0.1U
0603
50V

SFPJ-73
DC2010

PC536
10U
1812
25V
20%

1
1

PC16
10U
1206
16V

PC514
1U
0805
16V

0.005
7520

PD503

PC512
0.01U
0603

G
PQ11
SPB46N03L

2
510K
0603

PD7
3

5,6,8,17,18,20,24 SUSA#

C2
PR503
1

PR11

SB3032P

47K
0603

120Z/100M
2012
PL4

BAS32L

+5V

2
8UH/11.5T

PD6
A

2
VCC_CORE

PC13
0.1U
0603
50V

16
15
14
13
12
11
10
9

0
0603
PR504

RS
BOOST
VU
LCNX
PGND
VL
V5
VIN

PR15

21 PWRGDCPU_P

VOUT
SS
SGND
REF
FB
PWRGD
PWRON
RF

1
2
3
4
5
6
7
8

2
120Z/100M
2012
PL5

S
2

PC534
10U
1210
25V
20%
GND
GND
2

+ PC519
100U
25V

PC20
0.01U
0603

G
C1

PU5
SI4416DY

2
SHORT-SMT

1
2
3
4

RP41

PQ8B
NDC7002N

PQ8A
NDC7002N

PQ7B
NDC7002N

PQ7A
NDC7002N

GND

8
7
6
5

21,22 VDD5S_P
3

100K*4
1206

PQ5
2

DTC144WK

2 VID1

GND

PQ6
2

DTC144WK

2 VID2

SWITCH

VID1 VID2 VID3 VID4


0

1.85

1.8

1.75

1.7

1.65

1.6

1.55

1.5

1.45

1.4

1.35

1.3

GND

PQ9
2

DTC144WK

2 VID3

GND

PQ10
2

DTC144WK

2 VID4

1.9

1.95

2.0

VOL

GND

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

23
8

of

24

VMAIN

PL13
120Z/100M
2012
2

PC34
0.01U
0603

GND
PC15
0.01U
0603
5
6
7
8

+ PC518
100U
25V

PU3
SI4416DY

GND

G
T1

GND

4
1

PL14
2

VTT

PD5
RLZ2.0B

PC530
1000P
0603

PR8
10K
0603
1%

PC17
+ 220U
7343
4V

PC531
0.1U
0603
50V

PC509
0.1U
0603
50V

PC35
10U
1210
10V

S
2

1
2

PC32
10U
1206
16V

PC532
10U
1812
25V
20%

+ PC516
220U
4V

G
4

PU4
SI4832DY

BAS32L

T2

2
120Z/100M
2012

.02
2512
1%

2
510K
0603

PC10
1U
0805
16V

PC8
0.01U
0603

PR13
2

5
6
7
8

PD11

14U/13.5TS

PR515

PL502
T3

PD3

PC31
0.1U
0603
50V

SB3032P

47K
0603

5,6,8,17,18,20,23 SUSA#

16
15
14
13
12
11
10
9

17,21 PWR_ON

RS
BOOST
VU
LCNX
PGND
VL
V5
VIN

PR501
1

VOUT
SS
SGND
REF
FB
PWRGD
PWRON
RF

1
2
3
4
5
6
7
8

PU1

BAT54_NA
T4

PR27
39.2K
0603
1%

JP18
1

2
SHORT-SMT
GND

+5V

PQ2
SI2302DS
D

D
S

PR4
1K
0603

Could the CKT support 1.5 A current?

+2.5V_CPUIO
1

+3V

PC4
10U
1206
16V

2
1
PC5
1000P
0603

PD2
RLZ2.7B
A

PC3
1U
0805
16V

1
2

PQ1
DTC144WK_NA

Could the CKT support ATI Mobility?

PQ4
SCK431CSK-5
3

5,6,8,17,18,20,23 SUSA#

D
S
S

PR3
470
0603

PR2
100K_NA
0603
PQ3
2N7002_NA
G

GND

MITAC INTERNATIONAL CORP.


Title
6120W/N - MOTHER BD

Size
C

Document Number
SD411667900001

Date:

Monday, April 10, 2000

Rev
02
Sheet

24
8

of

24

FD3
FD_DOT040

FD4
FD_DOT040

FD501
FD_DOT040

FD1
FD_DOT040

J1

SUSB#

ADINP
BATT1
SMCLOCK
SMDATA

T_CLK
ROUT+
ROUT-

FD502
FD_DOT040

FD503
FD_DOT040

FD504
FD_DOT040

+5V
CHARGING
BAT_TYPE

+3V

PWR_ON
SHUTDOWN

GND
GND

VMAIN
1

PC17
0.1U
0603
50V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

FD2
FD_DOT040

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

VMAIN

GND

DISCHARG_C
+12V

+3V
+5V
NIMH
VADJ_1
VADJ_2
LI_OVP
ADINP

1
T_DATA
LOUT+
LOUT-

1
2
1
2
PL2
PL501
BEAD_120Z/100M_6A
PL502
BEAD_120Z/100M_6A 0805C
BEAD_120Z/100M_6A 0805C
0805C

BAT_V
LI/NIMH
BAT_T

HDR/MA/1.27MM/H9.5

7 MTG7

6
5

MTG/ID3.0OD6.0

GND

HDR/FM/6PX1/GLD
1
2

R6
R7

1
2

0_NA
0_NA 2 0805C_DFS
2 0805C_DFS

1
1

BAT_T

PL507
BEAD_300Z/100M
0603B

PL508
BEAD_300Z/100M
0603B

SMDATA

LI/NIMH

PL509
BEAD_300Z/100M
0603B

SMCLOCK

7 MTG5

MTG/ID3.0OD6.0

ROUT+
ROUT-

J4

GND
1

GND1
1

3
PL510
BEAD_300Z/100M
0603B

GND1

B1

7 MTG6

6
5
4
3
2
1

1
J2

LINE OUT

PC530
0.1U
0603
50V

MTG/ID3.0OD6.0

BATT+

PL516
PL511
BEAD_120Z/100M_6A BEAD_120Z/100M_6A
0805C
0805C
1
2 B2
1
2

BATTERY CONNECTOR

GND

1
1
1
1
2

SWR

GND

GND

C2
47P
0603

1
2
3
4
5
6
7
8
9
10
11
12

7 MTG3

MTG/ID3.0OD6.0
C501
0.1U
0603
50V

GND
GND

FPC/FFC-12P/1MM

C1
47P
0603
2

30V/.1A

1
2
3
4
5
6
7
8
9
10
11
12

R5
0
0603

30V/.1A
SW2
1

J501

C3
47P
0603

R2
0
0603

SWL

SW_LEFT
SW1
1

GND
1

T_DATA

GND

BEAD_300Z/100M
0603B

LOUT+
LOUT-

L3

C4
47P
0603

1
1

DF13-2P-1.25H

R4
R3

1
2

L1
BEAD_300Z/100M
0603B

1
2

0_NA
0_NA 2 0805C_DFS
2 0805C_DFS

J3

7 MTG4

3
4

T_CLK

MTG/ID3.0OD6.0
+5V

TOUCH_PAD OCNNECTOR
L2
BEAD_300Z/100M
0603B

DF13-2P-1.25H

GND

SW_RIGHT

GND

DRAWN

DESIGN CHECK

ISSUES
Title
6120- CHARGER & DD
Size
C
Date:

Document
Number

Rev
R02

SD411666500002
Friday, April 14, 2000
E

Sheet

of

PQ508
SI4435DY

PD509

K
2

PR2
1M
0603
1%

62

2
4

6
5

1
5

PR7
1M
0603
1%

1
PR3
22.6K
0603
1%

PR507
22.6K
0603
1%
1

PC512
2

0.1U
50V
0603B

0.1U
50V
0603B

PR506
1

GND1

2N7002

D
S

PWR_ON

PC508
1
2

PR521
.05
2512
1%

GND

PQ501

REF

6.2K
0603B

GND

BATT1

BATT+
PR11
301K
0603B
1%

PR12
100K
0603
1%

+ PC14
100U
25V

PR519
1

BAT_V

GND

GND

FUSE_6.5A/32VDC
1206

PC522
0.1U
0603
50V

PC15
0.1U
0603
50V

PR10
100K
0603B
1%
2

PF501
BATT3

2
PL504
120Z/100M
2012

PL503
120Z/100M
2012
1

8
7
6
5

12.60V

VMAIN

3
2
1
G

BATT2

PQ510
SI4435DY

2
PL506
120Z/100M
2012

12.50V

12.40V

12.30V

PL505
120Z/100M
2012

VADJ2_P

VADJ1_P

PR9
1M
0603
1%

2
PR4
10K
0603B
1%

PC6
1000P
0603B
10%,X7R

PR508
100K
0603
1%

PC510
1U
0805
16V

0.01U
0603B

PC7
2

2
PR509
10K
0603B
1%

VADJ_2

PQ1A
NDC7002N

PR6
1M
0603
1%

PC509 0603B
0.01U/16V
2

VADJ_1
PQ1B
NDC7002N
1

1
PR8
3M
0603

0
0603

TL594C
SO16
PR5
2

LI_OVP

BAT_TYPE

PD2
BAS32L
MLL34B

8
7
6
5
4
3
2
1

1
2

PC513
0.1U
0603B
50V

PR14
487K
0603
1%

PQ2B
NDC7002N
1

GND

2IN+

GND

E1
C1
E2
GND
C2
RT
VCC
CT
OUTPUTCTRL
DTC
REF
FEEDBACK
2IN1IN2IN+
1IN+

PR511
47K
0603

PU502
9
10
11
12
13
14
15
16

PC514
0.1U
0603B
50V

1
PQ2A
NDC7002N
3

D
2

PR16
976K
0603B
1%

NIMH

D
S

BATT+

GND
PR520
20K
0603B
1%

REF

PR13
13.7K
0603
1%
2

1
PQ506
DTA144WK

CHARGING

PR15
22.1K
0603B
1%

A
BAS32L
MLL34B

2
PR510
4.7K
0603

SFPJ-73
DC2010
PC525
0.1U
0603
50V

2
120Z/100M
2012

GND

PD507
K

PQ507
2N7002
SOT23_FET

PC524
10U
1812
25V
20%

PL515
2 L71

120Z/100M
2012
PD508
RLZ20C
MLL34B

2IN+
GND

PC523
0.01U
0603

2
GND

2
GND

PR517
100K
0603
1%

C
PQ509
EMMBT2222A
SOT23

+ PC13
22U
20V

PD506
SFPJ-73
DC2010

PR518
2.2K
0603B

PC515
0.1U
0603
50V

PL514
L6 1

PD510
1

80UH/33T/D.30

1
1

+ PC9
100U
25V

K
SFPJ-73
DC2010

L5

120Z/100M
2012
1

A
PL1
L4

ADINP

8
7
6
5

L3

PL513

3
2
1

DISCHARG_C
47K
0603B

GND

MITAC INTERNATIONAL CORP.


Title
6120- CHARGER & DD
Size
C

Document Number
SD411666500002

Date:

Friday, April 14, 2000

Rev
R02
Sheet

of

PR1
1

PWR_ON
100K/NA
0603B

PU1
HA178L12UA
SOT89N

PL3
PD1

3
1

GND

PC4
0.1U
0603
50V

PC519
0.1U
0603
50V

LI2209

PR515
100K
0603
1%

PC517
0.1U
0603
50V

+ PC520
150U
7343
6.3V

1
+ PC10
220U
6.3V
20%

+ PC11
220U
6.3V
20%

A
3

PC16
22U_NA
1812
10V
20%

SFPJ-73
DC2010

1
1

PD505
S
2

PC502
1000P
0603

PQ5051
FDS6690

+5V
PR516
243K
0603B
1%

G
D4

PR505
2
.02
2512
1%

PU501
SB3052P

20

PC505
1U
0805
16V

+12V
PC3
1U
1206
25V

5
6
7
8
2

LI2214

19
15
21
14
6
4
8
5
7

GND
LI2208

DL5
CS5
FB5
SS5
VH
D1
Q1
D2
Q2

1
4
PT1
2
18UH

PC2
0.1U
0805
25V
+80-20%

PC506
1000P
0603B

DL3
CS3
FB3
SS3
ON3
ON5
SHDN*
SYNC
REF

PGND

2
3
1

24
1
28
2
3
13
SD_PWR 12
11
10

OUT

IN

S
D3

PC503
0.1U
0603
50V

PC1
10U
1812
25V
20%

2
GND

5
6
7
8

GND

LI2212

PC504
10U
PD502
1210
16V
PQ503 D
BAS32L
FDS6612
G
GND
4

1
18
16
17

22
VL

1
1

1
23
V+

BST5
DH5
LX5

SGND

BST3
DH3
LX3

PQ504
NDS9410
SO8

PR501
10K
0603
1%

K
2
G

1
2

4
PC516
PR512
0.1U
0603
100K
50V
0603B
1%

25
27
26

GND

8
D

D2

7
6
5

PD504
EC10QS04

1
PC521
+ 220U
7343
4V

+ PC12
220U
4V

ETQP_CDRH125

.02
2512
1%

PR513
124K
0603
1%

SGND

PC507
0.1U
0603
50V

LI2213

PC518
0.1U
0603
50V

PC501
0.1U
0603
50V

+3V

PQ502
NDS9410
SO8

PT2

PR514
1

2
3
1

PC5
0.1U
0603
50V

BAS32L

D1

PD503

PC511
0.01U
0603

A
7
6
5

K
EC10QS04

+ PC8
100U
25V

LI2207

120Z/100M
2012

LI2211 A

L2

1
VMAIN

SGND
JP2

2
GND

GND

GND

SHORT-SMT

JP1
1

2
PR503
0
0603B

2
PR504
0/NA
0603B

2
SHORT-SMT

SGND
R1
47K
0603
2

PD501
PR502
SD_PWR

PWR_ON
3

SUSB#
D1

SHUTDOWN

2
2

3
1

10K
0603
1%

DAN202K

BAT54_NA

MITAC INTERNATIONAL CORP.


Title
6120- CHARGER & DD
Size
C

Document Number
SD411666500002

Date:

Friday, April 14, 2000

Rev
R02
Sheet

of

SERVICE
SERVICE MANUAL
MANUAL &
& TROUBLESHOOTING
TROUBLESHOOTING GUIDE
GUIDE FOR
FOR
6120N
6120N
Sponsoring Editor : Shoestring Tsai
Author : Willy.Chen
Assistant Editor : Kelly Chiang
Publisher : MITAC INTERNATIONAL CORP.
Address : 4F, NO.18, PU-DING ROAD, HSINCHU, TAIWAN, R.O.C.
TEL : 886-3- 5645850

Fax : 886-3- 5781245

Third Edition : Mar. 2001


E-mail : Jesse.Jan @ mic.com.tw

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