Lecture 28 - Oversampled ADCs & Final Remarks

EE247
Lecture 28
Administrative
Extra office hours next week @ 563 Cory:
Wed. Dec. 12th, 2pm-4pm
Thurs. Dec. 13th, 10am-12pm
Project submission:
Deadline extended: Thurs. Dec. 13th or Frid. Dec. 14th
If you have chosen to do the project, please make an
appointment with the instructor for 15mins per each project report
to present the results:
Thurs. Dec. 13th, after 1pm or
Frid. Dec.14th after 10am
EECS 247 Lecture 28:
Oversampled ADCs Cont'd & Final Remarks
2007 H. K. Page 1
EE247
Lecture 28
Higher order modulators
Cascaded modulators (MASH) (last lecture)
Forward path multi-order filter (continued)
Bandpass modulators
Testing of modulator front-end
Acknowledgements
Examples of systems utilizing analog-digital interface circuitry
(not part of final exam)
2007 H. K. Page 2
Higher Order Modulators

(2) Multi-Order Filter
E(z)
H ( z)
X(z)
Y ( z) =
Y(z)
H ( z)
1
X ( z) +
E( z)
1 + H ( z)
1 + H ( z)
NTF =
Y( z )
E( z )
1
1+ H( z )
Zeros of NTF (poles of H(z)) can be strategically positioned to

suppress in-band noise spectrum
Approach: Design NTF first and solve for H(z)
2007 H. K. Page 3
Example: Modulator Specification

Example: Audio ADC
Dynamic range
Signal bandwidth
Nyquist frequency
Modulator order
Oversampling ratio
Sampling frequency
DR
B
fN
L
M = fs/fN
fs
18 Bits
20 kHz
44.1 kHz
5
64
2.822 MHz
The order L and oversampling ratio M are chosen

based on
SQNR > 120dB
2007 H. K. Page 4
Noise Transfer Function, NTF(z)
NTF [dB]
% stop-band attenuation Rstop=80dB, L=5 ...

L=5;
Rstop = 80;
B=20000;
[b,a] = cheby2(L, Rstop, B, 'high');
20
% normalize
0
b = b/b(1);
NTF = filt(b, a, ...);
-20
Chebychev 2 filter chosen

zeros in stop-band
-40
-60
-80
-100
104
Frequency [Hz]
106
2007 H. K. Page 5
Loop-Filter Characteristics
H(z)
Loopfilter H [dB]
100
Y ( z)
1
NTF =
=
E ( z) 1 + H ( z)
1
H ( z) =
1
NFT
80
60
40
20
0
-20
10
10
Frequency [Hz]
2007 H. K. Page 6
Modulator Topology
Simulation Model
Filter
b2
b1
I1
I2
I3
I4
K1 z-1
-1
1-z
K2 z-1
-1
1-z
K3 z-1
-1
1-z
K4 z-1
-1
1-z
I_1
a1
I_2
a2
I5
I_3
K5 z-1
-1
1-z
I_4
a3
I_5
a5
a4
Q
DAC Gain
Comparator
+1
-1
2007 H. K. Page 7
Loop filter peak voltages [V]
Internal Node Voltages

Internal signal peak
amplitudes are weak
function of input level
(except near overload)
10
5
0
Maximum peak-topeak voltage swing

approach +-10V!
Exceed supply
voltage!
-5
i1
i2
i3
i4
i5
q
-10
-15
-20
-40
-35
-30
Integrator outputs
Quantizer input
-25
-20 -15
Input [dBV]
-10
-5
Solutions:
Reduce Vref ??
Node scaling
2007 H. K. Page 8
Node Scaling Example:

3rd Integrator Output Voltage Scaled by
K3 * , b1 /, a3 / , K4 / , b2 *
Vnew=Vold*
b1
b2
K1 z-1
-1
1-z
I1
K2 z-1
-1
1-z
I2
I_1
a1
K4 z-1
-1
1-z
I4
K3 z-1
-1
1-z
I3
I_2
I_3
a2
K5 z-1
-1
1-z
I5
I_4
I_5
a5
a4
a3
Q
DAC Gain
g
Comparator
Y
2007 H. K. Page 9
Node Voltage Scaling

1.5
0.5
-0.5
-1
-1.5
-40
-35
-30
-25
-20
-15
Input [dBV]
-10
-5
=1/10
k1=1/10;
k2=1;
k3=1/4;
k4=1/4;
k5=1/8;
a1= 1;
a2=1/2;
a3=1/2;
a4=1/4;
a5=1/4;
b1=1/512;
b2=1/16-1/64;
g =1;
Integrator output range reasonable for new parameters

But: maximum input signal limited to -5dB (-7dB with safety) fix?
2007 H. K. Page 10
Input Range Scaling

Increasing the DAC levels by using higher value for g reduces the
analog to digital conversion gain:
1
DOUT ( z )
H ( z)
=
1 + gH ( z ) g
VIN ( z )
Loop Filter
H(z)
VIN
Comparator
DOUT
+1 or -1
g
Increasing VIN & g by the same factor leaves 1-Bit data unchanged
2007 H. K. Page 11
Scaled Stage 1 Model

1.5
g modified:
From 1 to 2.5;
Overload
0.5
input level
shifted up by
8dB
0
-0.5
-1
-1.5
-40
-35
-30
-25
-20
-15
Input [dBV]
-10
-5
0
+2dB
2007 H. K. Page 12
Stability Analysis
(not included in final exam)
e(kT)
x(kT)
H(z)
q(kT)
Geff
y(kT)
Quantizer Model
Approach: linearize quantizer and use linear system theory!

One way of performing stability analysis use RLocus in Matlab with
H(z) as argument and Geff as variable
Effective quantizer gain
2
G2 = y
eff
q2
Can obtain Geff from simulation
Ref: R. W. Adams and R. Schreier, Stability Theory for Modulators, in Delta-Sigma Data
Converters- S. Norsworthy et al. (eds), IEEE Press, 1997
2007 H. K. Page 13
Stability Analysis
G H (z)
1+ G H (z)
N (z)
H (z) =
D (z)
G N (z)
STF =
D (z) + G N (z)
STF =
Zeros of STF same as zeros of H(z)

Poles of STF vary with G
For G=0 (no feedback) poles of the STF same as poles of H(z)
For G=large, poles of STF move towards zeros of H(z)
Draw root-locus: for G values for which poles move to LHP (s-plane) or
inside unit circle (z-plane) system is stable
2007 H. K. Page 14
Modulator z-Plane Root-Locus

z-Plane Root Locus
0.4
Increasing Geff
As Geff increases, poles of STF
move from
poles of H(z) (Geff = 0) to
zeros of H(z) (Geff = )
0.3
0.2
0.1
Geff = 0.45
Pole-locations inside unit-circle

correspond to stable STF and
NTF
-0.1
-0.2
Unit Circle
-0.3
Need Geff > 0.45 for stability
-0.4
0.6
0.7
0.8
0.9
1.1
2007 H. K. Page 15
Effective Quantizer Gain, Geff

Large inputs comparator
input grows
Output is fixed (1)
Geff drops
modulator unstable for
large inputs
Effective Quantizer Gain
0.8
0.6
Geff=0.45
0.4
stable
0.2
0
-40
-35
-30
-25
-20
-15
-10
-5
Solution:
Limit input amplitude
unstable Detect instability (long
sequence of +1 or -1)
and reset integrators
Input [dBV]
Be ware that signals

grow slowly for nearly
stable systems use
long simulations
2007 H. K. Page 16
5th Order Modulator

Final Parameter Values
1/512
b1
1/10
K1 z-1
-1
1-z
1/4
1/4
K2 z-1
-1
1-z
K3 z-1
-1
1-z
I3
K4 z-1
-1
1-z
I4
I2
I1
Input range
~ 1V
1/16-1/64
b2
I_1
a11 1
I_2
a2 12
1/8
K5 z-1
-1
1-z
I5
I_3
I_4
a3 1/2
a4 1/4
I_5
a5 1/4
2.5V
DAC Gain
g
Comparator
Y
Stable input range with margin ~ 1V

2007 H. K. Page 17
Summary
Oversampled ADCs decouple SQNR from circuit
complexity and accuracy
If a 1-Bit DAC is used, the converter is to 1st order,
inherently linearindependent of component matching
Typically, used for high resolution & low frequency
applications e.g. digital audio
2nd order used extensively due to lower levels of limit
cycle related spurious tones compared to 1st order
modulators of order greater than 2:
Cascaded (multi-stage) modulators

Single-loop, single-quantizer modulators with multi-order
filtering in the forward path
2007 H. K. Page 18
Bandpass Modulator
vIN
Resonator
dOUT
DAC
Replace the integrator in 1st order lowpass with a

resonator
2nd order bandpass
2007 H. K. Page 19
Bandpass Modulator
Example: 6th Order
Measured output
for a bandpass
(prior to digital
filtering)
Quantization
Noise
Input Sinusoid
Key Point:
NTF notch
type
shape
STF bandpass
shape
Ref:
Paolo Cusinato, et. al, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dB
Dynamic Range , JSSCC, VOL. 36, NO. 4, APRIL 2001
2007 H. K. Page 20
Bandpass Characteristics
Oversampling ratio defined as fs /2B where B
= signal bandwidth
Typically, sampling frequency is chosen to be
fs=4xfcenter where fcenter bandpass filter center
frequency
STF has a bandpass shape while NTF has a
notch shape
To achieve same resolution as lowpass, need
twice as many integrators
2007 H. K. Page 21
Bandpass Modulator Dynamic Range

As a Function of Modulator Order (K)
K=6
21dB/Octave
K=4
15dB/Octave
K=2
9dB/Octave
Bandpass resolution for order K is the same as lowpass

resolution with order L= K/2
2007 H. K. Page 22
Example: Sixth-Order Bandpass Modulator
Simulated noise transfer function
Simulated signal transfer function
Ref:
2007 H. K. Page 23
Example: Sixth-Order Bandpass Modulator

Features & Measured Performance
Summary
fs=4xfcenter
B
OSR=fs /2B
Ref:
2007 H. K. Page 24
Modulator Front-End Testing

Should make provisions for testing the modulator (AFE) separate from the
decimator (digital back-end)
Data acquisition board used to collect 1-bit digital output at fs rate
Analyze data in a PC environment or dedicated test equipment in manufacturing
environments can be used
Need to run DFT on the collected data and also make provisions to perform the
function of digital decimation filter in software
Typically, at this stage, parts of the design phase behavioral modeling effort can
be utilized
Good testing strategy vital for debugging/improving challenging designs
fs
Filtered
AFE
Sinwave
Data
Acq.
PC
Matlab
2007 H. K. Page 25
Summary
Oversampled ADCs
Noise shaping utilized to reduce baseband quantization noise
power
Reduced precision requirement for analog building blocks
compared to Nyquist rate converters
Relaxed transition band requirements for analog anti-aliasing
filters
Utilizes low cost, low power digital filtering
Speed is traded for resolution
Typically used for lower frequency applications compared to
Nyquist rate ADCs
2007 H. K. Page 26
Material Covered in EE247

Filters
Continuous-time filters
Biquads & ladder type filters
Opamp-RC, Opamp-MOSFET-C, gm-C filters
Automatic frequency tuning
Switched capacitor (SC) filters
Data Converters
D/A converter architectures
A/D converter
Nyquist rate ADC- Flash, Interpolating & Folding,
Pipeline ADCs,.
Self-calibration techniques
Oversampled converters
2007 H. K. Page 27
Acknowledgements
The course notes for EE247 are based on
numerous sources including:
Prof. P. Grays EE290 course

Prof. B. Bosers EE247 course notes
Prof. B. Murmanns Nyquist ADC notes
Fall 2004 & 05 & 06 EE247 class feedback
Last but not least, Fall 2007 EE247 class
The instructor would like to thank the class of 2007 for
their enthusiastic & active participation!
2007 H. K. Page 28
Systems Including Analog-Digital Interface Circuitry

(Not Included in Final Exam)
Wireline communications
Telephone related (DSL, ISDN, CODEC)
Television circuitry (Cable modems, TV tuners)
Ethernet (10/1Gigabit, 10/100BaseT)
Wireless
Cellular telephone (CDMA, Analog, GSM.)
Wireless LAN (Blue tooth, 802.11a/b/g..)
Radio (analog & digital), Television
Disk drives
Fiber-optic systems
2007 H. K. Page 29
E.E. Circuit Course

vs. Frequency Range
RF Band
500kHz
100GHz
IF Band
455kHz
AM Radio
10.7MHz
80MHz
FM Radio Cellular Phone
100MHz
Baseband
DC
500MHz
EE240, EE247
EE242
2007 H. K. Page 30
Wireline Communications
Telephone Based
2007 H. K. Page 31
Data Transmission Over Existing Twisted-Pair

Phone Lines
Backbone
Digital Network
Central Office
Xmitter
Customer
Twisted Pair
Xmitter
Receiver
Receiver
3 to 5km
POTS
Data transmitted over existing phone lines covering distances close to

3.5miles
Voice-band MODEMs (up to 56Kb/s)
ISDN (160Kb/s)
HDSL, SDSL,
ADSL (up to 8Mb/s)
2007 H. K. Page 32
Data Transmission Over Twisted-Pair Phone Lines

ISDN (U-Interface) Transceiver
Backbone
Digital Network
Central Office
Customer
Xmitter
Twisted Pair
Xmitter
Receiver
Receiver
3 to 5km
POTS
Full duplex transmission (RX & TX signals sent simultaneously)

160kbit/sec baseband data (80kHz signal bandwidth)
Standardized line code 2B1Q (4 level code 3:1:-1:-3)
Max. desired loop coverage 18kft (~36dB signal attenuation)
Final required BER (bit-error-rate) 10-7 (min. SNDR=27dB)
2007 H. K. Page 33

Echo Problem
Central Office
Customer
Xmitter
Xmitter
Receiver
Receiver
Transformer coupling to line

For a perfectly matched system no leakage of TX signal into RX path
Unfortunately, system has poor matching + complicating factor of bridgedtaps
Bridged
Tap
Problem
Open
Line
2007 H. K. Page 34

Echo Problem
Central Office
Customer
Xmitter
Xmitter
Receiver
Receiver
System full duplex transmission RX & TX signals sent simultaneous (& at the
same frequency band)
Leakage of TX signal to RX path (echo)
Worst case echo could be 30dB higher compared to the received
signal!!
2007 H. K. Page 35

Echo Cancellation
Echo cancellation performed in the digital domain

Typically echo cancellation performed by transversal adaptive digital filter
Any non-linearity incurred by the analog circuitry makes echo canceller
significantly more complex
Desirable to have high linearity analog circuitry (75dB range)
2007 H. K. Page 36
Simplified Transceiver Block Diagram
CMA Control, maintenance & access unit

DFE Decision feedback equalizer
DEC Decimation filter
REC Reconstruction filter
LEC & NEC Linear/non-linear echo-canceller
Ref: H. Khorramabadi, et. al"An ANSI standard ISDN transceiver chip set, " IEEE International
Solid-State Circuits Conference, vol. XXXII, pp. 256 - 257, February 1989
2007 H. K. Page 37
Analog Front-End
2b S.C.
DAC
2nd order
Butterworth
S.C. Filter
Class A/B
Line Driver
13bit
2nd Order
To avoid stringent
requirements for nonlinear echo canceller:
high linearity analog
circuitry needed (~ 75dB)
Peak signal frequency 80kHz
2007 H. K. Page 38

DSL (Digital Subscriber Loop)
Backbone
Digital Network
Central Office
Xmitter
Customer
Twisted Pair
Xmitter
Receiver
Receiver
3 to 5km
POTS
HDSL &SDSL more like ISDN @ higher frequencies

Full duplex transmission with RX & TX signals on the same
frequency band
2007 H. K. Page 39

ADSL (Asymmetric Digital Subscriber Loop)
Backbone
Digital Network
Central Office
Customer
Xmitter
Xmitter
Receiver
Receiver
POTS
In USA mostly ADSL FDM (frequency division multiplex)

Signal from CO to customer on a different band compared to
customer to CO
Echo cancellation can be performed by simple filtering
Data rates up to 8Mbps (much higher compared to ISDN)

2007 H. K. Page 40
ADSL Signal Characteristics
Main difference compared to ISDN: TX & RX signals on different

frequency bands
Downstream (fast, from CO to customer) 138kHz to 1.1MHz
Upstream (slow, from customer to CO) 30kHz to 138kHz
Echo cancellation much easier
More severe signal attenuation at high frequencies (1MHz DSL v.s.

80kHz ISDN)
2007 H. K. Page 41
Typical ADSL Analog Front-End

Central Office
Customer Premise
ADC 16/14b with 14bit linearity, pipeline with auto. calibration @ 5Ms/s
DAC 16/14b with 14bit linearity, with auto. calibration
On-chip filters 3rd to 4th order LPF with fc 1.1MHz for downstream and 138kHz upstream
(typically continuous-time type filters with on-chip frequency tuning)
Ref: D.S. Langford, et al, A BiCMOS Analog Front-End Circuit for an FDM-Based ADSL System,
IEEE Journal of Solid State Circuits, Vol. 33, No. 9, pp. 1383-1393, Dec. 1998.
2007 H. K. Page 42
Typical ADSL Analog Front-End
Note: Band selection filters

are off-chip due to stringent
noise requirements
(3nV/rtHz)
Discrete LC type
Line driver on a
separate bipolar
chip to achieve
required high
output signal levels
with high power
efficiency typically
+-12V supply
2007 H. K. Page 43
Wireless Communication
Circuits
2007 H. K. Page 44
Wireless Circuits
Differ from wired comm. circuits
Includes RF circuitry+IF
circuitry+baseband circuits (three different
frequency ranges)
Signal scenarios in wireless receivers more
challenging
Requirement for received signal BER in the
order of 10-3 for voice-only(min. SNR~9dB)
2007 H. K. Page 45
Typical Cellular Phone

Block Diagram
RF
Amp
Image
Reject
Filter
90
AGC
Duplexer
A/D
IF
Filter
AGC
A/D
Frequency
Synthesizer
D/A
Digital
Signal
Processor
(DSP)
PA
90
AGC
D/A
2007 H. K. Page 46
Superheterodyne Receiver
Image
Reject
Filter
RF
Amp
f2 -f1
f2 + f1 fc = f2 -f1
AGC
f1
f2
f2 -f1
f 2 + f1
Frequency
Synthesizer
One or more intermediate frequency (IF)

Periodic signal at a frequency equal to the desired RX signal + or IF frequency
is provided by a Local Oscillator
RX signal is frequency shifted to a fixed frequency (IF filter center frequency)
2007 H. K. Page 47
RF Superheterodyne Receiver
Example: CDMA Receiver
RF
Amp
Image
Reject
Filter
fc =85.38MHz
BW=1.25MHz
AGC
AGC
965.38MHz
870M
880MHz
RX Band
893.3MHz
Frequency
Synthesizer
85.38MHZ
Received frequency is mixed down to a fixed IF

frequency and then filtered with a bandpass filter
2007 H. K. Page 48
Why Image Reject Filter?
f2
f1
fIF
f 2 + f1
f2 -f1
f3 f2
RF
Amp
fIF = f2 -f1
f2
f3
fIF
f2 -f1
f 2 + f1
Frequency
Synthesizer
Any signal @ the image frequency of the RX signal with respect

to Osc. frequency will fall on the desired RX signal and cause
impairment
2007 H. K. Page 49
Why Image Reject Filter?

RF
Amp
Image
Reject
Filter
f1
f3
fosc -f1
fIF = fosc -f1

fosc
f1
fIF
f3
fIF
fosc
Frequency
Synthesizer
Image reject filter attenuate signals out of the RX band

Typically, image reject filters are ceramic or LC type filters
2007 H. K. Page 50
Quadrature Downconversion
A/D
RF
Amp
cosC t
sinC t
AGC
In-phase &
Quadrature
Channel Select
Filters
A/D
-fIF
fIF
In systems with phase or freq. modulation, since signal is not symmetric

around fIF , directly converting down to baseband corrupts the
sidebands
Quadrature downconversion overcomes this problem
2007 H. K. Page 51
1st
Adjacent
Channel
2nd
Adjacent
Channel
RF
Amp
60
30
Desired
Channel
Relative Signal Amplitude [dB]
Relative Signal Amplitude [dB]
Effect of Adjacent Channels
60
30
RF
Amp
fn1 fn2
2fn1 fn2
fRX fn1 fn2
2fn2 fn1
Adjacent channels can be as much as 60dB higher compared to the desired RX

signal!
Linearity of stages prior and including channel selection filters extremely important
2007 H. K. Page 52
Effect of Adjacent Channels

Due to existence of large unwanted signals & limited
dynamic range for the front-end circuitry:
Can not amplify the signal up front due to linearity issues
Need to allocate amplification/filtering numbers to RX blocks
carefully
Can only amplify when unwanted signals are filtered
adequately
System design critical with respect to tradeoffs affecting:
Gain
Linearity
Power dissipation
Chip area
2007 H. K. Page 53
Homodyne (Direct to Baseband) Receivers

A/D
RF
Amp
90
AGC
f1
f IF =0
A/D
fosc = f1
Frequency
Synthesizer
No intermediate frequency, signal mixed directly down to baseband

Almost all of the filtering performed at baseband
Higher levels of integration possible
Issue to be aware of:
Requirements for the baseband filters more stringent
Since the local oscillator frequency is exactly at the same freq. as the RX
signal freq. can cause major DC offsets & drive the receiver front-end
into non-linear region
2007 H. K. Page 54
Example: Wireless LAN 802.11b & Bluetooth

2MHz IF
Ref: H. Darabi, et al, A Dual Mode 802.11b/Bluetooth Radio in 0.35um CMOS, IEEE
ISSCC, 2003 pp. 86-87.
2007 H. K. Page 55
Digital IF Receiver
(IF sampling)
Digital
Multiplier
RF
Amp
A/D
cosC t
sinC t
Digital
LPF
Digital
Sinewave
Generator
AGC
Digital
Multiplier
Digital
LPF
IF signal is converted to digital most of signal processing performed in

the digital domain
Performance requirement for ADC more demanding in terms of noise,
linearity, and dynamic range!
With advancements of ADCs could be the architecture of choice in the
future
2007 H. K. Page 56
Typical Wireless Transmitter

Frequency
Synthesizer
D/A
D
S
P
PA
90
AGC
D/A
Transmit signal shipped from DSP to the analog front-end in the form of
I& Q signals
Signal converted to analog form by D/A
Lowpass filter provides signal shaping
In-phase & Quad. Components combined and then mixed up to RF
Power amplifier amplifies and provides the low-impedance output
2007 H. K. Page 57
Analog Filters in Super-Heterodyne Wireless

Transceivers
Image
RF
Amp
IF
Filter
Reject
Filter
AGC
Duplexer
A/D
90
AGC
A/D
Frequency
Synthesizer
D/A
PA
Digital
Signal
Processor
(DSP)
90
AGC
D/A
Filters
Function
Type
RF Filter
IF Filter
Base-band Filters
Image Rejection
Channel selection
Channel Selection
& Anti-aliasing for ADC
Ceramic or LC
SAW
Integrated Cont.-Time
or S.C.
2007 H. K. Page 58
Example: Dual Mode CDMA (IS95)& Analog Cellular Phone
2007 H. K. Page 59
Example: Dual Mode CDMA (IS95)& Analog

Cellular Phone
Baseband analog circuitry includes:
CDMA
4bit flash type ADC clock rate 10MHz

8bit segmented TX DAC clock rate 10MHz (shared with FM)
7th order elliptic RX lowpass filter corner freq. 650kHz
3rd order chebyshev TX lowpass filter corner freq. 650kHz
FM (analog)
8bit successive approximation ADCs clock rate 360kHz
5th order chebyshev RX lowpass filter corner frequency 14kHz
3rd order butterworth TX lowpass filter corner frequency
27kHz
2007 H. K. Page 60
Summary
Examples of systems utilizing
challenging analog to digital interface
circuitry- in the area of wireline &
wireless systems discussed
Analog circuits still remain the interface
connecting the digital world to the
real world!
2007 H. K. Page 61

Lecture 28 - Oversampled ADCs & Final Remarks

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EE247

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

Higher Order Modulators

Zeros of NTF (poles of H(z)) can be strategically positioned to

Oversampled ADCs Cont'd & Final Remarks

Example: Modulator Specification

The order L and oversampling ratio M are chosen

Oversampled ADCs Cont'd & Final Remarks

Noise Transfer Function, NTF(z)

% stop-band attenuation Rstop=80dB, L=5 ...

Chebychev 2 filter chosen

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

Loop filter peak voltages [V]

Internal Node Voltages

Maximum peak-topeak voltage swing

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

Node Scaling Example:

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

Node Voltage Scaling

Loop filter peak voltages [V]

Integrator output range reasonable for new parameters

Oversampled ADCs Cont'd & Final Remarks

Input Range Scaling

Oversampled ADCs Cont'd & Final Remarks

Scaled Stage 1 Model

Oversampled ADCs Cont'd & Final Remarks

Approach: linearize quantizer and use linear system theory!

Oversampled ADCs Cont'd & Final Remarks

Zeros of STF same as zeros of H(z)

Oversampled ADCs Cont'd & Final Remarks

Modulator z-Plane Root-Locus

Pole-locations inside unit-circle

Need Geff > 0.45 for stability

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

Effective Quantizer Gain, Geff

Effective Quantizer Gain

Oversampled ADCs Cont'd & Final Remarks

Be ware that signals

5th Order Modulator

Stable input range with margin ~ 1V

Oversampled ADCs Cont'd & Final Remarks

modulators of order greater than 2:

Cascaded (multi-stage) modulators

EECS 247 Lecture 28:

Oversampled ADCs Cont'd & Final Remarks

Replace the integrator in 1st order lowpass with a

Oversampled ADCs Cont'd & Final Remarks

Oversampled ADCs Cont'd & Final Remarks

Oversampled ADCs Cont'd & Final Remarks

Bandpass Modulator Dynamic Range

Bandpass resolution for order K is the same as lowpass

Oversampled ADCs Cont'd & Final Remarks