CSEITQUESTIONS.BLOGSPOT.

IN

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

UNIT-1
BOOLEAN ALGEBRA AND LOGIC GATES
16 mark question
1. state an postulates prove the postulates, theorems of Boolean algebra
2. use Quine MrVluscky method to obtain the minimal sum for the following
function F(X1,X2,X3,X44)=(0,1,3,6,7,14,15)
3. simplify the function using karnaugh map (i)F(ABCE)= (0,1,2,4,5,7,11,15) (ii)F(WXYZ)= (2,3,10,11,13,14,15)
1

4. state and prove demorgans theorm and expand the function F=((A+B)C+C D)
5. simplify
the
following
switching
function
using
karnaugh
map,
F(A,B,C,D)=
(0,5,7,8,9,10,11,14,15)+(1,4,13)
6. Simplify the boolen function using K-map and tabular mathods. Compare the mehods F(A,B,C,D)=
m(4,5,6,7,8) d(A,B,C,D)= m(11,12,13,14,15)
1
7. Implement using only NAND gates i)express the function f(x,y,z)=XY+XZ As a product of sum terms form
(ii) Express the following function as the minimal sum of productis using a K-map F(A,B,C,D)=
m(0,2,4,5,6,8,10,15)+ (7,13,14)
8. Implement the following with either NAND or NOR gate. Use only 4 gates. Only the normal inputs are
available
1
1
1 1
(i) d=WYX (ii)F=W XZ+W YZ+WXZY +X
9. What are codes? Explain the different types of codes with examples?
10. Using tabulation method simplify the Boolean function F(w,x,y,z)= (1,2,3,5,9,12,14,15) which has dont
care condition (4,8,11)
11. Reduce the Boolean function using K-map technique and implement using gates f(w,x,y,z)= (0,1,4,8,9,10)
which has the dont care condition (2,11).
12. Simplify the following Boolean function by using the tabulation method F=(0,1,2,8,11,14,15)
13. Simplify the following Boolean function F(w,z,y,z)= (1,3,7,11,15) that has the dont care condition (0,2,5)
14. Convert the following hexadecimal number to decimal (i) 1C (ii)A85 (iii)E5 (iv)B2F8
15. List out any basic rules that are used in Boolean algebra expression
16. Simplify the following Boolean function using tabulation method F(A,B,C,D)= m(0,2,3,6,7,8,10,12,13)
17. Simplify the following using tabulation method F(a,b,c,d)= (1,2,3,5,9,12,14,15)+ d(4,8,11)
18. Find the educed form of POS form of the following equation F(a,b,c,d)= m(1,3,7,11,15)+ d(0,2,5)
implement using NAND logic
19. Simplify the following using the quine-Mcclusky minimization technique D=f(a,b,c,d)= (0,1,2,3,6,7,8,9,10)
20. Minimize the switch function A(a,b,c,d)= (1,4,5,7,13)+ d(0,6,14,15) on a 4 variable karnaugh map
21. Express x+yz as the product of max terms
22. Find the MSP form of F(w,x,y,z)= (1-3,5-10,12-14) using the quine-mcclusky minimiztation technique
23. Simplify the following using map method F(a,b,c,d)= m(0,2,4,6,8,10,12,14) (ii)perform subtraction
on the following number using the 9s complement of the subtrahend a)5763-3145 b)59-9876 c)5200561
24. Simplify the following 5 variable Boolean expression using the QUINE-MCCLUSKY minimization technique
F(a,b,c,d,e)= (0,1,9,15,24,29,30)+d(8,11,31)
2 marks
1

CSEITQUESTIONS.BLOGSPOT.IN

6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.

CSEITQUESTIONS.BLOGSPOT.IN

1. What happens when all the gates in a two level AND-OR gate network is replaced by NOR
1
1
2. Implement Y=A+(B+C) +(AB)
1
3. If A and B are Boolean variable and if A=1 and (A+B) =0 find B
4. Express the switching function fAB =A in terms of minterms
11
5. Apply demorgans theorems to simplify (A+BC )
Express x+yz as the sum of minterms
What is prime implicannt
What are min-terms and max-terms
Why binary number system is used in digital systems?
Define the laws of Boolean algebra
For a switching is a function of n variables how many distinct minterms and max are possible
State two adsorption properties of Boolean algebra
Find the octal equivalent of the decimal number 64
Find the hexadecimal equivalent of the octal number 153.4
1
Define canonical form. Express F=BC +AC in a cannonical SOP form
Determine the decimal equivalent of binary .1101
Find the octal equivalent of hexadecimal number AB.CD
What is the advantage of biquinary code?
Find the hexadecimal equivalent of decimal number 256
What is mean by weighted and non-weighted coding
Convert A3BH and 2F3H into binary and octal respectively
Find the decimal equivalent of 1239
Find the complement of x+yz
State and prove consensus theorem
Implement AND and OR gate using NAND gates
Find the binary representation of decimal 125
1 1
Complement the express X(Y +Z )
1
1
Convert y=A+BC +AB+BCA
What is meant by essential prime implicant
1
1
Obtain the complent of f=wx +xy +wxy using demorgan theorm
1
Show that A+A B=A+B using the theorms of Boolean algebra
What is the advantage of grey codes over theb inary number sequence

UNIT-2
COMBINATION LOGIC
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

CSEITQUESTIONS.BLOGSPOT.IN

Define half adder and full adder

Define half subtractor and full subtractor
How logic circuits of a digital system are classified
What is a combinational circuit? Giva an example
Mention any two uses of HDL
What is logic simulation
What is the advantage of logic simulation
What is test bench
What is logid synthesis
How HDLs are classified
How the delay is specified interms of verilog HDL
2

CSEITQUESTIONS.BLOGSPOT.IN
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

Define system primitives

What is UDP
What is VHDL
Feature of VHDL
Define entity
Define VHDL package
What is meant by memory decoding
Write down the truth table of a half subtractor
Draw the half adder circuit
Write down the truth table of a full subtractor
Draw full adder circuit
What is meant by VHDL and what is its advantage
Write down the truth table of a full adder
Define combination logdic
Explain the design procedure for combinational circuit
Conver gray code 101011 into its binary equivalent
What are called dont care condition
Define magnitude comparator
What are the two steps in gray to binary conversion
What is HDL
Compare the serial and parallel adder
Define look ahead carry addition
What are the modeling techniques available to build HDL module
16 mark

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.

Define a BCD to Gray code converter. Use dont cares

Design a half adder and full adder circuits
Design a half subtractor and design a subtractor
Design a 4-bit binary to BCD code converter
Construct a 4-bit binary to gray code converter circuit and discuss its operation
Design a combinational circuit to convert excess-3 code to BCD code
Construct a full adder circuit and write a HDL program module for the same
Design a BDC adder to add two BCD digits
Design a combinational circuit that accepts 3 bit binary number and converts it to excess 3 code
Design a circuit to compare two four bit numbers
Design a gray to BCD code converter
Design a combination circuit to convert BCD code to excess-3-code
Design a combination logic circuit to compare two 2-bit binary numbers A and B and to generate the output
A<B,A=B, A>B
14. Design a full adder and full subtractor circuits using NAND and NOR gates respectively

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

UNIT-3
DESIGN WITH MSI DEVICES
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.

What is a decoder
What do you mean by encoder
What is a priority encoder
What is a multiplexer
Give application of MUX
How can a decoder be converted into a demultiplexer
1 1
Implement the logic function f=AB+A B using a suitable multiplexer
Explain how parity can be used for error detection
What is the difference between decoder and demultiplexers
What is a sequential circuit
How is the design of combinational and sequential logic circuits possible with PLA
Is the PAL same as the PLA? Justify or distinguish between them
Define priority encoder
What is meant by static and dynamic memories
What is FPLA
Name any two random access memories
Differentiate between SRAM and DRAM
What is PLA
Give any two application of PLAs
What is a decoder and obtain the realtion between the number of inputs n and outputs m of a decoder
List basic types of programmable logic devices
Define address and word
What are the types of ROM
What is programmable logic array?how it differs from ROM
What is field programmable logic array
Mention some major applications of multiplexers
Mention the uses of decoders
Write data flow description of a 2 to 1 MUX using condition operator
Implement the logic function f=(0,2,3,6) using a decoder
How can a multiplexer be used to convert 8 bit paralled data into serial form
What is the maximum range of a memory that can be accessed using 10 address lines?

16 marks
1. A combination circuit is defined by the function F1=m(3,5,7) F2 =m(4,5,7) implement the circuit with a PLA
having 3 inputs, 3 product terms and two outpus
2. Implement the following Boolean function using 8:1 MUX F(P,Q,R,S)= m (0,1,3,4,8,9,15)
1 1
1
1 1
3. Implement the following Boolean function using 8:1 multiplexer F(A,B,C,D)=A BD +ACD+B CD+A C D
4. Realize F(w,x,y,z)= (1,4,6,7,8,9,10,11,15) using 4-to-1 MUX
5. Tabulate the PAL programming table for the four Boolean function listed below. A(x,y,z)= (1,2,4,6) B(x,y,z)=
(0,1,6,7) c(x,y,z)= (2,6) D(x,y,z)= (1,2,3,5,7)
6. Implement the following Boolean function using a 8 to 1 multiplexer and 4 to 1 multiplexer F(A,B,C)= (0,1,5,7)
1 1
1
1 1
7. Implement the following Boolean function using 8:;1 multiplexer F(A,B,C,D)=A BD +ACD+B CD+A C D
8. A combinational circuit is defined by the function F1(A,B,C)= (3,5,6,7) F2(A,B,C)= (0,2,4,7) implement the
4

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

circuit with a PLA

9. A combination circuit is described by the functions F1=m(3,4,5,7,10,14,15), F2=m(1,5,7,11,15) implement the
circuit with a PLA having 4 inputs 6 product terms and two outputs
10. Write the structural VHDL description for 2 to 4 decoder and explain it in detail
11. Design and explain the working of a 1 to 8 demultiplexer
12. Draw a 4:1 MUX and implement the following function F=(0,1,2,4,6,9,12,14) write a HDL program for 2 to 1
MUX
13. Write the structural VHDL description for 4 to 1 multiplexer also draw the internal diagram of the multiplexer
14. A combinational circuit is defined by the functions F1=m(3,5,7) F2=(4,5,7) implement the circuit with a PLA
having 3 inputs 3 product terms and two outputs
15. Implement the Boolean function using 4 to 1 MUX F(w,x,y,z)= (1,2,3,6,7,8,11,12,14)
16. A combitational circuit is defined by the functions F1=m(1,3,5) F2=m(5,6,7) implement the circuit with a
PLA having 3 inputs and 3 product terms and two output

UNIT-4
SYNCHRONOUS SEQUENTIAL LOGIC
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.

How logic circuits in a digital system are classified?

What is a sequential circuit? Give a example
Distinguish the classification of sequential circuits and define them
Distinguish between latch and flip-flop
Why D latch is called transparent latch
What is triggering
What is meant by the term edge triggered
What is state equation
What is state table
What is state diagram
What is meant by the term state-reduction
Write the flip-flop excitation tables for JK and T FF
Mention the two types of circuit that include flip-flop
What is register
What is counter
What is a shift register
Define binary counter
Define ripple counter
Define binary count-down counter
What is decade counter
List out at least four applications of FFs
What are the principal between synchronous and asynchronous counters
Distinguish between combinational logic circuits and sequential logic circuits circuits
What are the advantages of shift registers
What are the various types of triggering of FF
Derive the characterstic equation of T flip flop
What is the minimum of Flip flop required to build a counter of modulus of 8
Draw the logic diagram for T flip flop
What is modulo n counter
How many states are there in a 3 bit ring counter? What are they?
5

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

31. What are the states of 4 bit ring counter

32. Draw the internal circuit of a NOR gate latch and derive the truth table
33. Discuss the operation of SR flip flop with help of the state diagram
16 marks
1. Using D flip flops design a synchrounous counter which counts in the sequence binary 0 to 7 then 0
2. Using JK flip flop design a synchronous counter which counts in the sequence 0 to 7 then 0
3. Design a binary counter using T flip flops to count pulses in the following sequence 0 t0 7 then 0 , next order
0,4,7,2,3,0
4. Explain the working of master slave flip flop
5. Write short notes on the following slip flops i)JK ii)D iii) T flip flop
6. Explain the functional operation of a binary ripple counter with its logical diagram
7. Draw a 4 bit serial in serial out shift register and draw its waveforms
8. Draw a 4 bit serial in parallel out and explain its operation
9. What are the general capabilities of universal shift register? And write the HDL code for the same
10. Explain the operation of BCD counter
11. Design an asynchronous BCD down counter using JK flip flop and verify its operation
12. Design a synchronous mod-8 down counter and implement it
13. Design and explain the working of a up down counter
14. Explain the operation of D type edge triggered flop flop and how can a d flip flop converted into a T flip flop
15. Using JK flip flop design a synchronous counter which counts in the sequence 2,6,1,7,5,4 and repeat
16. Design a mod 5 asynchrounous counter draw the wave form
17. Using RS flip flop design a paralled counter which counts in the sequence 0,3,5,6,1,2,0 and repeat

UNIT-5
ASYNCHRONOUS SEQUENTIAL CIRCUITS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.

Define asynchronous sequential circuit

State the difference between the synchronous and asynchronous sequential circuits
What is a fundamental mode asynchronous sequential circuits
What is a cirtical race?why should it be avoided
Define cycle
Define hazard
Define race, critical race and non-critical race
Define a primitive flow tables
What is static 1 hazard
Define static hazard
Define glitch
What is a dynamic hazard
What is essential hazard
What are mearly amd moore machine
What is a race
What is a shared row state assignment
Mention any advantage and disadvantage of asynchronous sequential circuits
Define static 0-hazard , static 1-hazard and dynamic hazard
6

CSEITQUESTIONS.BLOGSPOT.IN
19.
20.
21.
22.
23.
24.

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

What is the difference between mealy machine and moore machine

Explain the procedure for state minimization
What is pulse mode circuit
What are the types of hazards
What are the assumptions for pulse mode circuit
What are the assumptions for fundamental mode circuit

16 marks
1.
2.
3.
4.

6.
7.

8.

9.
10.
11.

Give examples for critical race and cycle and explain

Describe the hazards with neat circuit diagram
Give the hazard free realization for the following functions f(a,b,c,d)= m(0,2,6,7,8,10,12)
Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output z. when X1=0 the
output is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will
remain 1 until X1 returns to 0.

5. AN asynchronous sequential circuit has two internal states and one output. The excitation and output
function
describing the circuit are as follows
Y1=x1x2+x1y2+ x2y1
Y2=x2+x1y1y2+x1y1
Z=x2+y1
Give a hazard free realization for the following Boolean function F(A,B,C,D)= m(1,3,6,7,13,15) and summarize
the design procedure for asynchronous sequential circuit
An asynchronous sequential circuit is described by the following excitation and output function
Y=X1X2+(X1+X2)Y i)draw the logic diagram ii) derive the transition table and output map iii) describe the
behavior of the circuit
An asynchronous network has twoinputs and one output. The input sequence X1X2=00,01,11 causes the output
to become 1. The next input change then causes the output to return to 0. No other input sequence will
produce a 1 output. Construct the state diagram using primitive flow table.
Design a circuit with inputs A dn B to give an output Z equal to 1 when AB=11 but only if A become 1 before B,
by drawing total state diagram, primitive flow table and output map in which transient stae is included
Design a circuit with primary input A and B to give an output Z equal to 1 when a become 1 if B is already 1.
Once Z=1 it will remain so until a goes to
Draw waveform diagrams, total state diagram, primitive flow table for desigining the circuit
An asynchronous circuit described by the following excitation and output function Y=X1X2+(X1+X2)Y Z=Y
Draw the logic diagram of the circuit. Derive the transition table and output map. Describe the behavior of
the circuit

12. Design a asynchronous sequential circuit with 2 inputs X and Y and with one output Z whenever Y is 1 inmput X
is transferred to Z. when Y is 0 the output does not change for an change in X. use SR latch for implemention
of the circuit.
13. What is a merger graph. How it is used to reduced state in the incompletely specified state.
14. What are the problems in asynchronous circuits and what are essential hazards and static hazards how it can
be eliminated.
7

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

CSEITQUESTIONS.BLOGSPOT.IN

15. Design T flip flop from logic gates

16. Give the hazard free realization for the following function i)NAND ii) NOR gates f(a,b,c,d)=m (1,5,7,14,15)
17. Design a sequence detector circuit with a single input line and a single output line. Whenever the input
consists of the sequence 101, the output should be 1 for example if the input is 001100101then the ouput is
000000101.. in other words, over lapping sequence are allowed. Use any type of flip flop
18. Give the hazard free realization for the following function f(a,b,c,d)= m(1,3,6,7,13,15)
19. Summarize the design procedure for asynchronous sequential circuit
1
1
1
20. An asynchronous circuit described by the following excitation and output function X=(Y1.Z1 W2)X+(Y1 Z1W2 )
1
S=X DRAWS the logic diagram of the circuit. Derive the transition table and output map. Descirb the behavirour
of the circuit
21. Explain essential, static and dynamic hazards in digital circuit. Give the hazard free realization for the following
functions F(I,J,K,L)= m(1,3,4,5,6,7,9,11,15)