When to transmit a packet?

If multiple stations want to transmit their packets over a common channel, appropriate rules are needed to share the channel and to let each station determine when it may send
its packets. This problem is tackled by medium access control (MAC) protocols, discussed in Section 37.3.
How to cope with channel errors? The topic of error control is briefly touched in Section 37.4.
Which packet to transmit next? This is the problem of packet scheduling.
How to protect the receiver against too much data sent by the transmitter? This is the problem of flow
control.
This chapter surveys framing and synchronization, MAC protocols and error control in some detail in
the following sections. Some references discussing packet scheduling algorithms are [57, 5961, 58,
Chapter 9]. Flow control algorithms are explained in [20].

37.2

Framing and Synchronization

The problem of synchronization is related to the transmission of information units (packets, frames)
between a sending and a receiving entity. In computer systems, information is usually stored and
processed in a binary digital form (bits). A packet is formed from a group of bits and shall be transmitted to the receiver. The receiver must be able to uniquely determine the start and end of a packet as well
as the bits within the packet.
The transmission of information over short distances, for instance, inside the computer, can be done
with parallel transmission. Here, a number (say, 64) of parallel copper wires transport all bits of a 64-bit
data word at the same time. In most cases, one additional wire transmits the common reference clock.
Whenever the transmitter has applied the correct voltage (representing a 0 or 1 bit) on all wires, it signals this by sending a sampling pulse on the clock wire toward the receiver. Conversely, on receiving a
pulse on the clock wire, the receiver samples the voltage levels on all data wires and converts them back
to bits by comparing them with a threshold.
This kind of transmission is fast and simple, but cannot span large distances, because the cabling
cost becomes prohibitive. Therefore, the data words have to be serialized and transmitted bit-by-bit on
a single wire.1

Bit Synchronization
The spacing of bits generated by the transmitter depends on its local clock. The receiver needs this clock
information to sample the incoming signal at appropriate points in time. Unfortunately, the transmitters
and receivers clocks are not synchronized, and the synchronization information has to be recovered from
the data signal; the receiver has to synchronize with the transmitter. This process is called bit synchronization. The aim is to let the receiver sample the received signal in the middle of the bit period in order to be
robust against the impairments of the physical layer, like bandwidth limitation and signal distortions. Bit
synchronization is called asynchronous if the clocks are synchronized only for one data word and have to
be resynchronized for the next word. One common mechanism used for this uses one start bit preceding
the data word and one or more stop bits concluding it. The Universal Asynchronous Receiver/Transmitter
(UART) specification defines one additional parity bit that is added to the 8 data bits, leading to the transmission of 11 bits in total for every 8 data bits [3]. The upper row in Figure 37.2 illustrates this.
For longer streams of information bits, it is necessary to synchronize the receiver clock continuously.
The Digital Phase-Locked Loop (DPLL) is an electrical circuit that controls a local clock and adjusts it to
the received clock that is extracted from the incoming signal [20]. To recover the clock from the signal,
sufficiently frequent changes of signal levels are needed. Otherwise, if the wire shows the same signal level
for a long time (as may happen for the Non-Return to Zero (NRZ) coding method, where bits are directly
1
The term wire is actually used here as a synonym for a transmission channel. Therefore, it could also be a wireless
or ISDN channel.

BY#2#0RESS,,#

mapped to voltage levels), the receiver clock could drift away from the transmitter clock. The Manchester
encoding that is shown in the second row of Figure 37.1 ensures that there is at least one signal change
per bit. Every logical 1 is represented by a signal change from one to zero, while a logical 0 shows the
opposite signal change. The internal clock of the DPLL samples the incoming signal with a much higher
frequency, for instance, 16 times per bit. For a logical 0 bit that is arriving exactly in time, the DPLL
receives a sample pattern of 0000000011111111. If the transition between the 0 and 1 samples is not

NRZ

Manchester

Diff. Manchester

1 means no level change

0 means level change

FIGURE 37.1 NRZ, Manchester, and differential Manchester codes.

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

UART character (11 bit)

Start, Stop Start/Stop bit
D7D0
Data bits
SD1

DA

SA

FC

FCS

ED

Control frame (no data)

SD2

DA

SA

FC

Data

FCS

ED

Fixed data length (8 characters)

SD3

LE

LEr

SD3

SA

DA

FC

SD1SD3
DA, SA
FC
FCS
LE
LEr
ED

Data

Variable length data frame (0249 characters)

FIGURE 37.2 DIN 19245 Profibus: character and selected frame formats.

BY#2#0RESS,,#

Start delimiter
Destination, Source address
Frame Control byte
Frame Check Sequence (CRC)
Length Field
Length Field repeated
End Delimiter

FCS

ED