1992

IEEE SENSORS JOURNAL, VOL. 8, NO. 12, DECEMBER 2008

Single-Wafer-Processed Self-Testable High-g

Accelerometers With Both Sensing and Actuating
Elements Integrated on Trench-Sidewall
Xinxin Li, Lei Gu, Yuelin Wang, Senior Member, IEEE, and Heng Yang

AbstractA single-wafer-processed highpiezoresistive

accelerometer is reported. The microsensor has an in-plane
self-caging cantilever configuration, in which an electrostatic
self-testing function is integrated on-chip. Both the sensing
piezoresistors and the self-test actuating electrodes are integrated
on vertical sidewalls of the laterally deflecting cantilever. For
single-wafer-based fabrication of the self-testable piezoresistive
accelerometer, a trench-sidewall micromachining technology is
developed, which is capable of integration of both boron-diffused piezoresistive sensors and electrostatic actuators on deep
trench sidewalls. In addition, the technology can realize electrical continuity from the vertical trench-sidewall to the wafer
surface. After design and fabrication of the accelerometers for
a 200 000 g measure-range, characterization was performed to
evaluate the developed trench-sidewall integration technology
and to test the self-testable high- accelerometers. A linear I-V
relationship for the sidewall-diffused piezoresistor is measured
with satisfactory sidewall-to-surface electric-transfer properties.
The electrical isolation between adjacent elements on the sidewall
shows a breakthrough voltage of about 55 V. Moreover, with the
single-chip integrated lateral-actuating structure, both static and
dynamic self-testing functions are realized. The measurement of
the accelerometer results in a sensitivity of about 1 V/g/3.3 V,
noise-limited vibration resolution of about 1 g and zero-point
temperature drift of lower than 100 ppm/ C.
Index TermsPiezoresistive accelerometer, electrostatic
self-test, in-plane lateral cantilever, trench-sidewall micromachining, single-wafer-based microelectromechanical integration.

I. INTRODUCTION

INCE the first micromachined accelerometer was formed

in 1979 [1], this kind of inertial sensor has been intensively developed in the following two decades [2]. At the
early stage, most of the micromachined accelerometers, with
either piezoresistive or capacitive sensing scheme, were fabricated by conventional bulk micromachining techniques such
as anisotropic etching and wafer bonding, etc. [3], [4]. An
out-of-plane vertical sensing configuration was frequently used
for the developed sensors, with occasional exceptions that
Manuscript received July 17, 2007; revised September 11, 2007; accepted
September 11, 2007. Current version published November 12, 2008. This work
was supported by the Chinese 973 Program (2006CB300405) and 863 Program (2006AA040104). X. Li thanks the NSFC Projects (No. 60725414 and
No. 60721004) for the support. The associate editor coordinating the review of
this paper and approving it for publication was Prof. William Tang.
The authors are with the State Key Lab of Transducer Technology, Shanghai
Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China (e-mail: xxli@mail.sim.ac.cn).
Digital Object Identifier 10.1109/JSEN.2008.2006707

employed complicated wet etching processes to form in-plane

lateral accelerometers [5], [6]. For the out-of-plane sensing
scheme, multiwafer bonded structures were generally used to
realize over-range stop and self-test actuation. Obviously, the
multiwafer sensor structure does not facilitate integration with
interface circuits. For solving the problem, surface micromachined capacitive accelerometers were then developed that
featured better integration compatibility with readout circuits
[7]. However, piezoresistive accelerometers, the major complement to its capacitive counterparts, are difficult to fabricate
with surface micromachining technology.
Along with development of inductively coupled plasma (ICP)
reactive ion etching (RIE) technology [8], deep-trench-etching
based silicon bulk micromachining has been widely applied
in microelectromechanical systems (MEMS) [9]. Compared
with surface micromachined structures, much thicker mechanical structures can be fabricated by using deep RIE. More
importantly, the MEMS configuration of in-plane lateral deflection, which has been widely used in surface-micromachined
structures, can also be realized with the deep-RIE-based bulk
micromachining technology. Compared with surface-micromachined structures, the deep-RIE-based in-plane lateral MEMS
configuration features higher aspect ratio, less cross-sensitivity
in the vertical direction, heavier proof-mass, and much easier
structural-release. In addition to various types of capacitive
accelerometers and gyroscopes fabricated with deep RIE [2],
piezoresistive accelerometers can also benefit much from deep
RIE technology. In contrast to the conventional out-of-plane
vertical-sensing configuration, deep-RIE-formed piezoresistive
accelerometers can be constructed with an in-plane lateral
cantilever structure. Two typical structures were reported in
[10] and the serial publications of [11][13]. For the research
in [10], the sensing cantilever is defined with a deep trench to
form a self-caging structure. A disadvantage of the work lies
in that the piezoresistors were put on the top surface of the
cantilever. The maximal stress, located at the cantilever sidewall, was not used for piezoresistive sensing, thereby, leading
to a low piezoresistive sensitivity. In the work of [11][13], the
piezoresistors were formed on one of the two trench sidewalls
of the laterally deflecting cantilever. Using silicon on insulator
(SOI) wafers, oblique ion implantation with an angle of 31
was processed twice to sequentially form the piezoresistor on
one sidewall of the trench and the heavy-doped return current
path on another sidewall. Besides that the SOI wafers are
expensive, the oblique implantation is not a standard method
that therefore increases process complexity. Moreover, the ion

1530-437X/$25.00 2008 IEEE

LI et al.: SINGLE-WAFER-PROCESSED SELF-TESTABLE HIGH- ACCELEROMETERS WITH BOTH SENSING AND ACTUATING ELEMENTS

implantation needs to be repeatedly processed to complete

the sidewall doping. For a straight cantilever structure like in
[11], the oblique implantation has to be processed twice. If
the microstructure to be doped at its trench-sidewall takes a
rectangular shape, the ion implantation has to be sequentially
processed four times, with the inclined angles for the four
directions, respectively. If a microstructure takes circular or
ring shape, uniform trench-sidewall doping is difficult to be
achieved, even though the oblique implantation is repeated
many times.
From another point of view, self-test is an important function for many accelerometer applications. For example, the
accelerometer for vehicle airbag has to be checked every time
the motor is ignited. Force balanced capacitive accelerometers
are naturally enabled for electrostatic self-testing. However,
self-test of a piezoresistive accelerometer has to be completed
by an extra actuating element. Conventional piezoresistive
accelerometers with vertical-sensing configuration use a multilayer bonded structure to realize electrostatic self-test [14]. For
single-chip in-plane piezoresistive accelerometers, however,
self-test is quite difficult. For realizing self-test in a single-wafer
in-plane microstructure, the fabrication must enable integration
compatibility between piezoresistance and electrostatic actuation. To the authors knowledge, there has been no such kind of
work reported in the literature.
In the present research, a novel piezoresistive high- accelerometer is developed. The sensor has a single-chip in-plane
cantilever configuration. In addition, the piezoresistors are
fabricated on the sidewall surface of the deep trench, and
the electrostatic actuating elements are integrated on the
trench sidewall for self-test. The proposed accelerometers are
fabricated with a newly developed trench-sidewall micromachining technique, with which both the piezoresistors and the
self-testing actuators can be integrated on deep-RIE-formed
trench-sidewalls. The sensor design, fabrication and test are
described as follows.
II. SENSOR DESIGN
With the schematic shown in Fig. 1, an in-plane lateral-deflecting cantilever structure is designed for the accelerometer.
The cantilever is self-caged by the surrounding deep trenches.
When the cantilever laterally deflects under an applied acceleration, bending stress will occurs with the maximal value located at the vertical sidewall surface of the base segment of the
cantilever. Therefore, at the maximal stress location of the cantilever, two peozoresistors are put, one on each side, for differential sensing. For electrostatic self-test, the movable driving
electrodes are also put on both sidewalls of the cantilever. The
trench gap is used as driving space with the fixed electrode on
the vertical frame sidewalls. For a high- measure-range, the
cantilever is designed to be sufficiently stiff but that makes it difficult for electrostatic actuation. Therefore, the driving plates are
placed near the end of the cantilever to provide a large force-moment. Both the piezoresistors and the electrostatic self-testing
electrodes are formed by boron diffusion on the trench-sidewalls. A more negative electric potential than the n-type substrate is supplied to the sensing and actuating elements. This

1993

Fig. 1. Schematic of an in-plane lateral-deflective cantilever for high-g piezoresistive accelerometers with both the piezoresistors and the electrostatic selftesting actuators integrated on the deep trench sidewalls.

design aims to ensure electrical isolation by the reverse-biased

p-n junctions along the trench-sidewalls. Moreover, electric isolation has to be performed to define and isolate different sensing
and actuating elements on the trench-sidewall. Refilled by insulating SiO , electrically isolated trench-bars are used to cut
across the p-n junctions. With the edges protruding from the
sidewalls, the trench-bars electrically isolate the adjacent elements along the sidewalls.
For electrical interconnection, there should be a method to
electronically connect the vertical sidewall to the wafer surface.
is selectively doped on the
Prior to the cantilever formation,
wafer surface. Then contact holes are opened for metal interconnection. When the cantilever structure is shaped by deep trench
cross secetching, the heavily doped areas are cut by the
tions exposed at the vertical surface of the cantilever. Along
with the following boron diffusion on the sidewall, the sidewall-to-surface electric transfer is simultaneously completed via
the doping overlaps between the sidewall diffusion and the
surface doping.
For a 200 000 g measure-range, the cantilever-shaped accelerometer is designed according to the theoretical analysis
orientation of a
detailed in [10] and [15]. Along the
(100) wafer, the cantilever is designed as
m in
m in width (i.e., the trench etching depth) and
length,
m in thickness (i.e., the lateral width from top-view).
The sidewall piezoresistors are integrated at the base segment of
m. Composed
the cantilever, with the doped length as
of about five squares of resistance, the boron-diffused sidewall
piezoresistor has a targeted resistance value of about 1 k . At
this doping level, the corresponding piezoresistive coefficient
is about 1 10 Pa . The top-view layout of the
value
sensor is schematically shown in Fig. 2(a). To form a fully
sensitive Wheatstone bridge, two cantilevers are oppositely laid
each other in the sensor chip. Under an acceleration of , the

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IEEE SENSORS JOURNAL, VOL. 8, NO. 12, DECEMBER 2008

bending stress is located at the sidewall surface of the base segment of the laterally deflecting cantilever. Both theoretical analysis and finite-element method (FEM) simulation using the software of ANSYS7.0 have confirmed that for the designed sensitivity the maximum stress (located at the cantilever base) is
about 190 MPa that is safely lower than the rupture stress.
For electrostatic self-testing, two actuating electrical plates
are designed and formed on both sides of the cantilever. The
movable plates on each cantilever are electrically connected to
the common terminal of the two piezoresistors by doping
on the surface of the cantilever-end segment. Corresponding to
the top-view layout in Fig. 2(a) and (b) shows the circuit diagram for the self-testable accelerometer. For static self-test, a
can be applied to one side of the cantilever to
DC voltage
,
generate an electrostatic force of
where is the trench gap-distance and is dielectric constant of
is set herein to secure the isolation by
air. A negative value of
the reversed p-n junction. The force can be approximately considered acting at the middle point of the self-testing electrode
and, thus, the force-moment induced piezoresistive sensitivity
can be expressed as
(4)

Fig. 2. (a) Top-view layout of the accelerometer that consists of two cantilevers to form a fully sensitive Wheatstone bridge. The wire-bonding pads
for the sensing bridge and the self-testing electrodes are numbered. (b) Electric
schematic diagram for both sensing and self-testing with the corresponding
wire-bonding pads denoted.

piezoresistive sensitivity of the accelerometer is theoretically

calculated as
(1)
where is density of silicon. Here, the average bending stress
at the piezoresistor location is
(2)
with the Wheatstone bridge powered by 3.3 V, the sensor output
sensitivity is 0.95 V/g, i.e., the output voltage can be 190 mV
for the measure range of 200 000 g. The resonant frequency of
the cantilever lateral deflection mode can be calculated as
(3)
GPa is youngs modulus of silicon. The fullwhere
range output voltage is limited by the rupture stress of singlecrystalline-silicon micromechanical structures that is normally
set as about 400500 MPa [13]. In our design, the maximum

The electrostatic actuation can be implemented either on single

cantilever or on the both cantilevers. The signal is readout from
the Wheatstone bridge to realize the self-testing. Similarly, a
sin t, can be apcouple of DC biased AC voltage
plied on the two electrodes of one cantilever, respectively, to
perform a differential dynamic self-test. For dynamic movement
of the cantilever, the squeeze-film damping between the cantilever and the frame is considered dominating the air-damping
limited quality factor [15]. For adequate driving force across
the trench gap, the trench gap of the cantilever should be designed as narrow as possible. However, a mechanical stop for
over-range protection and squeeze-film damping for dynamic
control should be taken into consideration. 4.5 m trench width
for the deflective cantilever was finally designed, while the deflection of the cantilever-end under an acceleration of 200 000 g
was calculated as about 4 m.
III. FABRICATION
A trench-sidewall micromachining technology is developed
for the formation of the self-testable accelerometers. The
technology is capable of single-wafer-based integration of both
piezoresistive sensors and electrostatic actuators on trench
sidewalls. Therefore, the proposed in-plane piezoresistive
accelerometers can be on-chip integrated with the self-testing
actuators. Fig. 3 shows the process flow, with the cross-sectional
and
series steps, (a) and (b), cut along the dash line of
in Fig. 1, respectively. The process
the dotted line of
flow is described as follows.
1) The process starts from (100) n-type silicon wafers
cm resistivity. Prior to the formation of the
with 15
-oriented cantilevers, deep trenches perpendicular to
the cantilever direction are formed by ICP deep RIE. An
Alcatel 601E etching system is used for the trench etching.
The trench is 50 m in depth and 3.5 m in width. After

LI et al.: SINGLE-WAFER-PROCESSED SELF-TESTABLE HIGH- ACCELEROMETERS WITH BOTH SENSING AND ACTUATING ELEMENTS

1995

Fig. 3. Process steps for fabricating the accelerometers. The 3 0 a and 3 0 b cross sections are cut along the dash line of A 0 A and the dotted line of
B 0 B in Fig. 1, respectively.

Fig. 4. SEM images showing the cross-sectional evolution of a refilled-trench

for sidewall electrical isolation. With the top and the bottom parts shown in (a)
and (b), respectively, the trench is partly filled by LPCVD polysilicon. Then, the
trench is refilled with the volume-expansion by oxidizing the poly silicon into
SiO . The top and the bottom parts of the fully refilled trench are shown in (c)
and (d), respectively.

the trench etching, the deep RIE induced fluoride deposit

on the trench sidewalls needs to be stripped by a cleaning
sequence detailed as follows. The wafer is first cleaned
with an EKC265 cleaning solution at 70 for 30 min. Then,
oxygen-plasma dry etch is processed for 10 min. After the
cleaning sequence, a 300-nm-thick SiO layer is thermally
grown. The trenches are partly refilled with a layer of
polysilicon deposited by low-pressure chemical vapor
deposition (LPCVD). About 850-nm-thick polysilicon is
deposited at 630 C. The cross-sectional SEM images in

Fig. 4(a) and (b) show the top part and the bottom part of
a partly refilled trench, respectively.
2) The deposited polysilicon is oxidized. In this way, the
trenches are fully refilled by volume expansion during the
polysilicon oxidization [16]. We never tried to directly
deposit and fill LPCVD SiO film into the trench. Unfortunately, the upper-edge area was always blocked before the
whole trench was fully refilled, which caused a void in the
trench. It is well known that the volume will be expanded
to 2.27 times when silicon is oxidized into SiO . With this
oxidation of polysilicon, we found that the trenches can be
void-free refilled. In order to lower the residual stress of
the SiO film, the oxidization temperature is set as 980 C.
Shown in the cross-sectional SEM images of Fig. 4(c)
and (d) are the top part and the bottom part of the fully
refilled trench, respectively. It can be seen clearly that the
insulated trench is void-free. During the polysilicon oxidization, an SiO layer is simultaneously formed on both
surfaces of the wafer. After patterning at the backside,
TMAH anisotropic etching is processed from the backside
to open the cantilever regions. The etching is stopped
when the bottom of the insulated trenches are exposed.
For the 400 m-thick wafers, the backside etching depth
is about 350 m. After the backside etching, the front-side
SiO is removed by buffered HF. At the small areas of the
refilled trenches, the SiO is protected from etching by
patterned photoresist.
3) A 300 nm-thick SiO layer is thermally grown on both
surfaces. After patterning at the front-side, heavy boron
doping is selectively formed on the top surface so that electric connectivity can be established from the trench sidewall to the wafer surface. Either implantation or impurity

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IEEE SENSORS JOURNAL, VOL. 8, NO. 12, DECEMBER 2008

Fig. 5. The core of the trench-sidewall technology is sketched, including sidewall boron diffusion, electric isolation by SiO -trench and the sidewall-to-surface electric transfer via the doping overlaps.

predeposition can be used for this

doping. During the
drive-in step, oxygen gas is introduced and a new SiO
layer is grown for covering the
areas. The doping area
has a sheet resistance of 1020 /square.
4) After the contact-holes are opened for Al interconnection,
the trenches for shaping the cantilevers are ICP etched
with a patterned photoresist layer as etching mask. The
trench etching is stopped automatically by the backside
SiO -layer. These structural trenches cut across the preareas, with the
cross sections exviously doped
posed at the sidewall-surface. The structural trenches also
cut across the previously formed SiO -refilled trenches,
ensuring that the edges of the insulated-trenches are protruding at the sidewall-surface for electrical isolation.
5) The surface cleaning process described in (1) is used again
to strip the fluoride compound deposited during the ICP
trench etching. Then, the vertical sidewalls of the structural
trenches are boron diffused. Both sides of the wafer are
protected from diffusion by the existing SiO layer, with
the exception of the contact holes. The boron diffusion
has little influence on the contact resistance, as the areas
doped already. The sidewall boron-diffusion
have been
has a targeted sheet resistivity of about 200 /square and
the typical p-n junction depth of 0.70.8 m. With the
trench sidewall boron-diffused, both the piezoresistors
and the self-testing electrodes are formed at the sidewall
surface. Adjacent elements on the sidewall are electrically
isolated by a combination of the SiO -insulated trenches
and the boron-diffusion-formed p-n junctions along the
sidewalls. Electrical continuity from the trench sidewall
to the wafer surface is simultaneously completed via the
overlapping joints between the boron diffused sidewall and
areas at the wafer surface. During
the previous doped
the drive-in stage, nitrogen gas is first induced and then
switched to oxygen at the last few minutes in order to grow
a thin SiO layer on the sidewall surface for passivation
of the sidewall-diffused piezoresistors. For better understanding of the trench-sidewall integration technology,
the core of the technology is sketched in Fig. 5, including
the sidewall boron diffusion, the electrical isolation by

Fig. 6. SEM images showing the fabrication results. (a) A whole sensor-chip
consists of two oppositely laid cantilevers. (b) Close-up view of the base
segment of the cantilever. The SiO -refilled trenches are protruding from the
sidewall. (c) and (d) Close-up views of the free end and the middle part of
the cantilever, respectively. The self-testing electrodes are placed between the
SiO -trenches of the two parts.

SiO -trench, and the sidewall-to-surface electrical transfer

via the doping overlaps.
6) RIE is used to remove the thin SiO layer in the contact
holes, while the relatively thicker SiO layer at other areas
is retained. For interconnection, Al is sputtered and patterned with a liftoff technique. After sintering, backside
plasma-etching is processed to remove the SiO layer, and
free the cantilevers.
The SEM image in Fig. 6(a) shows a fabricated sensor chip,
while Fig. 6(b)(d) show the close-up views of the base part, the
middle, and the free end of the cantilever, respectively. Between
two adjacent sidewall-elements, four SiO -refilled trench-bars
are laid in series (with a common SiO cap) to secure electrical
isolation. In fact, it has been recently found that, in most applications, one insulating trench is enough for isolation. Fig. 6(b)
shows the SiO -trench-edges protruding on the vertical sidewall
of the cantilever base. The self-testing actuator is between the
insulated trenches shown in Fig. 6(c) and (d), with the top-view
micrograph of the actuator part shown in Fig. 7(a). The backside
view of the cantilever base part is shown in Fig. 7(b), where the
SiO -refilled trenches are exposed.
IV. TESTING RESULTS
For operation of the accelerometer, the n-type substrate
should be connected to the highest electric potential to ensure
reverse bias of the p-n junctions along the trench sidewalls. In
other words, a lower potential than the substrate is supplied
to the sidewall-integrated sensing and actuating elements
to prevent current leakage. The electric properties of the
trench-sidewall elements are tested at first. Fig. 8(a) shows the
characteristics of a sidewall-diffused piezoremeasured
sistor. For this measurement, the aluminum lines connecting
the neighboring piezoresistors of the Wheatstone bridge are

LI et al.: SINGLE-WAFER-PROCESSED SELF-TESTABLE HIGH- ACCELEROMETERS WITH BOTH SENSING AND ACTUATING ELEMENTS

1997

Fig. 7. (a) Front-side micrograph shows the actuator layout for differential selftesting. (b) Backside micrograph is taken near the base segment of the cantilever,
showing the exposed bottom of the SiO -trenches.

Fig. 9. Measurement results for self-test. (a) Double-cantilever static

self-testing output (without amplification) responds to DC driving voltage,
showing a good agreement with theoretical analysis. (b) 3.2 mV resonant peak
and 96.6 kHz resonant frequency are obtained by single-cantilever dynamic
self-testing. 10 cos ! t (V) differential actuation is biased by DC 15 V. The
self-testing results agree well with design.

Fig. 8. Measured trench-sidewall electrical properties of the fabricated

accelerometers. (a) Linear I-V relationship is measured for a sidewall piezoresistor with the sheet resistance of about 240
/square. (b) About 55 V
breakthrough voltage is measured between two facing electrostatic plates.

scraped and broken by a metal probe tip. A linear

relation
is obtained within a DC voltage range of 10 V. The uniformity
of the sidewall diffusion is evaluated by testing the resistance
value of the different piezoresistors. The nonuniformity in a

4-inch wafer is generally within 6%. Typical resistance value

of the piezoresistors was found to be 1.22 k , i.e., the sheet
resistance is about 240 /square, slightly larger than our target
of 200 /square. Limited impurity transportation and diffusion
in the narrow trenches are considered the main reasons for the
lower boron concentration. Further study will be conducted for
more precise sidewall doping control. When the two piezoresistor terminals are exchanged with each other, the linear
relationship is also measured with the same slope. The results
reveal that ohmic contact is realized at the two piezoresistive
-diffused
terminals, and the electrical continuity from the
sidewall to the -doped wafer surface is satisfactory. Fig. 8(b)
shows the measured electrical breakthrough behavior between
two facing self-testing electrodes. The trench-sidewall electrical isolation is realized by combination of both the negatively
biased p-n junctions and the SiO -refilled trench-bars. About
55 V breakthrough voltage is measured that is enough for most
sensing and self-testing operations.
Fig. 9 shows the self-testing results of a 200 000 g-range
shock accelerometer. The electric schematic diagram for both
sensing and self-testing is shown in Fig. 2(b). Terminal 3 is connected to DC 3.3 V, while Terminal 8 is grounded. The sensing

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IEEE SENSORS JOURNAL, VOL. 8, NO. 12, DECEMBER 2008

Fig. 11. Noise spectrum scanning results, with a 15 g acceleration generated

by a shaker inserted in the spectrum for evaluation of resolution.
Fig. 10. Measurement results for high-g sensing. The Wheatstone bridge of the
accelerometer is supplied by 3.3 V. A half-sine-wave output is measured for responding to a dropping-hammer induced 10 000 g elastic shocking acceleration.
Sensitivity of 0.97 V/g/3.3 V is calculated from the measurement data.

signal of the Wheatstone bridge is readout from Terminals 4 and

) is applied to Ter7. The static self-test voltage (denoted as
minals 1 and 6. The electrical potentials of the two actuating
electrodes at the two cantilevers are provided via Terminals 3
and 8, respectively. Therefore, the driving voltage between TerV and the voltage between Termiminals 6 and 3 is
, respectively. The electrostatic self-testing
nals 1 and 8 is
force for the two cantilevers was calculated individually. The
was measured, with
static self-testing output in terms of
the results shown in Fig. 9(a). The expected square function
is measured and has a satisfactory agreement with theoretical
analysis. Then, a dynamic self-test was performed by applying
sin( t)
DC 15 V biased AC voltage on one cantilever. A
volt driving voltage was applied on the both sides of the cantilever (via Terminals 1 and 2) for differential actuation. By frequency sweeping, dynamic self-testing results were obtained
and are shown in Fig. 9(b). The resonant frequency was measured as 96.6 kHz, with the resonant peak of 3.17 mV. The measured resonant frequency agrees well with the designed value of
98.8 kHz.
The response of the high- sensor to shock acceleration was
first evaluated by using a dropping-hammer elastic-shocking
setup plus a signal acquisition system, which is detailed in [10].
Shown in Fig. 10 is the sensor response to a 10 000 g elastic
shocking acceleration generated by dropping the hammer from
a height of 35 mm. The response shows a typical half-sine waveshape with the time period of 84 s. Without amplification of the
output signal, a sensitivity of 0.97 V/g/3.3 V was deduced from
the shock-response signal [10]. Then, the accelerometer was
measured and calibrated in the Beijing Institute of Aerospace
Instrumentation by using a Hopkinson bar system. They gave us
the final testing results but did not provide the detailed testing
data. For a 160 000 g measure-range, five output data points
were measured with sensitivity of 0.931 V/g/3.3 V and the
% FS. The shock acceleration sensitivity
nonlinearity of

Fig. 12. Offset temperature drift is measured for two sensors. Within the temperature range of 25 C to 90 C, the measured temperature coefficient of
offset (TCO) values are 40ppm/ C and 80 ppm/ C, respectively.

obtained by the both measurement methods agrees well with

design.
Noise limited resolution of the sensor was evaluated by scanning the noise-spectrum, with an acceleration response signal
included. The sensor under test was attached on an electromagnetic vibrator, in which a standard accelerometer was used
for calibrating the vibrating acceleration. An HP-4395A network-analyzer was used to implement frequency scanning, with
the results plotted in Fig. 11. At about 3.5 kHz, a sine-wave
vibrating acceleration of 15 g is generated by the vibrator and
calibrated by the standard sensor. Over the frequency scanning
range of 200 Hz to 30 kHz, which corresponds to the halfsine shock period between 2.5 ms and 67 s, the scanned noise
spectrum shows that the noise limited resolution is about 1 g
throughout the frequency band. The zero-point temperature coefficient (TCO) of the sensors was measured for a temperature
C to 90 C. The TCO of the sensors is generrange of
ally better than 100 ppm/ C in terms of the full-range output of
about 200 mV. Shown in Fig. 12 are the TCOs for two sensors
that are approximate 40 ppm/ C and 80 ppm/ C, respectively.

LI et al.: SINGLE-WAFER-PROCESSED SELF-TESTABLE HIGH- ACCELEROMETERS WITH BOTH SENSING AND ACTUATING ELEMENTS

V. CONCLUSION
A high-performance piezoresistive shock accelerometer is
proposed and developed with a single-wafer-based in-plane
lateral sensing configuration. An electrostatic actuator is integrated together with the shock-sensing piezoresistors on
vertical trench-sidewalls for on-chip self-testing. The sensor is
fabricated by using a novel trench-sidewall micromachining
technology, with which both piezoresistive sensing elements
and electrostatic actuating elements are integrated onto the
high-aspect-ratio trench sidewalls. By both static and dynamic
measurements, the on-chip self-testing function is verified.
Then the high- performance of the fabricated sensor is
measured, resulting in a sensitivity of near 1 V/g/3.3 V,
dynamic-vibration resolution of about 1 g, TCO of lower
than 100 ppm/ C and resonant frequency of about 97 kHz.
The measured results agree well with design. In addition to
the realized on-chip self-testing function, the present sensor
achieves much improved performance compared to previously
published results in [5] and [10].

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1999

Xinxin Li was born in Liaoning Province, China, in

1965. He received the B.S. degree in semiconductor
physics and devices from Tsinghua University,
Beijing, China, in 1987, and the M.S. and Ph.D.
degrees in microelectronics from Fudan University,
Shanghai, China, in 1995 and 1998, respectively.
He was with the Shenyang Institute of Instrumentation Technology for five years as a Research Engineer. Then, he was with the Hong Kong University
of Science and Technology as a Research Associate,
Nanyang Technological University, Singapore, as a
Research Fellow and, then, joined Tohoku University, Japan, as a nonpermanent
Lecturer (COE Research Fellowship). From 2001 to the present, he has been a
Professor and now serves as the Director of the State Key Lab of Transducer
Technology, Shanghai Institute of Microsystem and Information Technology,
Chinese Academy of Sciences. He is now also serving as an Adjunct Professor
in both Fudan University and Shanghai Jiaotong University, Shanghai, China.
He is an editorial board member for International Journal of Information Acquisition. For a long period of time, his research interest has been in the fields
of micro/nano sensors and transducers, micro/nano electromechanical systems
(MEMS/NEMS), and micro/nano electromechanical integration technologies.
He has invented more than 30 patents. He has published more than 150 papers
in referred journals and academic conferences.
Prof. Li served as a TPC member for the 2008 IEEE International Conference
on Micro Electro Mechanical Systems (IEEE MEMS-08) and the IEEE International Conference on Sensors (IEEE Sensors) from 2002 to 2008. He has been
appointed as a program committee member for Transducers09.

Lei Gu received the B.S. and M.S. degrees in

electrical and electronic engineering from Southeast
University, Nanjing, China, in 2001 and 2004,
respectively. He is currently working towards the
Ph.D. degree in microelectronics at the State Key
Laboratory of Transducer Technology, Shanghai Institute of Microsystem and Information Technology,
Chinese Academy of Sciences, Shanghai, China.
His current research interest is integrated RF
passives components and CMOS-compatible MEMS
processes.

Yuelin Wang (SM93) received the B.S. degree from

Zhejiang University, Zhejiang, China, in 1982, the
M.S. degree from the Harbin Institute of Technology,
Harbin, China, in 1985, and the Ph.D. degree from
Tsinghua University, China, in 1989.
He joined the faculty of Zhejiang University in
1985 and began his work in microelectromechanical
systems in 1986. He is currently a Professor at the
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences,
Shanghai, China. He is an Editor of the Journal
Sensors and Materials and was a committee member of the Transducers01,
03, and 05. His research interests include microelecromechanical systems and
nanoelectromechanical systems.

Heng Yang was born in Shanghai, China, on March

14, 1972. He received the B.Sc. and Ph.D. degrees
in electronic engineering from the Department
of Electronics Engineering, Fudan University,
Shanghai, China, in 1995 and 2001, respectively.
His doctoral work involved the development of a
bulk micromachined gyroscope.
He worked as a Postdoctoral in the Electronic
Instrumentation Laboratory, Delft University of
Technology, The Netherlands, from 2001 to 2003.
He is currently with the State Key Laboratory of
Transducer Technology, Shanghai Institute of Microsystem and Information
Technology, Chinese Academy of Sciences, Shanghai, China, as a Professor.
His research interests include the development of the solid-state sensors and
the related technologies.