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Northwestern Polytechnic University

EE520 - Advanced FPGA Design and Implementations


Lab 3 Sequential logic

Objectives:
This week exercise will get students to be familiar with modules in verilog to design
sequential logic circuits. Students must finish hands-on lab assignments.

Introduction:
This lab is to create designs to investigate latches, flip-flops, and registers.

Equipment:
The equipment/software you require is as follows:
Altera Cyclone II DE2 board
Quartus II FPAG IDE software

The Laboratory Procedure:


1. Design Examples
/*------------------------------------------------------------------------------------------File Name: RS.v
Description: The following design is for RS latch
---------------------------------------------------------------------------------------*/
// A gated RS latch
module RS (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
and (R_g, R, Clk);
and (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule

Note: Although the latch can be correctly realized in one 4-input LUT, this
implementation does not allow its internal signals, such as R_g and S_g, to be observed,
because they are not provided as outputs from the LUT. To preserve these internal signals
in the implemented circuit, it is necessary to include a compiler directive in the code.
Inthe directive /* synthesis keep */ is included to instruct the Quartus II compiler to use
separate logic elements for each of the signals R_g; S_g; Qa; and Qb.
/*------------------------------------------------------------------------------------------File Name: DLatch.v
Author: Alex Yang, Northwestern Polytechnic University, Fremont, CA
Date: 8/25/2013
Description: Based on the D latch circuit, the following module is for it.
---------------------------------------------------------------------------------------*/
module DLatch (Clk, D, Q);
input Clk, D;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
nand (S_g, D, Clk);
not(R, D);
nand (R_g, R, Clk);
nand (Qa, S_g, Qb);
nand (Qb, R_g, Qa);
assign Q = Qa;
endmodule

/*------------------------------------------------------------------------------------------File Name: Counter.v


Author: Alex Yang, Northwestern Polytechnic University, Fremont, CA
Date: 8/25/2013
Description: The following module is to count clock by TFF.
---------------------------------------------------------------------------------------*/
module Counter ( en, clk , clr , cnt );
input en, clk, clr;
output[3:0] cnt;
reg[3:0] q;
wire[3:0]

t;

assign
assign
assign
assign

t[0]=en;
t[1]=en & cnt[0];
t[2]=t[1] & cnt[1];
t[3]=t[2] & cnt[2];

always @ ( posedge clk or negedge clr)


if (~clr) cnt <=#1 0;
else begin
cnt[3] <= !t[3];
cnt[2] <= !t[2];
cnt[1] <= !t[1];
cnt[0] <= !t[0];
end
endmodule

/*------------------------------------------------------------------------------------------File Name: Counter.v


Author: Alex Yang, Northwestern Polytechnic University, Fremont, CA
Date: 8/28/2013
Description: The following module is to count clock by TFF.
---------------------------------------------------------------------------------------*/

module MCodeTop(rst, clk, sw, led);


input rst, clk;
//clk:=>50MHz; rst: => KEY0;
input[2:0] sw;
//sw:=> SW2~SW0
output led;
//led:=> LEDR0;
reg
led;
reg[24:0]
wire

cnt;
clock = cnt[24];//Low Freq clock = 50MHz/(2^25) = 1.5Hz

//Divide Freq by 2^25 (=33,554,432)


always@(posedge clk)begin
if(rst)
cnt<=#1 0;
else
cnt<=#1 cnt+1;
end
//Morse code counter from 0 to 19
reg[4:0]
MCnt;
always@(posedge clock)begin
if(rst)
MCnt<=#1 0;
else if(MCnt==5'b10011) MCnt<=#1 0;
else MCnt<=#1 MCnt+1;
end
always@(sw or MCnt)begin
led=0;
case(sw)
3'b000: begin
//Input "A"
if(MCnt==0 | ((MCnt>1)&&(MCnt<5)) ) led=1;
else
led=0;
end
3'b001: begin
//Input "B"
if(MCnt<2 | (MCnt==4) | (MCnt==6)| (MCnt==8)) led=1;
else
led=0;
end
3'b010: begin
//Input "C"
if(MCnt<2 | (MCnt==4) | ((MCnt>=6)&& (MCnt<=8)) |
(MCnt==10) )
led=1;
else
led=0;
end
3'b011: begin
//Input "D"
if(MCnt<2 | (MCnt==4) | (MCnt==6))
led=1;
else
led=0;
end
3'b100: begin
//Input "E"
if(MCnt==0)
led=1;
else
led=0;
end
3'b101: begin
//Input "F"
if(MCnt==0 | (MCnt==2) | (MCnt>=4)&&(MCnt<=6)|
(MCnt==8))
led=1;
else
led=0;
end
3'b110: begin
//Input "G"
if(MCnt<2 | (MCnt>=4)&&(MCnt<=6) | (MCnt==8))

led=1;
else
led=0;
end
3'b111: begin
//Input "H"
if((MCnt==0) | (MCnt==2) | (MCnt==4) | (MCnt==6))
led=1;
else
led=0;
end
endcase
end
endmodule
Morse code of alphabet A to H are as follows:

Hint: A:

234

dot off dash


B:

012

19

off

4 5

19

dash off dot off dot off dot off


C:

012

678

10

11

19

dash off dot off dash off dot off


D:

012

4 5

19

dash off dot off dot off


E:

19

dot off
F:

456 7 8

19

dot off dot off dash off dot off


G:

012

456

19

dash off dash off dot off


H:

1 2

dot off dot off dot off dot off

19

The Laboratory Assignments:


1. Design Morse code dector from inputs SW3-SW0(e.g. 0000->0, ... 1001->9) and
display by one LEDR.

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