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Objectives:
This week exercise will get students to be familiar with modules in verilog to design
sequential logic circuits. Students must finish hands-on lab assignments.
Introduction:
This lab is to create designs to investigate latches, flip-flops, and registers.
Equipment:
The equipment/software you require is as follows:
Altera Cyclone II DE2 board
Quartus II FPAG IDE software
Note: Although the latch can be correctly realized in one 4-input LUT, this
implementation does not allow its internal signals, such as R_g and S_g, to be observed,
because they are not provided as outputs from the LUT. To preserve these internal signals
in the implemented circuit, it is necessary to include a compiler directive in the code.
Inthe directive /* synthesis keep */ is included to instruct the Quartus II compiler to use
separate logic elements for each of the signals R_g; S_g; Qa; and Qb.
/*------------------------------------------------------------------------------------------File Name: DLatch.v
Author: Alex Yang, Northwestern Polytechnic University, Fremont, CA
Date: 8/25/2013
Description: Based on the D latch circuit, the following module is for it.
---------------------------------------------------------------------------------------*/
module DLatch (Clk, D, Q);
input Clk, D;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
nand (S_g, D, Clk);
not(R, D);
nand (R_g, R, Clk);
nand (Qa, S_g, Qb);
nand (Qb, R_g, Qa);
assign Q = Qa;
endmodule
t;
assign
assign
assign
assign
t[0]=en;
t[1]=en & cnt[0];
t[2]=t[1] & cnt[1];
t[3]=t[2] & cnt[2];
cnt;
clock = cnt[24];//Low Freq clock = 50MHz/(2^25) = 1.5Hz
led=1;
else
led=0;
end
3'b111: begin
//Input "H"
if((MCnt==0) | (MCnt==2) | (MCnt==4) | (MCnt==6))
led=1;
else
led=0;
end
endcase
end
endmodule
Morse code of alphabet A to H are as follows:
Hint: A:
234
012
19
off
4 5
19
012
678
10
11
19
012
4 5
19
19
dot off
F:
456 7 8
19
012
456
19
1 2
19