Documente Academic
Documente Profesional
Documente Cultură
UNIVERSITY
(Estd. u/s 3 of UGC Act 1956)
Compiled By
Prof. Jagannadha Naidu K
Asst. Prof.(Sr.)
SENSE
VIT University.
List of Tasks:
Sl. No
Reference
T1
T1
T1
T1
T1
T1
T1
T1
--List files
Task No:1
Date:
VI Characteristics of PMOS and NMOS
Aim:
To plot the V-I characteristics of NMOS and PMOS transistors. Determine the region of
operation for the MOSFET. Calculate its threshold voltage and pinch-off voltage.
Tool:
Cadence Virtuoso , ADE
Schematic diagram:
NMOS:
Fig1.
PMOS
Fig2.
Procedure:
1.
2.
3.
4.
Model graph:
NMOS Ids Vs Vds
Pinch-off Voltage=
Task No.:1(a)
Short Channel and Body effect of a N-MOSFET
Date:
Aim:
To find the channel length modulation co-efficient () and observe body bias effect
of N-Channel MOSFET.
Tool:
Cadence Virtuoso, ADE
Schematic diagram:
Channel length modulation:
Fig.1
Procedure:
Channel length modulation co-efficient:
1.
2.
3.
4.
Invoke Virtuoso
Draw the schematic of the Fig1.
Invoke ADE for device simulation.
Perform DC analysis, sweep the source drain voltage (Vds) from 0-1.8V and plot
the output current (ID).
5. Note down two values of ID1 and ID2 for two arbitrary values (Vds1 and Vds2) of
Vds in saturation region.
6. Calculate the Channel length modulation co-efficient () using the formula
ID1 1 VDS1
=
ID2 1 VDS 2
7. Plot the output characteristics Ids Vs Vgs, for different body bias voltage.
Model Graph:
Channel Length Modulation
ID2
ID1
VDS1
Calculation:
Calculate channel length modulation co efficient
Different Vth values for different VSB
Result and Inference:
VDS2
Task No:2
Date:
Fig.1
Model Graph:
Voltage Transfer Characteristics:
Fig.2a
Gain Plot: (dvout/dvin)
Fig.2b
Procedure:
1) Invoke the Cadence Virtuoso
2) Draw the schematic of the CMOS inverter.
3) Invoke ADE XL for device simulation.
Model Graph:
Procedure:
1) Perform Transient analysis and plot the output.
2) Plot .pwr signals at required nodes .
Calculation of Propagation Delay and Power Dissipation:
1)
TP = ( TPLH + TPHL) / 2
Where
TPHL: Time delay between 50% transition of the raising input voltage and 50%
transition of falling output voltage.
TPLH: Time delay between 50% transition of the falling input voltage and 50%
transition of raising output voltage.
2) Calculate total power consumption.
Result and Inference:
Task No:3
Date:
Inputs
A
0
0
1
1
B
0
1
0
1
Output
F
1
1
1
0
Circuit Diagram
NOR Gate:
Output F A B
Inputs
A
0
0
1
1
B
0
1
0
1
Outputs
F
1
0
0
0
Circuit Diagram
Procedure:
1.
2.
3.
4.
Model Graph
DC Characteristics:
NAND Gate:
NOR Gate:
Transient Analysis:
Tabulation:
NAND Gate:
NOR Gate:
Task No:3(a)
Date:
Output
C
0
0
0
0
0
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
Circuit Diagram:
Fig.1
Procedure:
1.
2.
3.
4.
5.
Model Graph:
V(A)
V(B)
V(C)
V(Y)
Task No:4
Date:
Designing an inverter chain to drive off-chip loads
AIM:
To minimize the delay through an inverter chain
Tool:
Cadence Virtuoso, ADE.
Circuit Diagram:
Fig.1
Procedure:
1.
2.
3.
4.
5.
Calculation:
If CL is given
How should the inverters be sized?
How many stages are needed to minimize the delay?
Design Challenges
Keep signal rise times < gate propagation delays.
good for performance and power consumption
Keeping rise and fall times of the signals of approximately equal values
Determine the min. propagation delay.
Determine the number of inverters N.
What are the gate widths of each inverter in the chain?
Results and Inference:
Task No:5
Date:
Physical Design of Digital Cells
AIM:
To use Cadence Virtuoso to create a CMOS layout for inverter, NAND and NOR.
a) Do pre-layout simulations using Spectre.
b) Layout a circuit using Cadence Virtuoso.
c) Use the Design Rule Checker to check for errors in the layout.
d) Perform extraction on the layout and use the Layout Vs. Schematic tool to verify that
the layout matches the circuit schematic.
e) Use the extracted netlist of the layout to perform post-layout simulation.
Tool:
Cadence Virtuoso, ADE.
Circuit Diagram
Inverter Schematic
Fig.1
Inverter Layout
Fig.2
Procedure:
1.
2.
3.
4.
5.
6.
7.
8.
Task No:6
Date:
D flip-flop setup and hold timing analysis
Aim:
To implement a CMOS circuit for D-flip flop and perform the timing analysis and
calculate setup time and hold time.
Tool:
Cadence Virtuoso, ADE.
Circuit Diagram:
Model Graph:
Procedure:
1)
2)
3)
4)
5)