CS647 Advanced Computer Architecture

L T P: 3 0 0 Credit: 3
Objective: The course will try to provide an insight on classification of parallel
computers, Advanced processor, pipelining, memory design and architecture and
multi processor architecture
Outcome: At the end of curriculum the student will be well versed with multiprocessor and multi-computers, condition of parallelism, data and resource
dependencies Latency, CISC, RISC, cache memory, hit and miss, symmetric and
distributed shared memory architectures
UNIT I Lectures: 9
Parallel computer models: The state of computing, Classification of parallel
computers, Multiprocessors and multi-computers, Multi-vector and SIMD computers.
Program and network properties: Conditions of parallelism, Data and resource
Dependences, Hardware and software parallelism, Program partitioning and
scheduling, Grain Size and latency, Program flow mechanisms, Control flow versus
data flow, Data flow Architecture, Demand driven mechanisms, Comparisons of flow
mechanisms
UNIT II Lectures: 10
Advanced processors: Advanced processor technology, Instruction-set
Architectures, CISC Scalar Processors, RISC Scalar Processors, Superscalar
Processors, VLIW Architectures, Vector and Symbolic processors Course Structure &
Detailed Syllabus of MURP & M. Tech Program 2015-16 149

Pipelining: Linear pipeline processor, nonlinear pipeline processor, Instruction

pipeline Design, Mechanisms for instruction pipelining, Dynamic instruction
scheduling, Branch Handling techniques, branch prediction, Arithmetic Pipeline
Design, Computer arithmetic principles, Static Arithmetic pipeline, Multifunctional
arithmetic pipelines
UNIT III Lectures: 15
Memory Hierarchy Design: Cache basics and cache performance, reducing miss
rate and miss penalty, multilevel cache hierarchies, main memory organizations,
design of memory hierarchies.
Multiprocessor architectures: Symmetric shared memory architectures,
distributed shared memory architectures, models of memory consistency, cache
coherence protocols (MSI, MESI, MOESI), scalable cache coherence, overview of
directory based approaches, design challenges of directory protocols, memory
based directory protocols, cache based directory protocols, protocol design
tradeoffs, synchronization,
UNIT IV Lectures: 8
Scalable point point interfaces: Alpha364 and HT protocols, high performance
signaling layer.
Enterprise Memory subsystem Architecture: Enterprise RAS Feature set:
Machine check, hot add/remove, domain partitioning, memory mirroring/migration,
patrol scrubbing, fault tolerant system.
Text / Reference Books:
1. Advanced computer architecture by Kai Hwang, TMH
2. Computer organization and design by D. A. Patterson and J. L. Hennessey, Morgan
Kaufmann, 2nd Ed.
3. Computer Architecture and organization by J.P.Hayes, MGH.
4. Memory System and Pipelined processors by Harvey G.Cragon, Narosa
Publication.
5. Parallel computer by V.Rajaranam and C.S.R.Murthy, PHI.
4. Foundation of Parallel Processing by R.K.Ghose, Rajan Moona and Phalguni Gupta
Narosa Publications.
5. Scalable Parallel Computers Architecture by Kai Hwang and Zu, MGH.
6. Computer Organisation and Architecture by Stalling W, PHI.
7. Advanced Computer Architecture-A Design space Approach by D.Sima,
T.Fountain, P.Kasuk, Addison Wesley.
8. Computer Architecture and Parallel Processing by Hwan and Briggs, MGH.