Documente Academic
Documente Profesional
Documente Cultură
Giornata IU.NET
18 Settembre 2014
Outline
Introduction & GaN properties
Applications opportunities
Open issues
Materials
Technology (E-Mode, Breakdown, Vertical
vs lateral, .)
Parasitic & Reliability
GaN Activities within IU.NET
Conclusions
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
[1] U. K. Mishra, P. Parikh, Y.F. Wu, AlGaN/GaN HEMTsAn Overview of Device Operation and
Applications IEEE Proc. Vol. 90, No. 6, p. 1022, June 2002.
[2] U. K. Mishra, L. Shen, T. E. Kazior, Y. F. Wu, GaN-Based RF Power Devices and Amplifiers IEEE
Proceedings, Vol. 96, No. 2, p. 287, February 2008.
http://www.edn.com/Pdf/ViewPdf?contentItemId=4409627
Slide 5
SiN
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
AlN
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ + + + + + + + + + + + + + + +
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ + + + + + +AlN
+ + + + + + + + +
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ + + + + + + + + + + + + + + +
GaN
+
Buffer
Typically 20-25%
Al composition
10
10
generalized
gradientand
reement
between measured
ed values
for approach(GGA)
(ii).
approximation
plasma-induced molecular
beam epitaxy (PIMBE)
-2
e (PSP + PPE)
GGA
lin. interpolation
13
10
12
GGA
nonlinear for alloys
10
N-face, PIMBE
Ga-face, PIMBE
Ga-face, PIMBE+MOCVD
Ga-face, MOCVD
11
10
0.1
0.2
0.3
0.4
Al-concentration x
0.5
0.6
HEMTs/Yale/WSI
G. Meneghesso- Giornata IU.NET - 18 Settembre 2014N00014-99-10714
11
I:GaN
Cornell
12
13
14
[3] Y.-F. Wu, M. Moore, A. Saxler, T. Wisleder and P. Parikh 40-W/mm Double
Field-plated GaN HEMTs, Device Research Conference, . 151, 2006
15
16
17
Outline
Introduction & GaN properties
Applications opportunities
Open issues
Materials
Technology (E-Mode, Breakdown, Vertical
vs lateral, .)
Parassitic
Reliability
GaN Activities within IU.NET
Conclusions
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
18
Efficienza Energetica
Eolica/Solare
Altre
Perdite di
conversioneOggigiorno,
Idroeletrica
Nucleare
Carbone
oltre il 10%
dellenergia elettrica globale
viene completamente persa a
causa dellinefficienza dei sistemi
di conversione.
Chart: EIA U.S. Electric Power Generation
Nat. Gas
E-LAB,
19
POWER APPLICATIONS
20
Why nitride?
N- (Si)
N-
Electric Field
(GaN)
N+
N+
VB V
= E C WD
RON = WD / q mn ND
Emax = (q N D WD ) /e Si
VB
VB
R ON =
3
e Si mn E C
Thickness of Drift Layer, WD
21
@ 1 MHz
22
Morita, T.; Tamura, S.; Anda, Y.; Ishida, M.; Uemoto, Y.; Ueda, T.; Tanaka, T.; Ueda, D.
99.3% Efficiency of three-phase inverter for motor drive using GaN-based Gate Injection
TransistorsApplied Power Electronics Conference and Exposition (APEC),
2011 Twenty-Sixth Annual IEEE 2011 , Page(s): 481 484
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
23
GaN-HF-Leistungselektronik
Fraunhofer IAF
24
Outline
Introduction & GaN properties
Applications opportunities
Open issues
Materials
Technology (E-Mode, Breakdown, Vertical
vs lateral, .)
Parassitic
Reliability
GaN Activities within IU.NET
Conclusions
Fraunhofer IAF
25
AlGaN
GaN
Al2O3, SiC, Si
NL
GaN 2 nm
AlGaN
Channel
C Conc. 1x1013 cm-2
Resistivity 400-700 ohms / sq
Insulating GaN
GaN
(~1 micron )
Nucleation
Substrate
Substrate
26
250nm
Upper Interface
Sharp and
perfectly
delineated
heterointerfa
ces
Lower Interface
27
28
- Cheap (0,5kE 2 4)
- poor thermal conductivity
- Good/poor mismatch
29
GaN on Si (6 8)
The use of SixNy interlayers in
GaN grown on sapphire
substrates is very successful and a
dislocation density reduction by
two or three orders of magnitude
has been reported. However, it is
not straightforward to implement
SixNy interlayers in GaN grown
on Si due to the large thermal
mismatch between GaN and Si.
-Cheap and large diameter
- good/poor thermal conductivity
- bad mismatch
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
30
31
Outline
Introduction & GaN properties
Applications opportunities
Open issues
Materials
Technology (E-Mode, Breakdown, Vertical
vs lateral, .)
Parassitic
Reliability
GaN Activities within IU.NET
Conclusions
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
32
Normally OFF
Recess on the Scho ky Gate (also
with MIS)
S
D
Gate
Barrier (AlGaN)
-----
--------------
Gate
F- F - F-
Barrier (AlGaN)
--------------
Buffer (GaN)
Leakage, trapping,
-----
-----
Buffer (GaN)
Fluorine implanta on
D
Barrier (AlGaN)
-------------
Buffer (GaN)
33
Breakdown measurements
The breakdown voltage of AlGaN/GaN
HEMTs can be evaluated by pulsed IDVD measurements
When BDV is reached Snapback,
due to degradation, hot spots
The junction can degrade even before
BDV
34
35
36
Field-plate Optimization
37
38
39
Vertical vs
Lateral GaN
HEMT
AlGaN
GaN
Substrate 250nm
40
Outline
Introduction & GaN properties
Applications opportunities
Open issues
Materials
Technology (E-Mode, Breakdown, Vertical
vs lateral)
Parassitic & Reliability
GaN Activities within IU.NET
Conclusions
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
41
SOURCE
GATE
DRAIN
AlGaN
Epi traps
affect both
transconductance
AND
pinch-off voltage
GaN
Buffer
Traps affecting VT
42
Slump
RL
VDS
VGSON
Gate
Drain
VGS
OFF
Source
IDEAL
43
43
Current
collapse
99 s
Measured by pulsing from
rest conditions (VG_QB=0,
Current
VD_QB=0)
Collaps
Measured by pulsing from
trapping conditions (VG_QB=-8,
e
VD_QB=50)
ON
OFF
ON
OFF
ON
VGS
(-8
V)
OFF
1 s
IDEAL
Slump
44
44
The Drain Current Transient analysis comprehensively investigate the time evolution
of carrier (de)trapping processes. The deep-levels signatures activation
energies and capture cross-sections and their localization can be achieved by
performing the measurements under different bias conditions and different base-plate
temperatures.
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
45
45
45
D. Bisi et al., Deep-Level Characterization in GaN HEMTsPart I: Advantages and Limitations of Drain Current Transient
Measurements, IEEE Trans. Electr. Dev.60, 3166, 2013.
46
46
46
47
47
48
P. Tenti,
L. Rossetto,
G. Spiazzi,
S. Buso,
P. Mattavelli
L. Corradini
VCC
CF
DRIVER
DUT
Rs
Io(t)
1
2
J1
SMB_maschio
1
Vmis
J3
R2
Q1
IRLR3705Z
20
Vpol
CONN MOD 6-2_J
D3
STPS0520Z
D1
5.1V
C1
10n
DYNAMIC RDSon
10
D2
STPS0520Z
R1
10
10
120 V
[W]
4 dispositivi
160 misurati
V
-1
10
80 V
RDSon = 25 mW
-2
10
3
Time [s]
-5
x 10
49
50
Destructive breakdown
occuring at 650V
GaN HEMTs G. Meneghesso- Giornata IU.NET - 18 Settembre 2014
51
ID (A)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.5
ID (A)
A: pre-stress
B: neutral GaN:UID traps (no
e-) & neg. GaN:C traps (no h+)
VDS =0.5V
A
B
C
D
1
0.5
B
C
A
0
Sim
Exp
-7
VDS =0.5V
VGS=-5.5V
-6
-5
VGS (V)
-4
-3
B to C: e- capture into
GaN:UID traps
C: neg. GaN:UID traps
& neg. GaN:C traps
C to D: h+ capture into
GaN:C traps
52
3rd leakage
mechanism
2nd leakage
mechanism
1st leakage
mechanism
53
GaN-HEMTs - UniBO
Simulation of a GaN-on-Si power HEMT in off-state up to
breakdown Comparison against literature data
F. Monti, D. Cornigli, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani
54
GaN-HEMTs - UniBO
Simulation of vertical leakage/breakdown in GaN-on-Si buffers
up to 150C Comparison against literature data
F. Monti, D. Cornigli, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani
TCAD data
Vertical
buffer in
forward bias
traps in the
GaN/AlGaN
buffer
Piezoelectric
induced holes
Experiments
Trap-assisted conduction
in the transition layer
TCAD data
55
GaN-HEMTs - UniBO
Modeling Self-Heating Effects in AlGaN/GaN HEMT
A. N. Tallarico, P. Magnone, E. Sangiorgi, C. Fiegna
10
-1
(cm K W )
12
Simulation results by Sentaurus TCAD
Experimental results by A. Sarua [1]
Power law by A. Sarua [1]
TBR X10
-4
6
4
2
0
300
350
400
450
500
550
600
650
Temperature (K)
The TBR (thermal boundary resistance), between GaN layer and SiC substrate is
modeled according to [1].
PMI (physical model interface) implemented in Sentaurus TCAD [2].
[1] A. Sarua et al., IEEE Trans. Electron Devices, 2007
[2] A. N. Tallarico, SISPAD, 2014
56
GaN-HEMTs - UniBO
Applications
Modeling Self-Heating
Effects in AlGaN/GaN HEMT
Drain-lag simulations accounting for both self-heating
and traps at AlGaN/Nitride interface
1.0
LSTR_PITCH (um)
5.0
7.5
10.0
12.5
15.0
-2
2.5
24.4
10.4
4.4
13
0.0
0.0
604.4
204.4
64.4
0.8
0.6
0.4
LSTR_PITCH (um)
604.4
24.4
204.4
10.4
64.4
4.4
4.4 isothermal
0.2
0.0
2.39
800
2.38
700
2.37
2.36 E
= 0.5 eV from VB
TRAPS
600
2.35
LSTR_PITCH (um)
- - - - 4.4 isothermal
4.4
2.33
10.4
24.4
2.32
500
2.34
2.31
10
-8
10
-7
10
-6
400
10
-5
Time (s)
10
-4
10
-3
10
300
0.4
0.6
0.2
1.0
TTHERMODE = 300 K
-2
57
B
On-wafer device
Low-noise
programmable
bias source
Low-noise
programmable
bias source
Low-noise
transimpedance
amplifier
Arbitrary
waveform
generator
DC
AC-coupled
amplifier
AC
PC-based
2-channels
A/D
converter
58
59
http://www.hiposwitch.eu/
http://www.e2cogan.eu/
60