DigitalSystemDesign

Introduction

Intro
DigitalDesignmeans

Area
Powerdissipation
Performance
Testability

Mappingalgorithms/applicationsinsilicon
Applyingtransformationsandtricksthatresultsin
optimalmappingincompetingdesignspaceof

VLSIhasenabledsolutionstointractable
engineeringproblems
Rapidadvancementhasledtonewdimensionsin
thetechnology
VLSI
VLSIhasrevolutionizedthecommercialmarket
has revolutionized the commercial market

DigitalSystemsinDSPApplications

DigitalSystemstechnologies&
constraints

Usuallysuchasystemconsistsof
Usually such a system consists of
heterogeneousphysicaldevicessuchas
Microcontrollers
Microprocessors
DSPs
FPGAs

Choicedependsonapplication
Ch i d
d
li i
Constraints?

MooressLaw
Moore
Law

Intel continues to pursue MooressLaw

IntelcontinuestopursueMoore
Law

Intel ticktock
Inteltick
tockmodel
model

https://en.wikipedia.org/wiki/Intel_Tick
https://en wikipedia org/wiki/Intel TickTock
Tock

AlgorithmimplementedinC

HWmappingofthecodeinpreviousslide

DigitalTransceiverforaVoice
CommunicationSystem

Algorithms distribution
Algorithmsdistribution
Codeintensivealgorithms

phonebookmanagement,keyboardinterface

Structuredandcomputationallyintensive
algorithms
l ih
digitalupanddownconversion,
demodulationandsynchronizationloops
d
d l i
d
h i i l
forwarderrorcorrection(FEC)

Codeintensiveandcomputationallyintensive
C d i
i
d
i
ll i
i
algorithms
Video/Speechcompression
Vid /S
h
i

Design examples
Designexamples
Realtimesurveillancesystem

DLMB
MICROBLAZE

FIFO

VdectoFIFO
interface

Video
Decoder

Character
BRAM

FIFOto
memory
interface

Character
Generator

Graphics
BRAM

Cursor
Generator

Graphics
Generator

IXCL

DXCL

Xilinx
Multichannel
memoryinterface

Video Mux
VideoMux

Video
Decoder
Chip

Comp.
Video
Output

Comp.
Video
Input

SRAM
Chip
Chi

Video
Encoder
Chip

Mainblockdiagram

Hardware

Design examples
Designexamples
Realtimesurveillancesystem
Advancedversion
Advanced
version

140 000
140,000
120,000
100,000
80,000
60,000
40,000
20,000
0

88,000

Image
decimation

Taskanalysis

MeanShift
vector

106,000

Machinecycles

126,000

Kernel
weighted
histogram

15,000

850

Bhattacharyya
SSRLS
coefficient predictionfilter

16

H d
Hardware/software
/ ft
partitioningof
MeanShifttracking
algorithm
algorithm

17

im
magecopro
ocesssor
a
archit
tectu
ure(M
Mean
nShifft
trrackeer)

18

Prop
posed
darch
hitecture
hardwarre/sofftwarrecodesiggn

19

P f
Performancecomparison
i
SoftwarebasedMean
Software based Mean
Shifttracker
FrameRate=10fps
p

Co
Codesign
designbasedMean
based Mean
Shifttracker
FrameRate=290fps
p
Acceleration=29x

20