Time To Digital Converter Slides

A Tutorial on Robust
High-Resolution
Time-to-Digital Converters
High-Speed Digital CMOS Circuits

Stephan Henzler
Technische Universitt Mnchen
Sumer Term 2011
Outline
Motivation the way to the time domain
Basics of time-to-digital conversion (TDC)
Delay line based TDCs
Time-to-digital converters for sub-gate delay resolution
Comparison of TDC concepts
Outlook: Digital performance enhancement
Stephan Henzler
Sumer Term 2011
Motivation
Basic task of time-to-digital converter (TDC):
Quantize the time interval between a start and a stop signal
with a resolution of some picoseconds
High resolution time-to-digital converters become popular for
Time of flight measurements

Phase detectors in digital PLLs
Measurement and instrumentation
High speed signal capturing, demodulators, data converters,
Reason for increasing popularity:

In a deep-submicron CMOS process,
time-domain resolution of a digital signal edge transition
is superior to voltage resolution of analog signals
Staszewski et al. JSSC 2005
Stephan Henzler
Sumer Term 2011
Counter Based Time Interval Measurement

Time-to-digital converter:
Building block converting time intervals into digital values
Basic idea: Count cycles of known reference clock
In fact this is not a time-to-digital converter but simply a
digital counter
Nutt. Digital Time Intervalometer. Rev. Sci. Instrum., Vol. 39, pp. 13421345, 1968

Stephan Henzler
Sumer Term 2011
Meas. Uncertainty in Clock Based TDC

Stephan Henzler
Sumer Term 2011
Clock Cycle Interpolation
Reduction of reference clock frequency possible

power reduction
Resolution increased beyond maximum frequency
Nutt. Digital Time Intervalometer. Rev. Sci. Instrum., Vol. 39, pp. 13421345, 1968
Jansson et al. A CMOS Time-to-Digital Converter with Better Than 10ps Single-Shot Precision. JSSC 2006

Stephan Henzler
Sumer Term 2011
Principle of Cycle Interpolation

Stephan Henzler
Sumer Term 2011

Stephan Henzler
Sumer Term 2011
Propagation of start signal in

delay-line is a measure for skew
between start and stop signal
Resolution limited to buffer delay
Resolution sensitive to process
and environmental variations

control loop for buffer delay

augmented resolution and
digital calibration
Robust and small,

Nearly digital shrink factor
Stephan Henzler
Sumer Term 2011
TDC Converter Characteristic

Stephan Henzler
10
Sumer Term 2011
TDC Performance Figures

minimum change of input time interval that can be
resolved by the TDC
dynamic range
maximum time interval to be measured
offset error
digital output word for zero time interval
gain error
deviation of actual slope from ideal converter

characteristics
integral nonlinearity
absolute deviation of midlevel of each step from

straight line beween first and last step
differential nonlinearity
deviation of actual stepwidth from ideal one
single shot precision
standard deviation of measurement values

acquired for several measurements of the same
constant time interval
conversion time (latency)
time required to compute the measurement value

after a start (stop) event is captured
dead time
inert period after a measurement before the TDC

can be used for further acquisitions
multi acquisition
ability to measure multiple time intervals

simultaneously
Stephan Henzler
equal as for ADC
resolution
Sumer Term 2011
Alternative TDC Architectures and

Sub-Gate Delay Resolution
Inverter delay-line
TDC embedded in Delay Locked Loop
Skewed parallel delay-lines
Vernier delay-line
Pulse shrinking technique
Local passive interpolation technique
Stephan Henzler
Sumer Term 2011
Inverter Delay-Line: Double Resolution

CMOS inverter provides shortest delay available in technology

Two delay-lines and symmetrical differential flip-flops required
Careful layout required
Eventually coupling between delay-lines
Stephan Henzler
Sumer Term 2011
TDC based on Delay Locked Loop
Jansson et al., 2006
Controlled delay-line for absolute delay measurement

To avoid as much analog circuitry as possible, digital
calibration would be desirable
higher resolution necessary than requested by application
Stephan Henzler
Sumer Term 2011
Arrival Time Uncertainty along Delay Line
delay line without

analog callibration
delay line with

analog callibration
looped
delay line with
analog callibration

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Absolute arrival time

variation increases along
delay line ( n )
integral nonlinearity (INL)
DLL operation reduces INL
of delay line by 2
High resolution allows for
digital gain compensation
Work mainly on monotonicity and use digital
correction of nonlinearity
Reduce length of delay
line and exploit loop
structure
Sumer Term 2011
Looped Time-to-Digital Converter
Folding of delay line enables TDC with (theoretically) infinite

dynamic range
(in reality: intrinsic pulse shrinking gives upper limit)
Improved linearity
Reduced area and power consumption
Possible for all delay-line based time-to-digital converters
Stephan Henzler
Sumer Term 2011
Loop Control
Stop completely async. to all other TDC signals

One erroneous counter step causes large error in overall result
Two fold stop signal synchronization
Stephan Henzler
Sumer Term 2011
Alternative TDC Architectures and

Sub-Gatedelay Resolution
Inverter delay-line
TDC embedded in Delay Locked Loop
Skewed parallel delay-lines
Vernier delay-line
Pulse shrinking technique
Local passive interpolation technique
Stephan Henzler
Sumer Term 2011
Parallel Scaled Delay-Line

Sub-gatedelay resolution
achieved by differently sized
parallel delay elements
Strongly affected by
variations
Digital correction possible
but weak linearity
Not a robust concept
Stephan Henzler
Sumer Term 2011
Vernier Delay Line-Based TDC

flip-flop as
early-late detector
td2
td
td1
Rahkonen et al., JSSC, 1993.
Dudek et al., TSSC, 2000.
Nonius principle:
Race between start and stop signal in two delay lines
Resolution given by difference of gate delays: TLSB=td1-td2
Local variations of gate delays and flip-flops limit maximum
resolution to approximately 6 sigma(gate delay)
Slow, area intensive, power hungry
De-skewing required
Stephan Henzler
Sumer Term 2011
Hierarchical Time-to-Digital Converter
Significantly smaller Vernier delay-line

Complex wiring in multiplexer introduces asymmetries, i.e.
nonlinearities in the converter characteristics
Ramakrishnan, A Wide-Range, High-Resolution, Compact, CMOS Time-to-Digital Converter, VLSID 2006.

Stephan Henzler
Sumer Term 2011
Pulse Shrinking Time-to-Digital Converter

Operating principle:
start and stop signals create a pulse
which propagates in a line or ring of
delay elements
Pulse width is continuously reduced by
resolution time TLSB
Detect vanishing of pulse
Chen et al., TCAS-II, 2000.
t
t , +t
)
Resolution given by TLSB = (t
i.e. dependent on global p/n ratio (ratioed logic!)
Local variations of gate delays and flip-flops limit maximum resolution to
approximately 6 sigma(gate delay)
Minimum length of un-looped delay line equal to dynamic range
large non-linearity (preprocessing of pulse increases non-linearity)
Slow, area intensive, power hungry, susceptible to variations
rise
d ,inv1
fall
d ,inv1
rise
d ,inv 2
fall
d ,inv 2

Stephan Henzler
Sumer Term 2011
Comparison of TDC Concepts

Type
Basic
Vernier
Pulse shrinking
schematic
1
resolution
t d ,inv
or t d ,buf
td ,buf 1 td ,buf 2
fall
rise
fall
t drise
, inv1 t d , inv1 t d , inv2 + t d ,inv 2
subgate del.
no
yes
yes
chain/loop
yes / yes
yes / yes
yes / yes
Tconversion
Tlatency
Tconversion
Tconversion
stage effort
2 Inv + MSFF
8 Inv
MSFF + 4.4 Inv

10.4 Inv
MSFF + 3 Inv
9 Inv

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2 TINV
TLSB
T
TLSB
(T + Tmin )
Sumer Term 2011
Principle of Local Passive Interpolation

Linear interpolation increases the time resolution by generating
intermediate signals in between two signals with the same
switching direction and a skew smaller than the rise-time

Stephan Henzler
Sumer Term 2011
Local Passive Interpolation TDC

Differential delay-line
Same latency as basic TDC but increased resolution
Linear interpolation by resistors, transistors or diodes
Loop structure:
Increased dynamic range and improved linearity
Resolution limited by local variations
Stephan Henzler
Sumer Term 2011
Sampling of LPI Delay Line

Fully symmetrical sense amplifier
to sample differential LPI delay line
Pre-charge eliminates history
effect from prior conversion
Coupling latches hold pseudo
thermometer code while TDC is
prepared for next conversion
Post processing:
Bubble correction
Thermometer-to-binary conversion

Stephan Henzler
Sumer Term 2011
Sizing of Interpolation Resistors
power [AU]
small R
power [AU]
trade-off
power [AU]
large R
Trade-off between power and linearity

Low resistance:
large cross-current but perfect interpolation
Large resistance:
small cross-currents but systematic linearity error
Stephan Henzler
Sumer Term 2011
Characterization of TDC
Precise time-to-digital converter measurement
Calibrate converter under PVT-variations
Required during production test
Externally generated start and stop signals requires

expensive high precision measurement equipment
No periodic voltage and temperature calibration
On-chip calibration circuitry desirable
Generating the start and stop signal independently not

feasible due to jitter
Derive start and stop signal from same source
Characterization circuitry must relate the relative time interval
measurement to an absolute reference
Stephan Henzler
Sumer Term 2011
On-Chip Characterization Unit

Stephan Henzler
Sumer Term 2011
Absolute Time Interval Reference

Configure both delay lines as ring oscillators and count
number of cycles during reference interval Tcal
Tcal

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Sumer Term 2011
10
Converter Characteristics

Stephan Henzler
Sumer Term 2011
1.2 LSB
Integral Non-Linearity

Stephan Henzler
Sumer Term 2011
0.6 LSB
Differential Non-Linearity

Stephan Henzler
Sumer Term 2011
11
mean
variation
Single-Shot Precision
0.7LSB single shot precision

Variation of output data word if one time interval is
measured repeatedly caused by noise in TDC
Limits resolution for single shot operation
Averaging, i.e. over-sampling increases resolution
Stephan Henzler
Sumer Term 2011
Single Shot Precision

Histogram of data shifts with increasing time interval
mean value
single shot precision
Finite single shot precision, i.e. noise superimposes single

shot measurement
Stephan Henzler
Sumer Term 2011
Recommended Literature

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36
Sumer Term 2011
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A Tutorial on Robust

High-Speed Digital CMOS Circuits

Sumer Term 2011

Sumer Term 2011

Time of flight measurements

Reason for increasing popularity:

Sumer Term 2011

Counter Based Time Interval Measurement

High-Speed Digital CMOS Circuits

Sumer Term 2011

Meas. Uncertainty in Clock Based TDC

High-Speed Digital CMOS Circuits

Sumer Term 2011

Clock Cycle Interpolation

Reduction of reference clock frequency possible

High-Speed Digital CMOS Circuits

Sumer Term 2011

Principle of Cycle Interpolation

High-Speed Digital CMOS Circuits

Sumer Term 2011

Principle of Cycle Interpolation

High-Speed Digital CMOS Circuits

Sumer Term 2011

Principle of Cycle Interpolation

Propagation of start signal in

control loop for buffer delay

Robust and small,

Sumer Term 2011

TDC Converter Characteristic

High-Speed Digital CMOS Circuits

TDC Performance Figures

maximum time interval to be measured

digital output word for zero time interval

deviation of actual slope from ideal converter

absolute deviation of midlevel of each step from

deviation of actual stepwidth from ideal one

single shot precision

standard deviation of measurement values

conversion time (latency)

time required to compute the measurement value

inert period after a measurement before the TDC

ability to measure multiple time intervals

High-Speed Digital CMOS Circuits

equal as for ADC

Sumer Term 2011

Alternative TDC Architectures and

Sumer Term 2011

Inverter Delay-Line: Double Resolution

CMOS inverter provides shortest delay available in technology

Sumer Term 2011

TDC based on Delay Locked Loop

Jansson et al., 2006

Controlled delay-line for absolute delay measurement

Sumer Term 2011

Arrival Time Uncertainty along Delay Line

delay line without

delay line with

High-Speed Digital CMOS Circuits

Absolute arrival time

Looped Time-to-Digital Converter

Folding of delay line enables TDC with (theoretically) infinite

Sumer Term 2011