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High-Resolution
Time-to-Digital Converters
Outline
Motivation the way to the time domain
Basics of time-to-digital conversion (TDC)
Delay line based TDCs
Time-to-digital converters for sub-gate delay resolution
Comparison of TDC concepts
Outlook: Digital performance enhancement
High-Speed Digital CMOS Circuits
Stephan Henzler
Technische Universitt Mnchen
Motivation
Basic task of time-to-digital converter (TDC):
Quantize the time interval between a start and a stop signal
with a resolution of some picoseconds
High resolution time-to-digital converters become popular for
Nutt. Digital Time Intervalometer. Rev. Sci. Instrum., Vol. 39, pp. 13421345, 1968
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Sumer Term 2011
dynamic range
offset error
gain error
integral nonlinearity
differential nonlinearity
dead time
multi acquisition
resolution
looped
delay line with
analog callibration
Loop Control
td2
td
td1
Rahkonen et al., JSSC, 1993.
Dudek et al., TSSC, 2000.
Nonius principle:
Race between start and stop signal in two delay lines
Resolution given by difference of gate delays: TLSB=td1-td2
Local variations of gate delays and flip-flops limit maximum
resolution to approximately 6 sigma(gate delay)
Slow, area intensive, power hungry
De-skewing required
High-Speed Digital CMOS Circuits
Stephan Henzler
Technische Universitt Mnchen
t
t , +t
)
Resolution given by TLSB = (t
i.e. dependent on global p/n ratio (ratioed logic!)
Local variations of gate delays and flip-flops limit maximum resolution to
approximately 6 sigma(gate delay)
Minimum length of un-looped delay line equal to dynamic range
large non-linearity (preprocessing of pulse increases non-linearity)
Slow, area intensive, power hungry, susceptible to variations
rise
d ,inv1
fall
d ,inv1
rise
d ,inv 2
fall
d ,inv 2
Basic
Vernier
Pulse shrinking
schematic
1
resolution
t d ,inv
or t d ,buf
td ,buf 1 td ,buf 2
fall
rise
fall
t drise
, inv1 t d , inv1 t d , inv2 + t d ,inv 2
subgate del.
no
yes
yes
chain/loop
yes / yes
yes / yes
yes / yes
Tconversion
Tlatency
Tconversion
Tconversion
stage effort
2 Inv + MSFF
8 Inv
MSFF + 3 Inv
9 Inv
2 TINV
TLSB
T
TLSB
(T + Tmin )
Differential delay-line
Same latency as basic TDC but increased resolution
Linear interpolation by resistors, transistors or diodes
Loop structure:
Increased dynamic range and improved linearity
Resolution limited by local variations
High-Speed Digital CMOS Circuits
Stephan Henzler
Technische Universitt Mnchen
power [AU]
small R
power [AU]
trade-off
power [AU]
large R
Characterization of TDC
Precise time-to-digital converter measurement
Calibrate converter under PVT-variations
Required during production test
Tcal
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Converter Characteristics
1.2 LSB
Integral Non-Linearity
0.6 LSB
Differential Non-Linearity
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mean
variation
Single-Shot Precision
Recommended Literature
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Sumer Term 2011
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