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ST200 VLIW
Series
ST231 Core and
Instruction Set
Architecture Manual
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces
all information previously supplied. STMicroelectronics products are not authorized for use as critical components in
life support devices or systems without the express written approval of STMicroelectronics.
The ST231 core is based on technology jointly developed by Hewlett-Packard Laboratories and
STMicroelectronics.
Linux is a registered trademark of Linus Torvalds
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Contents
Preface
1
xv
Introduction
1.1
VLIW overview
1.2
ST231 overview
1.3
1.4
Document overview
Execution units
2.1
2.2
Multiply units
2.3
2.3.1
Memory access
2.3.2
Addressing modes
2.3.3
Alignment
2.3.4
Control registers
2.3.5
Cache purging
2.3.6
Dismissible loads
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2.4
10
2.4.1
11
2.4.2
syncins macro
12
Architectural state
13
3.1
13
3.2
Register file
13
3.2.1
13
3.3
Branch unit
Link register
14
3.3.1
Bit fields
14
3.3.2
USER_MODE
15
3.3.3
PSW access
15
3.4
16
3.5
Control registers
16
17
4.1
Execution pipeline
17
4.2
Operation latencies
18
4.3
Interlocks
18
4.4
Additional notes
19
4.4.1
19
21
5.1
Trap mechanism
21
5.2
Exception handling
22
5.3
22
5.4
Interrupts
24
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5.5
24
5.6
24
5.6.1
26
27
5.7.1
27
5.7
Misaligned implementation
29
6.1
Introduction
29
6.2
Overview
29
6.3
TLB sizes
30
6.4
Address space
30
6.4.1
Physical addresses
30
6.4.2
Virtual addresses
30
6.4.3
Caches
30
6.5
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Control registers
34
6.5.1
PSW
34
6.5.2
TLB_INDEX
34
6.5.3
TLB_ENTRY0
35
6.5.4
TLB_ENTRY1
38
6.5.5
TLB_ENTRY2
38
6.5.6
TLB_ENTRY3
39
6.5.7
TLB_REPLACE
39
6.5.8
TLB_CONTROL
41
6.5.9
TLB_ASID
41
6.5.10
Coherency
41
6.5.11
TLB_EXCAUSE
42
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6.6
6.7
TLB description
43
6.6.1
Reset
43
6.6.2
UTLB arbitration
44
6.6.3
Exceptions
44
6.6.4
Instruction accesses
44
6.6.5
Data accesses
46
47
6.7.1
SCU_BASEx
48
6.7.2
SCU_LIMITx
48
6.7.3
48
Memory subsystem
49
7.1
Memory subsystem
50
7.2
50
7.2.1
Instruction buffer
51
7.2.2
Instruction cache
51
7.2.3
53
7.3
53
7.3.1
53
7.3.2
54
7.3.3
Speculative loads
54
7.3.4
55
7.3.5
55
7.3.6
Prefetching data
55
7.3.7
56
7.3.8
D-side synchronization
57
7.3.9
57
7.3.10
Operations
58
7.3.11
Cache policy
58
7.3.12
Write buffer
63
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7.4
63
7.5
Additional notes
63
7.5.1
63
7.5.2
64
7.5.3
Reset state
64
7.5.4
64
7.5.5
Prefetch performance
64
67
8.1
Overview
67
8.2
Functional description
68
8.2.1
Data width
68
Communication channel
69
8.3.1
69
8.3
8.4
8.5
Timeouts
Registers
69
8.4.1
69
8.4.2
71
8.4.3
Protection
71
72
8.5.1
Interrupts
72
8.5.2
SDI exceptions
73
8.5.3
73
Control registers
77
9.1
Access operations
77
9.2
Exceptions
77
9.3
78
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9.4
83
9.5
Version register
84
10 Timers
85
10.1
Operation
85
10.1.1
TIMEDIVIDE
86
10.1.2
TIMECOUNTi
86
10.1.3
TIMECONSTi
86
10.1.4
TIMECONTROLi
87
10.2
Timer interrupts
87
10.3
87
11 Peripheral addresses
89
11.1
89
11.2
Peripheral addresses
90
11.2.1
90
11.2.2
DSU registers
92
11.2.3
DSU ROM
94
12 Interrupt controller
95
12.1
Architecture
95
12.2
Operation
96
12.2.1
96
12.3
Test register
Interrupt registers
96
12.3.1
96
12.3.2
97
12.3.3
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12.4
12.3.4
12.3.5
Programming
100
103
12.4.1
Enabling/disabling interrupts
103
12.4.2
Test register
103
12.4.3
Interrupt priority
103
13 Debugging support
105
13.1
Overview
105
13.2
Core
106
13.3
13.4
13.5
13.2.1
Debug interrupts
106
13.2.2
107
109
13.3.1
Architecture
109
13.3.2
110
13.3.3
111
Debug ROM
113
13.4.1
113
13.4.2
113
117
13.5.1
Message format
117
13.5.2
Operation
119
14 Performance monitoring
121
14.1
Events
121
14.2
Access to registers
124
14.3
124
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14.4
125
14.5
126
14.6
Recording events
126
15 Interfaces
15.1
15.2
Mode pins
Peripheral address
127
15.1.2
Boot address
127
15.1.3
Debug enable
127
15.1.4
Port list
128
System
129
Port List
Debugging interface
Port list
Security interface
15.8.1
15.9
Port list
15.7.1
15.8
129
SDI Interfaces
15.6.1
15.7
129
129
15.5.1
15.6
Port list
Port list
15.4.1
15.5
128
Interrupt controller
15.3.1
15.4
127
15.1.1
15.2.1
15.3
127
Port list
Port list
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132
133
133
134
134
135
135
136
136
137
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16 Execution model
139
16.1
Introduction
139
16.2
140
16.3
Functions
142
16.3.1
Bundle decode
142
16.3.2
Operation execution
142
16.3.3
Exceptional cases
143
17 Specification notation
145
17.1
Overview
145
17.2
146
17.3
17.4
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17.2.1
Integer
146
17.2.2
Boolean
147
17.2.3
Bit-fields
147
17.2.4
Arrays
147
Expressions
148
17.3.1
148
17.3.2
149
17.3.3
150
17.3.4
Relational operators
151
17.3.5
Boolean operators
152
17.3.6
Single-value functions
152
Statements
154
17.4.1
Undefined behavior
154
17.4.2
Assignment
155
17.4.3
Conditional
156
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17.4.4
Repetition
157
17.4.5
Exceptions
157
17.4.6
Procedures
158
17.5
Architectural state
158
17.6
159
17.6.1
Support functions
159
17.6.2
Memory model
161
17.6.3
167
17.6.4
Cache model
169
18 Instruction set
18.1
Introduction
171
18.2
Bundle encoding
171
18.2.1
Extended immediates
172
18.2.2
Encoding restrictions
173
18.3
Operation specifications
173
18.4
Example operations
175
18.4.1
171
add Immediate
175
18.5
Macros
177
18.6
Operations
178
Instruction encoding
357
A.1
Reserved bits
357
A.2
Fields
357
A.3
Formats
358
A.4
Opcodes
359
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Glossary
365
Index
367
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Preface
This document is part of the ST200 documentation suite detailed below. Comments
on this or other manuals in the ZZZ documentation suite should be made by
contacting your local STMicroelectronics sales office or distributor.
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Introduction
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ST231 overview
ST230 core
Mul
ITLB
Mul
DTLB
UTLB
4 x SDI
Control
registers
SCU
Instruction
buffer
ICache
Register
file (64
registers
8 read
4write)
Load
store
unit
(LSU)
Write
buffer
DCache
STBus
CMC
64-bit
Prefetch
cache
PC and
branch
unit
I-side
memory
subsystem
Branch
register
file
IU
IU
IU
IU
D-side
memory
subsystem
Trap
controller
Peripherals
Timers
Interrupt
controller
61 interrupts
Debug
support unit
STBus
32-bit
Debuglink
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ST231 changes summary
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Document overview
The DSU status register (DSR1) has the additional endian bit (see Table 49:
DSR1 bit fields on page 111).
The VERSION (see Table 26: VERSION bit fields on page 84) and
DSU_VERSION (see Table 48: DSR0 bit fields on page 111) registers have been
changed.
A number of new 32x32 multiply instructions, mul32, mul64h, mul64hu &
mulfrac have been added (see Chapter 18: Instruction set on page 171).
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Document overview
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Document overview
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Execution
units
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Cacheable memory transactions that miss are written to the write buffer not the
data cache.
Uncached accesses are performed directly on the memory system (refer to
Chapter 7: Section 7.3.5: Uncached load and stores on page 55).
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Load/store unit (LSU)
2.3.3 Alignment
1 All load and store instructions work on data stored on the natural alignment of
the data type; that is, words on word boundaries, half-word on half word
boundaries.
2 load and store operations with misaligned addresses raise an exception which
makes possible the implementation of misaligned loads by trap handlers.
3 For a byte or half-word load, the data from memory is loaded into the least
significant part of a register and is either sign-extended or zero extended
according to the instruction definition.
4 For a byte or half-word store, the data stored from the least significant part of a
register.
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Branch unit
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Branch unit
11
all prefetches issued to the bus have completed (responses have come
back),
all writes issued to the bus have completed (responses have come back).
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Branch unit
the SDI output ports will not send out data as they must be empty before the
core enters idle mode,
the peripheral block will accept and respond to STBus transactions as normal,
the DSU continues to operate as normal (both via the taplink and via the
STBus).
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Architectural
state
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Bit(s)
Writeable
Reset
Comment
USER_MODE
RW
0x0
INT_ENABLE
RW
0x0
TLB_ENABLE
RW
0x0
TLB_DYNAMIC
RW
0x0
SPECLOAD_MALIGNTRA
P_EN
RW
0x0
Reserved
RO
0x0
Reserved
Reserved
RO
0x0
Reserved
Reserved
RO
0x0
Reserved
DBREAK_ENABLE
RW
0x0
IBREAK_ENABLE
RW
0x0
Reserved
10
RO
0x0
Reserved
Reserved
11
RO
0x0
Reserved
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Program status word (PSW)
15
Name
Bit(s)
Writeable
Reset
Comment
DEBUG_MODE
12
RW
0x0
Reserved
[31:13]
RO
0x0
Reserved
3.3.2 USER_MODE
The USER_MODE bit indicates whether the machine is in user mode or
supervisor mode. When in user mode, the processor has restricted access:
The TLB (see Chapter 6: Memory translation and protection on page 29) define
the level of access to memory in both user and supervisor modes.
In user mode there is limited access to control registers (see Chapter 9: Control
registers on page 77).
Certain instructions can not be executed in user mode (see Chapter 18:
Instruction set on page 171).
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Execution
pipeline and
latencies
This chapter describes the architecturally visible pipeline and operation latencies.
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Operation latencies
Operational latencies may vary between different members of the ST200 processor
family.
4.3 Interlocks
The ST231 provides operation latency interlock checking which enforces the latency
between certain operations. The following latencies are checked on the ST231:
load to use,
compare to branch,
multiply to use,
link register write to call or return.
For these particular operation latencies the processor will automatically stall the
pipeline to uphold the internal latency constraints. As such there are no possible
latency violations for the above cases.
However, for optimal machine usage, bundles containing useful operations should
be inserted in order to respect the underlying latency between operations.
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Additional notes
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Additional notes
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Traps:
exceptions
and interrupts
In the ST231 architecture, exceptions and interrupts are jointly termed traps. This
chapter describes the trap mechanism.
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Exception handling
At the trap point, the ST231 transfers execution to the trap handler, starting at the
address held in the HANDLER_PC control register, and saves the execution state
as detailed in Section 5.3: Saved execution state. All operations issued before the
trapping bundle are allowed to complete. All operations issued after and including
the trapping bundle are discarded. The architectural state, with the exception of
saved execution state, is exactly that at the trap point. Hence ST231 interrupts and
exceptions can be considered precise.
Traps are handled strictly (in order), and indivisibly with respect to the bundle
stream.
EXCAUSE HighestPriority();
// Store information
EXADDRESS ExceptAddress(EXCAUSE);// for the handler
SAVED_PSW PSW;
SAVED_PC BUNDLE_PC;
PSW[USER_MODE] 0;
//
PSW[INT_ENABLE] 0;
//
PSW[IBREAK_ENABLE] 0; //
PSW[DBREAK_ENABLE] 0; //
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Saved execution state
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Where the function HighestPriority returns the highest priority exception from
those that have been thrown (please refer to Section 5.6). The ExceptAddress
function defines the value that is stored into the EXADDRESS control register. Its
return value will either be 0 or the address of data or instruction which has
triggered the exception.
Therefore,
variable ExceptAddress(exception);
is equivalent to:
IF ((exception = DBREAK) OR
(exception = MISALIGNED_TRAP) OR
(exception = CREG_NO_MAPPING) OR
(exception = CREG_ACCESS_VIOLATION) OR
(exception = DTLB) OR
(exception = ITLB)) THEN
variable value;
ELSE
variable 0;
Where value is the optional argument that will have been passed to the THROW
(see Section 17.4.5: Exceptions on page 157) when the exception was generated.
The rfi (return from interrupt) operation is used to recommence execution at the
trap point. An rfi operation will cause the following state updates:
PC SAVED_PC;
//
//
//
//
PSW SAVED_PSW;
SAVED_PC SAVED_SAVED_PC;
SAVED_PSW
SAVED_SAVED_PSW;
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Interrupts
5.4 Interrupts
All interrupts are effectively treated by the ST231 as an exception of type
EXTERN_INT. Individual interrupt lines are indicated by registers in the interrupt
controller, Chapter 12: Interrupt controller on page 95.
Bit(s)
Writeable
Reset
Comment
EXCAUSENO
[4:0]
RW
0x0
Reserved
[31:5]
RO
0x0
Reserved.
Value
Comment
STBUS_IC_ERROR
STBUS_DC_ERROR
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Exception types and priorities
25
Name
Value
Comment
EXTERN_INT
IBREAK
ITLB
SBREAK
ILL_INST
SYSCALL
System call.
DBREAK
MISALIGNED_TRAP
CREG_NO_MAPPING
10
CREG_ACCESS_VIOLATIO
N
11
DTLB
12
Reserved
13
Reserved
SDI_TIMEOUT
14
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Speculative load considerations
27
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Memory
translation and
protection
6.1 Introduction
The ST230 provides full memory translation and protection by means of a
translations lookaside buffer (TLB).
It allows the running of memory managing operating systems (OS) (for example,
Linux) together with some level of backward compatibility support for the IPU and
DPU functions under a non memory managed OS (for example, OS21).
6.2 Overview
The ST230 has a small instruction TLB (ITLB), a small data TLB (DTLB) and a
larger unified TLB (UTLB).
The ITLB performs instruction address translations and acts as a cache for address
translations stored in the UTLB. When the ITLB misses it automatically updates
from the UTLB.
The DTLB performs data address translations and acts as a cache for address
translations stored in the UTLB. When the DTLB misses it automatically updates
from the UTLB.
When the UTLB is changed, the ITLB and DTLB are not updated. The ITLB and
DTLB can be flushed under software control by means of the TLB_CONTROL
register. See Section 6.5.8: TLB_CONTROL on page 41.
The ITLB and DTLB act as small caches that keep copies of the currently active
translations. Only translations that are shared or match the current application
(ASID) specific identifier are loaded into the ITLB and DTLB.
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TLB sizes
UTLB
ITLB
DTLB
Value
DTLB size
8 entries
ITLB size
4 entries
UTLB size
64 entries
The UTLB size can be determined either by reading the core version register (using
a lookup table) or reading the TLB_REPLACE register after reset.
6.4.3 Caches
The level 1 caches are virtually indexed and physically tagged. The cache tag RAM
lookup occurs in parallel with the TLB lookup.
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Address space
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Address space
The instruction cache is 32Kb direct mapped and built from 512 x 64 byte lines.
The virtual address bits [14:06] are used to index the instruction cache RAMs.
Virtual address bits [31:13] are sent to the ITLB for translation. The translated
physical address bits [31:13] from the ITLB is then compared against the
instruction cache tag.
Virtual address bits [05:00] are used to select the correct bytes from the cache line.
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Control registers
The data cache is 32Kb four way set associate and built from 4 x 256 x 32 byte lines.
The virtual address bits [12:05] are used to index the data cache RAMs.
Virtual address bits [31:13] are sent to the DTLB for translation. The translated
physical address bits [31:13] from the DTLB are then compared against the data
cache tag.
Virtual address bits [04:00] are used to select the correct bytes from the cache line.
6.5.1 PSW
The TLB can be enabled and disabled by a bit in the PSW (see Chapter 3:
Architectural state on page 13).
When address translation is disabled (TLB_ENABLE = 0) the virtual address will
be used as the physical address. In this case, the default attributes for data accesses
will be uncached and no TLB exceptions will be thrown.
6.5.2 TLB_INDEX
Name
Bit(s)
Writeable
Reset
Comment
ENTRY
[7:0]
RW
0x0
Reserved
[31:8]
RO
0x0
Reserved.
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Control registers
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6.5.3 TLB_ENTRY0
This register maps bits [31:00] of the TLB entry. The entry is chosen by writing to
the TLB_INDEX register.
Name
Bit(s)
Writeable
Reset
Comment
ASID
[7:0]
RW
0x0
SHARED
RW
0x0
PROT_SUPER
[11:9]
RW
0x0
PROT_USER
[14:12]
RW
0x0
DIRTY
15
RW
0x0
POLICY
[19:16]
RW
0x0
SIZE
[22:20]
RW
0x0
PARTITION
[24:23]
RW
0x0
RESERVED
[31:25]
RO
0x0
Reserved.
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Control registers
Value
Comment
UNCACHED
CACHED
WCUNCACHED
Reserved
Reserved
Reserved
Reserved
Reserved
Value
Comment
DISABLED
Page is disabled.
8K
8Kb page.
4MB
4MB page.
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Control registers
37
Name
Value
Comment
256MB
256MB page.
Reserved
Reserved
Reserved
Reserved
Value
Comment
REPLACE
WAY1
WAY2
WAY3
Table 9 lists of the possible values of the PROT_USER and PROT_SUPER fields:
Name
Value
Comment
EXECUTE
Execute permission
READ
WRITE
Write permission
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Control registers
6.5.4 TLB_ENTRY1
This register allows access to bits [63:32] of the TLB entry. The entry is chosen by
writing to the TLB_INDEX register
Name
Bit(s)
Writeable
Reset
Comment
VADDR
[18:0]
RW
0x0
Reserved
[31:19]
RO
0x0
Reserved.
6.5.5 TLB_ENTRY2
This register allows access to bits [95:64] of the TLB entry. The entry is chosen by
writing to the TLB_INDEX register.
Name
Bit(s)
Writeable
Reset
Comment
PADDR
[18:0]
RW
0x0
Reserved
[31:19]
RO
0x0
Reserved.
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6.5.6 TLB_ENTRY3
This register maps bits [127:96] of the TLB entry. The entry is chosen by writing to
the TLB_INDEX register.
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RO
0x0
Reserved.
6.5.7 TLB_REPLACE
Name
Bit(s)
Writeable
Reset
Comment
LFSR
[15:0]
RW
0xffff
LIMIT
[23:16]
RW
0x40
Reserved
[31:24]
RO
0x00
Reserved.
15 14 13 12 11 10
LFSR
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Control registers
The replacement register is used by the software to randomly decide which TLB
entry to replace. The value of the REPLACE field is generated in a pseudo-random
manner using a 16-bit linear feedback shift register (LFSR) generating a maximum
length sequence (taps on bits 3, 12, 14 and 15).
A read from the TLB_REPLACE register returns the current LFSR and LIMIT
values, the LFSR is then clocked to generate a new value. The current value of the
LFSR field can be changed by writing to the TLB_REPLACE register.
The LIMIT field is reset to the number of entries in the TLB1. The LIMIT field can
be changed by writing the TLB_REPLACE register. It is expected that the software
will reduce the value of the LIMIT field in order to reserve a number of TLB entries
for a fixed mapping.
The LIMIT field is not used by the hardware but is included to allow the software to
quickly determine the next TLB entry to replace. A suggested replacement
algorithm is as follows:
unsigned replace, lfsr, limit, index;
// Read replace register to get LIMIT and LFSR
replace = VOLUINT(LXTLB_REPLACE);
// Extract fields
lfsr = LXTLB_REPLACE_LFSR(replace);
limit = LXTLB_REPLACE_LIMIT(replace);
// Decide which entry to replace
index = (lfsr * limit) >> 16;
// Select the correct entry
VOLUINT(LXTLB_INDEX) = index;
Note:
The mullhu instruction can be used to extract the LFSR and LIMIT fields from the
TLB_REPLACE register and perform the multiply. The result is then shifted right by
16 bits to obtain the entry number to replace.
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6.5.8 TLB_CONTROL
Name
Bit(s)
Writeable
Reset
Comment
ITLB_FLUSH
RW
0x0
DTLB_FLUSH
RW
0x0
Reserved
[31:2]
RO
0x0
Reserved.
Before the ITLB or DTLB are flushed, the hardware will ensure that all
outstanding writes to the UTLB have completed.
6.5.9 TLB_ASID
Name
Bit(s)
Writeable
Reset
Comment
ASID
[7:0]
RW
0x0
Reserved
[31:8]
RO
0x0
Reserved.
6.5.10 Coherency
When flushing the ITLB, DTLB, changing the current ASID or updating the UTLB
the software must allow enough time for the change to take effect:
To ensure coherency a following such an update a sync (to ensure the store has
completed) followed by a syncins (to allow the change to take effect) must be used.
In addition to the above the software must be aware that updating the UTLB will
not update the ITLB or DTLB. If a mapping is changed in the UTLB that is also
present in the ITLB or DTLB then the ITLB or DTLB must be flushed. In this case
the sync and syncins should be performed after the flush.
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Control registers
6.5.11 TLB_EXCAUSE
When the TLB raises an exception this register is updated with its cause.
The possible exceptions are:
Name
Value
Comment
NO_MAPPING
PROT_VIOLATION
WRITE_TO_CLEAN
MULTI_MAPPING
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TLB description
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When a TLB exception is taken, the software can determine if the given page is in
the UTLB by checking the IN_UTLB bit.
Name
Bit(s)
Writeable
Reset
Comment
INDEX
[7:0]
RW
0x0
Reserved
[15:8]
RO
0x0
Reserved
CAUSE
[17:16]
RW
0x0
SPEC
18
RW
0x0
WRITE
19
RW
0x0
IN_UTLB
20
RW
0x0
RESERVED
[32:21]
RO
0x0
Reserved.
6.6.1 Reset
After reset the contents of the UTLB are undefined. Before the TLB is enabled all
entries must be programmed (or cleared) to prevent undefined behavior.
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TLB description
6.6.3 Exceptions
When the TLB throws an exception it jumps to the exception vector and updates the
TLB_EXCAUSE, EXADDRESS and EXCAUSENO registers.
When a DTLB exception is raised, the EXADDRESS register contains the virtual
effective address that caused the exception.
When an ITLB exception is raised, the EXADDRESS register will contain the
virtual address of the syllable that caused an exception. In the case of possible
multiple ITLB exceptions, the exception with the lowest syllable address is thrown.
The SAVED_PC and SAVED_PSW stack are also updated in the same way as other
traps.
As noted above, the TLB_EXCAUSE register indicates the nature of the ITLB or
DTLB exception.
Note:
Misaligned loads and control register violations are not considered TLB exceptions.
Details of the EXCAUSENO register can be found in Section 5.6: Exception types
and priorities on page 24.
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TLB description
45
No
PSW[TLB_ENABLE]?
Yes
ITLB hit?
Yes
No
Yes
No
No
PA = Translated VA
Protection
violation?
Multiple hits?
Yes
UTLB hit?
Yes
No
TLB_EXCAUSE NO_MAPPING
THROW ITLB_EXCEPTION
TLB_EXCAUSE MULTI_MAPPING
THROW ITLB_EXCEPTION
TLB_EXCAUSE PROT_VIOLATION
THROW ITLB_EXCEPTION
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TLB description
PSW[TLB_ENABLE]?
Yes
DTLB hit?
Yes
Physical Address (PA) =
Virtual Address (VA)
No
Yes
No
Protection
violation?
No
UTLB hit?
Multiple hits?
Yes
Yes
No
TLB_EXCAUSE NO_MAPPING
THROW DTLB_EXCEPTION
TLB_EXCAUSE MULTI_MAPPING
THROW DTLB_EXCEPTION
TLB_EXCAUSE PROT_VIOLATION
THROW DTLB_EXCEPTION
Access type
Write
Read
Page clean?
No
No
Yes
TLB_EXCAUSE WRITE_TO_CLEAN
THROW DTLB_EXCEPTION
Cached
Yes
Read
PA = Translated VA
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Speculative control unit (SCU)
47
Speculative
abort
CMC
Speculative
abort
SCU
Speculative
control unit
The SCU filters physical speculative load addresses (both cached and uncached)
and prefetches that miss the cache to ensure that speculative bus requests are not
sent out to peripherals and unmapped memory regions.
The SCU supports four regions of memory aligned to the smallest TLB page size
(8 Kbyte). If the physical address of the speculative load/prefetch address falls
within one of the four supported regions it will be allowed, otherwise the SCU
aborts the speculative load/prefetch and zero is returned or the prefetch is
cancelled.
The regions are configured using the SCU_BASEx and SCU_LIMITx control
registers. A region may be disabled by setting the base to be larger than the limit.
The SCU resets so each of the four regions cover the whole of memory. This allows
speculative loads to be issued before the SCU has been initialized.
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6.7.1 SCU_BASEx
Name
Bit(s)
Writeable
Reset
Comment
BASE
[18:0]
RW
0x0
RESERVED
[31:19]
RO
0x0
Reserved.
The SCU base register defines the physical start address of the region where
speculative loads/prefetches are permitted. This region is aligned to the smallest
page size (by virtue of the read only zero bits). The base address is inclusive, so
setting BASE==LIMIT defines an 8 Kbyte region.
6.7.2 SCU_LIMITx
Name
Bit(s)
Writeable
Reset
Comment
LIMIT
[18:0]
RW
0x0x7
ffff
RESERVED
[31:19]
RO
0x0
Reserved.
The SCU base register defines the physical end address of the region where
speculative loads are permitted. This region is aligned to the smallest page size (by
virtue of the read only zero bits). The limit address is inclusive, so setting
BASE==LIMIT defines an 8 Kbyte region.
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Memory
subsystem
This chapter describes the operation of the ST231 processor memory subsystem.
The memory subsystem includes the caches, protection units, write buffer, prefetch
cache, translation lookaside buffer (TLB) and the core memory controller (CMC).
The memory subsystem is split broadly into two parts, the instruction side (I-side)
and the data side (D-side). The CMC interfaces these two halves to the STBus port.
The I-side, containing the instruction cache, supports the fetching of instructions.
The D-side, containing the data cache, prefetch cache and write buffer, support the
storing and loading of data.
The TLB performs memory address translation and protection. The function of the
TLB is detailed in Chapter 6: Memory translation and protection on page 29.
The ST231 ensures that data access are coherent with other data accesses. There is
no guarantee of coherency between instruction and data accesses (see Section 7.5.2:
Coherency between I-side and D-side on page 64) or between the core and external
memory. To ensure coherency data must be purged from the core as described later
in this chapter.
The function of the streaming data interface (SDI) is described in Chapter 8:
Streaming data interface (SDI) on page 67.
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Memory subsystem
Load
Store
Unit
(LSU)
Read/Write/
Flush/Sync/Prefetch
Request
Read
Word
Data Cache
Busy
Fetched
Data
Instruction
Cache
Read
4x32 bit
Instruction
Buffer
PC
PC and
Branch Unit
Uncached
Read/Writes
& Cache Fill
Writes &
(Reads/Prefetch/Sync/Flush)
Write Buffer
Prefetches &
(Reads/Writes/Flush)
Write
Data
CMC
STBUS
Busy
D-Side
Memory
Subsystem
Prefetch
Request
Prefetch Cache
Prefetch
Data
Read
Request
Read Response
Cache Line
I-Side Memory
Subsystem
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I-side memory subsystem
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D-side memory subsystem
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D-side memory subsystem
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The prgset operation also resets the replacement pointer in the set to way 0. This
will not be visible unless using data cache partitioning.
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In the case of writes the data will have already been discarded and therefore the
write is lost. The write may or may not have completed.
In the case of reads the cache will not be updated.
7.3.10 Operations
Table 20 lists the operations supported by the data side memory subsystem:
Word
aligned
Type
Byte aligned
Load
Load word
Load half
unsigned
Load half
signed
Load byte
unsigned
Load byte
signed
Load
dismissible
Load word
Load half
unsigned
Load half
signed
Load byte
unsigned
Load byte
signed
Store
Store word
Store half
Store byte
Prefetch
Prefetch
Purge
Purge address
Purge set
Sync
Sync
Table 20: Memory operations
It is a requirement that half word load/stores are half word aligned (2 bytes) and
word load/stores are word aligned (4 bytes). Misaligned accesses will cause a
MISALIGNED_TRAP exception.
When a cache line is purged to the write buffer it is also invalidated in the cache.
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D-side memory subsystem
Instruction
Loads:
Policy
Uncached
Cache
Miss
59
Write
buffer
Prefetch
Miss
Miss
Load uncached
Hit
SCU
Hit
Dismissable
loads
Uncached
Result
Hit
clean
Hit dirty
Miss
Miss
Miss
Hit
ldb.d, ldh.d,
ldw.d
Hit
Hit
clean
Hit dirty
Hit
Load uncached
Miss
Return 0
Hit
Miss
Hit
Miss
Hit
Miss
Hit
Miss
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Instruction
Stores:
Policy
Uncached
Cache
Miss
Write
buffer
Prefetch
Miss
Miss
Store uncached
Hit
SCU
Hit
Loads:
uncached
ldb, ldh,
ldw,
write
combine
Result
Hit
clean
Hit dirty
Same as uncached.
ldb.d, ldh.d,
ldw.d
Stores:
Uncached
write
combining
Miss
Miss
Miss
Hit
Hit
clean
Hit dirty
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D-side memory subsystem
Instruction
Loads:
Policy
Cached
Cache
Miss
61
Write
buffer
Prefetch
Miss
Miss
Hit
ldb, ldh,
ldw,
SCU
Hit
Dimissable
Loads:
Cached
Hit
clean
Hit dirty
Miss
Miss
ldb.d, ldh.d,
ldw.d
Miss
Hit
Miss
Return 0
Transfer data from prefetch
cache to data cache, Load data
from data cache.
Hit
Hit
Stores:
Cached
Result
Hit
Miss
Hit
clean
Hit dirty
Miss
Miss
Miss
Hit
Hit
clean
Hit dirty
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Instruction
prgadd
Policy
All
Cache
Miss
Write
buffer
Prefetch
Miss
Miss
No effect
Hit
SCU
No effect
Hit
prgset
All
Hit
clean
Hit dirty
Miss
Hit
sync
pft
Result
Cached
Miss
Miss
Miss
Hit
Miss
Hit
Hit
Prefetch discarded
Prefetch discarded
Prefetch discarded
Hit
Uncached
Prefetch discarded
Uncached
write
combining
Prefetch discarded
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Core memory controller (CMC)
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Additional notes
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Additional notes
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The first two points indicate a window for which prefetches might be considered.
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Additional notes
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Streaming
data interface
(SDI)
8.1 Overview
The ST231 SDI is designed to allow fast and easy connection of on-chip peripherals.
Each SDI is unidirectional and includes handshakes to prevent data loss and
improve data flow.
The ST231 implements four SDI interfaces, two input ports and two output ports.
ST230
ST220
Core
Data In
SDI
Input
Data In
SDI
Input
Data Out
SDI Output
Data Out
SDI Output
Control
Registers
Execution
Cluster
unit
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Functional description
The SDIs:
provide a mechanism for attaching streaming hardware to the processor core,
reduce STBus traffic and associated processor stall cycles,
reduce cache pollution and control complexity,
prevent deadlock through a timeout mechanism,
allow communication between clock domains without complex synchronization
hardware.
The SDI ports are accessed via control registers in the core.
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Communication channel
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8.3.1 Timeouts
The timeouts operate as monitors to each individual SDI access. If an access
remains stalled for too long, as defined by the control registers, an exception will
occur.
8.4 Registers
The SDI interfaces directly to the ST231 load store unit. The interface is through a
number of memory mapped registers in the control register address space.
The addresses of these registers are detailed in Chapter 9: Control registers on
page 77.
SDIi_READY
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Registers
Bit(s)
Writeable
Reset
Comment
PRIV
[1:0]
RW
0x0
Privilege bits.
RESETINPUT
RO
0x0
RESETOUTPUT
RW
0x0
RESETOUTPUT, acts as
RESETREQUEST when master,
RESETACK when slave.
INPUTNOTOUTPUT
RO
0x0
Reserved
RO
0x0
Reserved
MASTERNOTSLAVE
RO
0x0
TIMEOUTENABLE
RW
0x0
Reserved
[31:8]
RO
0x0
Reserved
SDIi_COUNT
SDIi_TIMEOUT The number of cycles an SDI data access will be allowed to stall
before a timeout exception will be raised. The value may be read
or written. This register will normally be set to the value of
SDIi_COUNT. Exceptions to this are when it has been
specifically set to another value, or when an SDI access has taken
a timeout exception or been interrupted. In the case of an SDI
timeout the SDIi_TIMEOUT register will contain the value zero.
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Registers
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SDIi_READY
8.4.3 Protection
The SDI register space is protected from malicious usage via access permissions
held in each SDIi_CONTROL register. The reset behavior is that accesses to the
SDI registers are only allowed in supervisor mode.
The protection can be loosened to allow user access to an SDIi_DATA and
SDIi_READY registers. This is achieved via the SDIi_CONTROL register,
PRIV[1:0] two bit field, indicating the access allowed for each SDI.
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Value
Comment
PRIV_NOUSER
PRIV_USER
Reserved
Reserved
Accessing the SDIi_DATA register may alter the state of the processor observed by
the interrupted processor.
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Exceptions, interrupts, reset and restart
73
The SDIi_TIMEOUT register will need increasing from the zero value that caused
the exception, otherwise the exception will be triggered again immediately.
The timeout exception is generated by the processor and not the channel.
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Normally the output channel will be the master. However in cases where the output
channel is connected to a dumb peripheral it may be necessary to make the input
channel the master, particularly where this is a processor interface.
The restart structure outlined will work across asynchronous clock boundaries.
Data
Transport
Data
Transport
Slave
Master
Control
Transport
ResetReq
Control
Transport
ResetAck
ResetReques
t
ResetAck
3
1
4
2
1) Master requests reset Subsystem resets itself and consumes all data
presented at inputs. RESETREQUEST is forwarded to other
slave side subsystems.
2) All units in reset After subsystem has reset itself AND all slave side
subsystems have sent RESETACK, RESETACK can be
forwarded to master.
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Control
registers
The ST231 control registers contain processor state which is not commonly accessed
by application code. This includes accessing the TLB, PSW, exception registers and
breakpoint registers.
9.2 Exceptions
The control register unit generates an exception when a load or store tries to:
Access a control register that does not exist (CREG_NO_MAPPING),
Access to a control register without correct permissions
(CREG_ACCESS_VIOLATION),
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RO
ROF
RW
Read/write.
CF
CFRO
Name
Offset
Access
(U/S)
Comment
PSW
0xfff8
NA/RO
SAVED_PSW
0xfff0
NA/RW
SAVED_PC
0xffe8
NA/RW
HANDLER_PC
0xffe0
NA/RW
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Control register addresses
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Name
Offset
Access
(U/S)
EXCAUSE
0xffd8
NA/RO
EXADDRESS
0xffd0
NA/RW
SAVED_SAVED_PSW
0xffc0
NA/RW
SAVED_SAVED_PC
0xffb8
NA/RW
EXCAUSENO
0xff88
NA/RW
STATE1
0xfe00
NA/RW
VERSION
0xffc8
NA/RO
PERIPHERAL_BASE
0xffb0
NA/RO
SCRATCH1
0xffa8
NA/RW
SCRATCH2
0xffa0
NA/RW
SCRATCH3
0xff98
NA/RW
SCRATCH4
0xff90
NA/RW
TLB_INDEX
0xff80
NA/RW
Comment
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Name
Offset
Access
(U/S)
Comment
TLB_ENTRY0
0xff78
NA/RW
TLB_ENTRY1
0xff70
NA/RW
TLB_ENTRY2
0xff68
NA/RW
TLB_ENTRY3
0xff60
NA/RW
TLB_EXCAUSE
0xff58
NA/RW
TLB_CONTROL
0xff50
NA/RW
TLB_REPLACE
0xff48
NA/RW
Replacement pointer.
TLB_ASID
0xff40
NA/RW
RESERVEDFF38
0xff38
NA/RO
Reserved
RESERVEDFF30
0xff30
NA/RO
Reserved
RESERVEDFF28
0xff28
NA/RO
Reserved
RESERVEDFF20
0xff20
NA/RO
Reserved
RESERVEDFF18
0xff18
NA/RO
Reserved
RESERVEDFF10
0xff10
NA/RO
Reserved
RESERVEDFF08
0xff08
NA/RO
Reserved
RESERVEDFF00
0xff00
NA/RO
Reserved
SCU_BASE0
0xd000
NA/RW
SCU_LIMIT0
0xd008
NA/RW
SCU_BASE1
0xd010
NA/RW
SCU_LIMIT1
0xd018
NA/RW
SCU_BASE2
0xd020
NA/RW
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Control register addresses
81
Name
Offset
Access
(U/S)
Comment
SCU_LIMIT2
0xd028
NA/RW
SCU_BASE3
0xd030
NA/RW
SCU_LIMIT3
0xd038
NA/RW
DBREAK_LOWER
0xfe80
NA/RW
DBREAK_UPPER
0xfe78
NA/RW
DBREAK_CONTROL
0xfe70
NA/RW
IBREAK_LOWER
0xfdd0
NA/RW
IBREAK_UPPER
0xfdc8
NA/RW
IBREAK_CONTROL
0xfdc0
NA/RW
PM_CR
0xf800
NA/RW
PM_CNT0
0xf808
NA/RW
PM_CNT1
0xf810
NA/RW
PM_CNT2
0xf818
NA/RW
PM_CNT3
0xf820
NA/RW
PM_PCLK
0xf828
NA/RW
SDI0_DATA
0xe000
CF/RW
SDI 0 data.
SDI0_READY
0xe008
CFRO/RO
SDI 0 ready.
SDI0_CONTROL
0xe010
NA/RW
SDI 0 control.
SDI0_COUNT
0xe018
NA/RW
SDI 0 count.
SDI0_TIMEOUT
0xe020
NA/RW
SDI 0 timeout.
SDI1_DATA
0xe400
CF/RW
SDI 1 data.
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Name
Offset
Access
(U/S)
Comment
SDI1_READY
0xe408
CFRO/RO
SDI 1 ready.
SDI1_CONTROL
0xe410
NA/RW
SDI 1 control.
SDI1_COUNT
0xe418
NA/RW
SDI 1 count.
SDI1_TIMEOUT
0xe420
NA/RW
SDI 1 timeout.
SDI2_DATA
0xe800
CF/RW
SDI 2 data.
SDI2_READY
0xe808
CFRO/RO
SDI 2 ready.
SDI2_CONTROL
0xe810
NA/RW
SDI 2 control.
SDI2_COUNT
0xe818
NA/RW
SDI 2 count.
SDI2_TIMEOUT
0xe820
NA/RW
SDI 2 timeout.
SDI3_DATA
0xec00
CF/RW
SDI 3 data.
SDI3_READY
0xec08
CFRO/RO
SDI 3 ready.
SDI3_CONTROL
0xec10
NA/RW
SDI 3 control.
SDI3_COUNT
0xec18
NA/RW
SDI 3 count.
SDI3_TIMEOUT
0xec20
NA/RW
SDI 3 timeout.
RESERVEDFE40
0xfe40
NA/RO
Reserved
RESERVEDFE38
0xfe38
NA/RO
Reserved
RESERVEDFE30
0xfe30
NA/RO
Reserved
RESERVEDFE28
0xfe28
NA/RO
Reserved
RESERVEDFE20
0xfe20
NA/RO
Reserved
RESERVEDFE18
0xfe18
NA/RO
Reserved
RESERVEDFE10
0xfe10
NA/RO
Reserved
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Machine state register
83
Name
Offset
Access
(U/S)
Comment
RESERVEDFE08
0xfe08
NA/RO
Reserved
Bit(s)
Writeable
Reset
Comment
PARTITION
[1:0]
RW
0x0
Reserved
[31:2]
RO
0x0
Reserved.
When the partition field is changed, the current data in the cache is not altered in
any way. If the software wishes to force data out of a particular partition following a
change to this register, the data must be purged from the cache in the normal way
(prgadd or prgset).
For more details on cache partitioning see Section 7.3.2: Data cache partitioning on
page 54.
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Version register
Bit(s)
Writeable
Reset
Comment
PRODUCT_ID
[15:0]
RO
0x000
0
Chip ID.
CORE_VERSION
[23:16]
RO
0x05
DSU_VERSION
[31:24]
RO
0x02
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Timers
10
Three timers are provided on the ST231. These are controlled by registers mapped
into the ST231 memory space (see Chapter 11: Peripheral addresses on page 89).
10.1 Operation
For each of the three timers (i = 0, 1, 2), the TIMECOUNTI register is the current
value of the timer. When a timer is enabled its TIMECOUNTI value is decremented
on each timer tick until zero is reached. Upon the next tick, TIMECOUNTI is
loaded with TIMECONSTI, the STATUS bit in TIMECONTROLI register is then
set.
The ENABLE bit in the TIMECONTROLI register controls the enabling of
interrupts for each timer. The STATUS bit in the TIMECONTROLI register is
ANDed with the interrupt enable to produce the timer interrupt line. When a value
of 1 is written to the STATUS bit it is cleared (and thus the interrupt is cleared).
Timer counting is enabled by the ENABLE bit in the TIMECONTROLI register.
Counters are not reset when disabled, hence initial values can be written using the
TIMECOUNTI registers.
The frequency of timer ticks is controlled by programming the TIMEDIVIDE
register.
These registers are covered in more detail in the following subsections.
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Operation
10.1.1 TIMEDIVIDE
The TIMEDIVIDE register sets the number of bus clock cycles between each timer
tick. This register can be programmed with values between 0 and 65535 (only the
bottom 16 bits are used). The divide value is equal to the value of this register plus
one. This register will reset to zero (divide by 1). Writing this register sets the
divide value and reading it returns the current divide value.
It is expected that the boot code will setup the TIMEDIVIDE register so that timer
ticks occur every 1us.
10.1.2 TIMECOUNTi
Name
Bit(s)
Writeable
Reset
Comment
COUNT
[31:0]
RW
0x0
The TIMECOUNTi registers hold the current values of the timer counters.
Writing to these registers can be used to set initial values for the counters.
10.1.3 TIMECONSTi
Name
Bit(s)
Writeable
Reset
Comment
CONST
[31:0]
RW
0x0
The TIMECONSTi registers set the value to be reloaded into each corresponding
timer on reaching zero. If interrupts are enabled, this will define the number of
ticks between interrupts.
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Timer interrupts
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10.1.4 TIMECONTROLi
Name
Bit(s)
Writeable
Reset
Comment
ENABLE
RW
0x0
INTENABLE
RW
0x0
STATUS
RW
0x0
Reserved
[31:3]
RO
0x0
Reserved
The TIMECONTROLi registers enable the timer, enable timer interrupts and are
used to clear a timer interrupt.
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Peripheral
addresses
11
On the ST231 the interrupt controller, DSU, DSU ROM and the timers are memory
mapped peripherals. Under normal usage these peripherals should, with the
exception of the DSU ROM, be mapped in an uncacheable region in the TLB.
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Peripheral addresses
RO
ROF
RW
Read/write.
CF
CFRO
Name
Offset
Access
(U/S)
Comment
INTPENDING0
0x0000
RO
INTPENDING1
0x0008
RO
INTMASK0
0x0010
RW
INTMASK1
0x0018
RW
INTTEST0
0x0020
RW
INTTEST1
0x0028
RW
INTCLR0
0x0030
RW
INTCLR1
0x0038
RW
INTSET0
0x0040
RW
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Peripheral addresses
91
Name
Offset
Access
(U/S)
Comment
INTSET1
0x0048
RW
INTMASKCLR0
0x0108
RW
INTMASKCLR1
0x0110
RW
INTMASKSET0
0x0118
RW
INTMASKSET1
0x0120
RW
TIMECONST0
0x0200
RW
Timer constant.
TIMECOUNT0
0x0208
RW
Timer counter.
TIMECONTROL0
0x0210
RW
Timer control
TIMECONST1
0x0218
RW
Timer constant.
TIMECOUNT1
0x0220
RW
Timer counter.
TIMECONTROL1
0x0228
RW
Timer control
TIMECONST2
0x0230
RW
Timer constant.
TIMECOUNT2
0x0238
RW
Timer counter.
TIMECONTROL2
0x0240
RW
Timer control.
TIMEDIVIDE
0x0248
RW
Timer divide.
RESERVED50
0x0050
RO
Reserved
RESERVED58
0x0058
RO
Reserved
RESERVED60
0x0060
RO
Reserved
RESERVED68
0x0068
RO
RReserved
RESERVED70
0x0070
RO
Reserved
RESERVED78
0x0078
RO
Reserved
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Peripheral addresses
Name
Offset
Access
(U/S)
Comment
RESERVED80
0x0080
RO
Reserved
RESERVED88
0x0088
RO
Reserved
RESERVED90
0x0090
RO
Reserved
RESERVED98
0x0098
RO
Reserved
RESERVED100
0x0100
RO
Reserved
Name
Offset
Access
(U/S)
Comment
DSR0
0x0000
RO
DSU version.
DSR1
0x0008
RW
DSU status.
DSR2
0x0010
RW
DSU output.
DSR3
0x0018
RW
DSU communication.
DSR4
0x0020
RW
DSU communication.
DSR5
0x0028
RW
DSU communication.
DSR6
0x0030
RW
DSU communication.
DSR7
0x0038
RW
DSU communication.
DSR8
0x0040
RW
DSU communication.
DSR9
0x0048
RW
DSU communication.
DSR10
0x0050
RW
DSU communication.
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Peripheral addresses
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Name
Offset
Access
(U/S)
Comment
DSR11
0x0058
RW
DSU communication.
DSR12
0x0060
RW
DSU communication.
DSR13
0x0068
RW
DSU communication.
DSR14
0x0070
RW
DSU communication.
DSR15
0x0078
RW
DSU communication.
DSR16
0x0080
RW
DSU communication.
DSR17
0x0088
RW
DSU communication.
DSR18
0x0090
RW
DSU communication.
DSR19
0x0098
RW
DSU communication.
DSR20
0x00a0
RW
DSU communication.
DSR21
0x00a8
RW
DSU communication.
DSR22
0x00b0
RW
DSU communication.
DSR23
0x00b8
RW
DSU communication.
DSR24
0x00c0
RW
DSU communication.
DSR25
0x00c8
RW
DSU communication.
DSR26
0x00d0
RW
DSU communication.
DSR27
0x00d8
RW
DSU communication.
DSR28
0x00e0
RW
DSU communication.
DSR29
0x00e8
RW
DSU communication.
DSR30
0x00f0
RW
DSU communication.
DSR31
0x00f8
RW
DSU communication.
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Peripheral addresses
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12
Interrupt
controller
12.1 Architecture
The structure of the interrupt controller is shown in Figure 11.
External
events
64 lines
(3 dedicated
to the timer)
Mask register
Test register
64 bits
Pending register
OR
AND
64 lines
OR
Interrupt line
to processor
64 bits
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Operation
12.2 Operation
An interrupting event takes an interrupt line high. This is then sampled, causing
the corresponding bit in the 64-bit INTPENDING register to be set. The
INTPENDING register is then parallel AND-ed with the INTMASK register. The
masked interrupts are then OR-red into a single interrupt line that is presented to
the processor core.
This architecture ensures that:
all external interrupts will interrupt the processor,
interrupts can be individually enabled or disabled.
Setting or clearing bits in the INTMASK register enables or disables the
corresponding interrupt lines.
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12.3.1.1 INTPENDING0
Name
Bit(s)
Writeable
Reset
Comment
TIMER0
RO
0x0
TIMER1
RO
0x0
TIMER2
RO
0x0
Reserved
[31:3]
RO
0x0
12.3.1.2 INTPENDING1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RO
0x0
Bit(s)
Writeable
Reset
Comment
TIMER0
RW
0x0
TIMER1
RW
0x0
TIMER2
RW
0x0
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Interrupt registers
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:3]
RW
0x0
12.3.2.2 INTMASK1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RW
0x0
Bit(s)
Writeable
Reset
Comment
TIMER0
RW
0x0
TIMER1
RW
0x0
TIMER2
RW
0x0
Reserved
[31:3]
RW
0x0
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12.3.3.2 INTMASKCLR1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RW
0x0
12.3.3.3 INTMASKSET0
Name
Bit(s)
Writeable
Reset
Comment
TIMER0
RW
0x0
TIMER1
RW
0x0
TIMER2
RW
0x0
Reserved
[31:3]
RW
0x0
12.3.3.4 INTMASKSET1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RW
0x0
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Interrupt registers
Bit(s)
Writeable
Reset
Comment
TIMER0
RW
0x0
TIMER1
RW
0x0
TIMER2
RW
0x0
Reserved
[31:3]
RW
0x0
12.3.4.2 INTTEST1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RW
0x0
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Interrupt registers
101
Bit(s)
Writeable
Reset
Comment
TIMER0
RW
0x0
TIMER1
RW
0x0
TIMER2
RW
0x0
Reserved
[31:3]
RW
0x0
12.3.5.2 INTCLR1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RW
0x0
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Interrupt registers
12.3.5.3 INTSET0
Name
Bit(s)
Writeable
Reset
Comment
TIMER0
RW
0x0
TIMER1
RW
0x0
TIMER2
RW
0x0
Reserved
[31:3]
RW
0x0
12.3.5.4 INTSET1
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[31:0]
RW
0x0
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Programming
103
12.4 Programming
12.4.1 Enabling/disabling interrupts
Interrupts are enabled and disabled by setting and clearing the appropriate bits in
the INTMASK register.
The INTMASK register can written to directly as two 32-bit words, or bit-wise using
the mask clear and mask set locations, see Section 12.3.3: Interrupt mask set and
clear registers (INTMASKSET and INTMASKCLR) on page 98.
INTTEST register bits are not reset when the interrupt is taken and must be
explicitly cleared by the program.
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Debugging
support
13
13.1 Overview
Debugging support on the ST231 is provided by 4 main components.
Core
DSU
Debug ROM
Host debug
interface
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Core
13.2 Core
13.2.1 Debug interrupts
The ST231 can accept and service interrupts from the DSU. Debug interrupts are
higher priority than normal interrupts, cannot be masked, and place the ST231 in a
debug state.
A debug interrupt can be triggered either by an event from the host (see
Section 13.5.2.1: Generating debug interrupts on page 119) or by an external trigger
(see Section 13.3.3.2: DSU status register (DSR1) on page 111).
13.2.1.1 Entering debug mode
A debug interrupt is handled differently to other external interrupts. When a debug
interrupt is taken, the TLB is disabled and the process jumps to the start of the
debug ROM.
Taking a debug interrupt can be summarized as:
NEXT_PC DEBUG_HANDLER_PC;
// Branch to handler
SAVED_SAVED_PSW SAVED_PSW;
SAVED_SAVED_PC SAVED_PC;
SAVED_PSW PSW;
SAVED_PC BUNDLE_PC;
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The default debug ROM itself is not aware of virtual memory issues and will
provide the host with a physical view of memory. If address translation is in use, it
is up to the operating system to install its own debug handler that is virtual
memory aware.
13.2.1.2 Exiting debug mode
When the DEBUG_MODE bit is cleared in the PSW, debug mode is exited, and
normal mode re-entered. If a debug interrupt is pending when the core leaves debug
mode, it will be re-entered as normal (see Section 13.2.1.1: Entering debug mode on
page 106).
Although clearing the DEBUG_MODE bit causes the ST231 to exit debug mode,
attempting to set the DEBUG_MODE bit when it is not already set does not cause
the core to enter debug mode and the DEBUG_MODE bit remains clear. Debug
mode can only be entered by taking a debug interrupt from the DSU.
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Core
As the PC does not contain bits 1:0, these bits are ignored in any instruction address
comparisons.
.
Name
Bit(s)
Writeable
Reset
Comment
BRK_IN_RANGE
RW
0x0
BRK_OUT_RANGE
RW
0x0
BRK_EITHER
RW
0x0
BRK_MASKED
RW
0x0
BRK_RESERVED4
[31:4]
RO
0x0
Reserved
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13.3.1 Architecture
The architecture of the DSU is shown in Figure 12.
Host
Host
debug
interface
Control
block
Shared
register
bank
Debug
ROM
DEBUG_INTERRUPT
STBus port
DEBUG_INTERRUPT_TAKEN
ST200
ST220Core
core
The DSU is controlled by a host via the debug interface. The DSU control block
interacts directly with the ST231 core via the DEBUG_INTERRUPT and
DEBUG_INTERRUPT_TAKEN signals, and the shared register block.
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The shared registers can also be accessed via the STBus port.
Value
Comment
REG0
REG1
REG2
REGGEN
3-30
The STBus addresses of the DSU registers are detailed in Chapter 11: Peripheral
addresses on page 89.
13.3.2.1 Shared access conventions
The DSU shared registers are accessible independently from both the DSU and the
STBus. The ST231 and DSU have no hardware support for synchronizing writes, so
software conventions are used to prevent write conflicts.
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111
Bit(s)
Writeable
Reset
Comment
PRODUCT_ID
[15:0]
RO
0x000
0
Chip ID.
CORE_VERSION
[23:16]
RO
0x05
DSU_VERSION
[31:24]
RO
0x02
Bit(s)
Writeable
Reset
Comment
DEBUG_INTERRUPT_TA
KEN
RO
0x0
Value of
DEBUG_INTERRUPT_TAKEN signal,
active high.
SUPERVISOR_WRITE_E
NABLE
RW
0x1
USER_WRITE_ENABLE
RW
0x0
BIGENDIAN
RO
0x0
Reserved
RO
0x0
Reserved
OUTPUT_PENDING
RO
0x0
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Name
Bit(s)
Writeable
Reset
Comment
TRIGGER_IN
RO
0x0
TRIGGER_OUT
RW
0x0
TRIGGER_ENABLE
RW
0x0
Reserved
[15:9]
RO
0x0
Reserved
SW_FLAGS
[31:16]
RW
0x0
Bit(s)
Writeable
Reset
Comment
DATA
[7:0]
RW
0x0
Output data.
Reserved
[31:8]
RO
0x0
Always zero.
If OUTPUT_PENDING is non-zero then the byte most recently written has not yet
been sent to the HTI and additional writes to the DSR2 will not affect the byte
being sent even if they change the contents of the register.
Messages sent via the DSR2 may be delayed if the DSU is busy.
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Where the DEBUG_ENABLE signal cannot be asserted, the boot ROM should start
with a tight loop, or perhaps just a delay loop, to allow time for the DSU to interrupt
the processor before it takes any action.
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Debug ROM
Register name
Host use
Target use
DSU_COMMAND
DSU_ARG1,2,3
DSU_RESPONSE
When the command is complete, the default debug handler stores the results in the
argument registers and sets a success code in the response register.
13.4.2.3 Default handler commands
DSU_PEEK
(DSU_COMMAND =4)
Reads the 32-bit memory location addressed by DSU_ARG1 and returns the
data in DSU_ARG1. The address must be word aligned. If the operation is
successful DSU_RESPONSE is set to DSU_PEEKED (1) and a
TAPLINK_EVENT_DEFAULT (reason=7) event is sent to the HTI.
Note:
(DSU_COMMAND = 3)
Writes the 32-bit data word in DSU_ARG2 to the memory location addressed by
DSU_ARG1. The address must be word aligned. If the operation is successful
DSU_RESPONSE is set to DSU_POKED (2) and a
TAPLINK_EVENT_DEFAULT (reason=7) event is sent to the HTI.
DSU_CALL_OR_RETURN
(DSU_COMMAND = 1)
Calls the routine addressed by DSU_ARG1. If the called routine does not return
this is effectively a branch. If DSU_ARG1 is zero this is a return call. Just before
calling the user routine, or returning from a call, DSU_RESPONSE is set to
DSU_RETURNING (3) and a TAPLINK_EVENT_DEFAULT (reason=7) event is
sent to the host.
DSU_FLUSH (DSU_COMMAND = 2)
Flushes the address range delimited by DSU_ARG1 and DSU_ARG2 from data
and instruction caches.
If a command was successful DSU_RESPONSE is set to DSU_FLUSHED (4)
and a TAPLINK_EVENT_DEFAULT (reason=7) event is sent to the host.
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Designation
Comment
DSR3
DSR_USER_DEBUG_HANDLER
DSR4-8a
DSU_ARG4-8
DSR9a
DSU_ARG3
Command argument 3
DSR10a
DSU_ARG2
DSU_FLUSH.
DSR11a
DSU_ARG1
DSR12
DSU_COMMAND
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Debug ROM
DSR
number
Designation
Comment
DSR13
DSU_RESPONSE
DSR14
Context saving
Saves SCR4_REGb
DSR15
Context saving
Saves SCR1_REGb
DSR16
Context saving
Saves SCR2_REGb
DSR17
Context saving
Saves SCR3_REGb
DSR18
Context saving
DSR19
Context saving
Saves LINK_REGb
DSR20
Context saving
Saves HANDLER_PC
DSR21
Context saving
Saves SAVED_SAVED_PSW
DSR22
Context saving
Saves SAVED_SAVED_PC
DSR23
Context saving
Saves SAVED_PSW
DSR24
Context saving
Saves SAVED_PC
DSR25
Context saving
Saves EXCAUSENO
DSR26
Context saving
Saves EXADDRESS
DSR27-30
Unused
Unused
DSR31
Context saving
Saves DSR1
Table 52: DSU command registers
a. Argument registers are placed before the command register in the address space so
that a command and its arguments can be loaded with a single poke operation.
b. As defined by the toolchain header files.
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HTI
adapter
Host
JTAG
DSU
ST200 core
DSR address
Peek
DSR address
Second...
Third...
2nd
byte
Note:
Messages are transmitted little endian, independent of the endianness of the ST231
core.
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Peek
word count
7
Peeked
word count
7
Event
word count
Poke
channel
reason
Header byte
Subsequent bytes
peeked messages are not supported from the host to the target and their behavior is
undefined.
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13.5.2 Operation
13.5.2.1 Generating debug interrupts
In order to interrupt the core, the host sends an event with reason=1. The event is
decoded by the DSU and a DEBUG_INTERRUPT signal is sent to the ST231. When
the ST231 takes the interrupt (as described in Section 13.2.1: Debug interrupts on
page 106) the DEBUG_INTERRUPT_TAKEN signal goes high.
The functionality available to the host is then dependent on the debug handler
program running. The default handler uses designated shared registers to provides
the higher level operations detailed in Section 13.4.2.3: Default handler commands
on page 114.
13.5.2.2 Core initiated events
The core can also request service from the host by sending it an event message.
This is done by writing the event to the DSR2 (the output register). The channel
and reason fields of the event message are not examined by the hardware and can
be used as desired by the software.
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Performance
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14
14.1 Events
The programmable events supported by the ST231 are the following:
Name
Value
Comment
PM_EVENT_DHIT
PM_EVENT_DMISS
PM_EVENT_DMISSCYCLES
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Events
Name
Value
Comment
PM_EVENT_PFTISSUED
PM_EVENT_PFTHITS
PM_EVENT_WBHITS
PM_EVENT_IHIT
PM_EVENT_IMISS
PM_EVENT_IMISSCYCLES
PM_EVENT_IBUFINVALID
PM_EVENT_BUNDLES
10
Bundles executed.
PM_EVENT_LDST
11
PM_EVENT_TAKENBR
12
PM_EVENT_NOTTAKENBR
13
PM_EVENT_EXCEPTIONS
14
PM_EVENT_INTERRUPTS
15
Number of interrupts.
PM_EVENT_BUSREADS
16
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Name
Value
Comment
PM_EVENT_BUSWRITES
17
PM_EVENT_OPERATIONS
18
PM_EVENT_WBMISSES
19
PM_EVENT_NOPBUNDLES
20
PM_EVENT_LONGIMM
21
PM_EVENT_ITLBMISS
22
PM_EVENT_DTLBMISS
23
PM_EVENT_UTLBHIT
24
PM_EVENT_ITLBWAITCYC
LES
25
PM_EVENT_DTLBWAITCYC
LES
26
PM_EVENT_UTLBARBITRA
TIONCYCLES
27
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Access to registers
Name
Value
Comment
Reserved
28-31
All the events relating to the architectural state of the machine are sampled when
bundles commit.
Bit(s)
Writeable
Reset
Comment
ENB
RW
0x0
RST
RW
0x0
IDLE
RW
0x0
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Event counters (PM_CNTi)
125
Name
Bit(s)
Writeable
Reset
Comment
Reserved
[11:3]
RO
0x0
Reserved
EVENT0
[16:12]
RW
0x0
EVENT1
[21:17]
RW
0x0
EVENT2
[26:22]
RW
0x0
EVENT3
[31:27]
RW
0x0
If counting is enable when the PM_CR register is written to any event that is
triggered on the same bundle/cycle as the write is ignored. For example if one of the
event counters were counting load/store operations then a store to the PM_CR
register will not be included in the count.
Note:
When the performance monitoring counters are enabled the core will not enter idle
mode (see Section 2.4.1: Idle mode macro on page 11).
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System
The big endian enable input (big_enable_enable) is used to select the endiness of
the core. If this signal is low after reset then the core will operate in little endian
mode. If however this signal is high the core will operate in big endian mode.
Size
I/O
Timing
Comment
periph_addr
[11:0]
static
boot_addr
[29:0]
static
Boot address
big_endian_enable
static
debug_enable
static
15.2 System
The system pins provide the cpu clock (clk_cpu), the bus clock (clk_bus) and the
power on reset.
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129
Size
I/O
Timing
Comment
clk_cpu
Cpu clock
clk_bus
Bus clock
rst_in_n
rst_out_n
clk_cpu/mid
Size
I/O
Timing
Comment
irq
[63:3]
clk_bus/late
irq_timer_out
[2:0]
clk_bus/early
clk_cpu/late
irq_master_in
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SDI Interfaces
The input channels are a subset of an STBus type 1 target and the master channels
are a subset of an STBus type 1 master.
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Size
I/O
Timing
Comment
sdi0_data
[31:0]
clk_cpu/mid
sdi0_req
clk_cpu/mid
sdi0_reset_in
clk_cpu/mid
sdi0_master_not_slave
static
sdi0_gnt
clk_cpu/mid
sdi0_reset_out
clk_cpu/mid
clk_cpu/mid
sdi1_req
clk_cpu/mid
sdi1_reset_in
clk_cpu/mid
sdi1_master_not_slave
static
sdi1_gnt
clk_cpu/mid
sdi1_reset_out
clk_cpu/mid
clk_cpu/mid
sdi2_req
clk_cpu/mid
sdi2_reset_in
clk_cpu/mid
sdi2_master_not_slave
static
sdi2_gnt
clk_cpu/mid
sdi2_reset_out
clk_cpu/mid
clk_cpu/mid
sdi1_data
sdi2_data
sdi3_data
[31:0]
[31:0]
[31:0]
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Name
Size
I/O
Timing
Comment
sdi3_req
clk_cpu/mid
sdi3_reset_in
clk_cpu/mid
sdi3_master_not_slave
static
sdi3_gnt
clk_cpu/mid
sdi3_reset_out
clk_cpu/mid
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Size
req_ini
I/O
Timing
Comment
clk_cpu/mid
Request
data_ini
[63:0]
clk_cpu/mid
Request data
add_ini
[31:3]
clk_cpu/mid
Request address
opc_ini
[7:0]
clk_cpu/mid
Request opcode
src_ini
[1:0]
clk_cpu/mid
tid_ini
[4:0]
clk_cpu/mid
Request transaction ID
be_ini
[7:0]
clk_cpu/mid
eop_ini
clk_cpu/mid
gnt_ini
clk_cpu/mid
Request grant
r_req_ini
clk_cpu/mid
Response request
clk_cpu/mid
Response data
clk_cpu/mid
Response opcode
r_data_ini
[63:0]
r_opc_ini
r_src_ini
[1:0]
clk_cpu/mid
r_tid_ini
[3:0]
clk_cpu/mid
Response transaction ID
clk_cpu/mid
r_eop_ini
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Debugging interface
Size
req_tar
I/O
Timing
Comment
clk_bus/late
Request
data_tar
[31:0]
clk_bus/late
Request data
add_tar
[19:2]
clk_bus/late
Request address
opc_tar
[7:0]
clk_bus/late
Request opcode
src_tar
[7:0]
clk_bus/late
tid_tar
[7:0]
clk_bus/late
Request transaction ID
gnt_tar
clk_bus/early
Request grant
r_req_tar
clk_bus/early
Response request
clk_bus/early
Response data
clk_bus/early
Response opcode
r_data_tar
[31:0]
r_opc_tar
r_src_tar
[7:0]
clk_bus/early
r_tid_tar
[7:0]
clk_bus/early
Response transaction ID
r_eop_tar
clk_bus/early
r_gnt_tar
clk_bus/late
Response grant
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Security interface
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Size
I/O
Timing
Comment
clk_tck
Tap clock
tmx_tdi
clk_tck/late
tmx_tms
clk_tck/late
Tap mode
tmx_not_trst
clk_tck/late
tmx_tdo
clk_tck/early
tmx_enable_tdo
clk_tck/early
tmx_trigger_in
clk_tck/late
tmx_trigger_out
clk_tck/early
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Size
I/O
Timing
Comment
clk_cpu/early
clk_cpu/early
sec_priv_out
clk_cpu/early
sec_handlerchange_out
clk_cpu/early
sec_tlbenabled_out
clk_cpu/early
sec_valid_out
sec_physaddr_out
[31:2]
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137
Size
I/O
tst_scanout
[88:1]
tst_scanin
[88:1]
tst_gclkenable
tst_scanenable
tst_scanmode
tst_scanout_bbad_st230
tst_scanin_bbad_st230
tst_bbad_st230
tst_bend_st230
tst_rst_n
BIST control
tst_membist
[4:0]
Timing
Comment
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Execution
model
16
16.1 Introduction
This chapter defines the way in which bundles are executed in terms of their
component operations.
In the absence of any exceptional behavior the execution is straightforward.
The bundle is fetched from memory. The operations within it are decoded, and their
operands read. The operations then execute and writeback their results to the
architectural state of the machine. It is important to note that all instructions in a
bundle commit their results to the state of the machine at the same point in time.
This is known as the commit point.
In the presence of exceptional behavior the commit point is used to distinguish
between recoverable and non-recoverable exceptions.
Exceptions which can be detected prior to the commit point are treated as
recoverable. They are recoverable because the machine state has not been updated,
hence the state prior to the execution of the bundle can be recovered. In some cases
the cause of the exception can be corrected and the bundle restarted.
Conversely non-recoverable exceptions are detected after the commit point.
Machine state has been updated and in some cases it may not even be clear which
bundle caused the exception. Non-recoverable exceptions are naturally of a serious
nature and cannot be restarted. The cause is normally an error in the external
memory system, these translate to a bus error exception. On the ST231 this is the
only non-recoverable exception.
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141
Start
Bus error?
Yes
Yes
Data Cache?
No
No
Interrupt?
THROW
STBUS_IC_ERROR
Yes
THROW
STBUS_DC_ERROR
No
Debug
interrupt?
No
Yes
NumWords(PC) > 4
Yes
THROW
EXTERN_INT
NUM_OPERS
BUNDLE_SIZE
THROW
ILL_INST
No
NumWords(PC) - NumExtImms(PC);
NumWords(PC) x 4;
PC Register(BUNDLE_PC + BUNDLE_SIZE);
Exception
detected?
Yes
No
InitiateDebugIntHandler();
InitiateExceptionHandler();
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Functions
16.3 Functions
The flow chart, Figure 16, contains a number of functions which abstract out some
the details. Those functions are described in this section. Starting with those used
in the decode phase, then execution of operations, and finally the exceptional cases.
Description
NumWords(address)
NumExtImms(address)
Description
Pre-commit(n)
Commit(n)
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Description
InitiateExceptionHandler()
InitiateDebugIntHandler()
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Specification
notation
17
17.1 Overview
The language used to describe the operations, exceptions and interrupts has the
following features:
a simple variable and type system (see Section 17.2),
expressions (see Section 17.3),
statements (see Section 17.4),
notation for the architectural state of the machine (see Section 17.5).
Additional mechanisms are defined to model memory (Section 17.6.2), control
registers (Section 17.6.3), and cache instructions (Section 17.6.4).
Each instruction is described using informal text as well as the formal language.
Sometimes it is inappropriate for one of these descriptions to convey the full
semantics. In such cases the two descriptions must be taken together to constitute
the full specification. In the case of an ambiguity or a conflict, the notational
language takes precedence over the text.
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17.2.1 Integer
An integer variable can take the value of any mathematical integer. No limits are
imposed on the range of integers supported. Integers obey their standard
mathematical properties. Integer operations do not overflow. The integer operators
are defined so that singularities do not occur. For example, no definition is given to
the result of divide by zero; the operator is simply not available when the divisor is
zero.
The representation of literal integer values is achieved using the following
notations:
Unsigned decimal numbers are represented by the regular expression: [0-9]+
Signed decimal numbers are represented by the regular expression: -[0-9]+
Hexadecimal numbers are represented by the regular expression:
0x[0-9a-fA-F]+
Binary numbers are represented by the regular expression: 0b[0-1]+
These notations are standard and map onto integer values in the obvious way.
Underscore characters (_) can be inserted into any of the above literal
representations. These do not change the represented value but can be used as
spacers to aid readability.
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17.2.2 Boolean
A boolean variable can take two values:
Boolean false. The literal representation of boolean false is FALSE.
Boolean true. The literal representation of boolean true is TRUE.
17.2.3 Bit-fields
Bit-fields are provided to define bit-accurate storage.
Bit-fields containing arbitrary numbers of bits are supported. A bit-field of b bits
contains bits numbered from 0 (the least significant bit) up to b-1 (the most
significant bit). Each bit can take the value 0 or the value 1.
Bit-fields are mapped to, and from, unsigned integers in the usual way. If bit i of a
b-bit bitfield, where i is in [0, b], is set then it contributes 2i to the integral value of
the bitfield. The integral value of the bit-field as a whole is an integer in the range
[0, 2b).
Bit-fields are mapped to, and from, signed integers using twos complement
representation. This is as above, except that the bit b-1 of a b-bit bitfield
contributes -2(b-1) to the integral value of the bitfield. The integral value of the
bit-field as a whole is an integer in the range [-2b-1, 2b-1].
A bitfield may be used in place of an integer value. In this case the integral value of
the bitfield is used. A bit-field variable may be used in place of an integer variable
as the target of an assignment. In this case the integer must be in the range of
values supported by the bit-field.
17.2.4 Arrays
One-dimensional arrays of the above types are also available. Indexing into an
n-element array A is achieved using the notation A[i] where A is an array of some
type and i is an integer in the range [0, n]. This selects the ith. element of the array
A. If i is zero this selects the first entry, and if i is n-1 then this selects the last
entry. The type of the selected element is the base type of the array.
Multi-dimensional arrays are not provided.
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Expressions
17.3 Expressions
Expressions are constructed from monadic operators, dyadic operators and
functions applied to variables and literal values.
There are no defined precedence and associativity rules for the operators.
Parentheses are used to specify the expression unambiguously.
Sub-expressions can be evaluated in any order. If a particular evaluation order is
required, then sub-expressions must be split into separate statements.
Description
i+j
Integer addition
i-j
Integer subtraction
ij
Integer multiplication
i/j
Integer division*
i\j
Integer remainder*
Description
-i
Integer negation
|i|
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The division operator truncates towards zero. The remainder operator is consistent
with this. The sign of the result of the remainder operator follows the sign of the
dividend. Division and remainder are not defined for a divisor of zero.
For a numerator (n) and a denominator (d), the following properties hold where
d0:
n = d ( n d ) + ( n\d )
( n ) d = ( n d ) = n ( d )
( n )\d = ( n\d )
n\ ( d ) = n\d
0 ( n\d ) < d where n 0 and d > 0
Description
n << b
n >> b
b
n2
nb =
( n 2b + 1 ) 2b
where
n0
where
n<0
Note that right shifting by b places is a division by 2b but with the result rounded
towards minus infinity. This contrasts with division, which rounds towards zero,
and is the reason why the right shift definition is separate for positive and negative
n.
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Expressions
Description
ij
ij
Integer bitwise OR
ij
~i
n<b>
where
<0
Care must be taken whenever the infinitely long twos complement representation
of a negative number is constructed. This representation will contain an infinite
number of higher bits with the value 1 representing the sign. Typically, a
subsequent conversion operation is used to discard these upper bits and return the
result back to a finite value.
Bitwise AND (), OR (), XOR () and NOT () are defined on integers as follows,
where b takes all values such that b 0:
BIT(i j, b) = BIT(i, b) BIT(j, b)
BIT(i j, b) = BIT(i j, b) + BIT(i j, b)
BIT(i j, b) = ( BIT(i, b) + BIT(j, b) )\2
BIT(~i, b) = 1 BIT(i, b)
Note:
Bitwise NOT of any finite positive i will result in a value containing an infinite
number of higher bits with the value 1 representing the sign.
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Description
i=j
ij
i<j
i>j
ij
ij
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Expressions
Description
i AND j
i OR j
i XOR j
NOT i
INT i
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Description
CountLeadingZeros(i)
Convert integer i to 32-bit bitfield and return the number of leading zeros in
the bitfield. For example:
If i<31> is 1 then the return value is 0.
If all bits are 0 then the return value is 32.
Table 73: Arithmetic functions
Description
ZeroExtendn(i)
SignExtendn(i)
i
0 FOR n
SignExtend n(i) =
n
i
2
0 FOR ( n 1 )
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Statements
For syntactic convenience, conversion functions are also defined for converting an
integer or boolean to a single bit and to a value which can be stored as a 32-bit
register. Table 75 shows the additional functions provided.
Operation
Description
Bit(i)
Register(i)
17.4 Statements
An instruction specification consists of a sequence of statements. These statements
are processed sequentially in order to specify the effect of the instruction on the
architectural state of the machine. The available statements are discussed in this
section.
Each statement has a semi-colon terminator. A sequence of statements can be
aggregated into a statement block using { to introduce the block and } to
terminate the block. A statement block can be used anywhere that a statement can.
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In cases where architecturally undefined behavior can occur in user mode, the
implementation will ensure that implemented behavior does not break the
protection model. Thus, the implemented behavior will be some execution flow that
is permitted for that user mode thread.
17.4.2 Assignment
The operator is used to denote assignment of an expression to a variable. An
example assignment statement is:
variable expression;
The expression can be constructed from variables, literals, operators and functions
as described in Section 17.3: Expressions on page 148. The expression is fully
evaluated before the assignment takes place. The variable can be an integer, a
boolean, a bit-field or an array of one of these types.
17.4.2.1 Assignment to architectural state
This is where the variable is part of the architectural state (as described in
Table 76: Scalar architectural state on page 158). The type of the expression and the
type of the variable must match, or the type of the variable must be able to
represent all possible values of the expression.
17.4.2.2 Assignment to a temporary
Alternatively, if the variable is not part of the architectural state, then it is a
temporary variable. The type of the variable is determined by the type of
expression. A temporary variable must be assigned to, before it is used in the
instruction specification.
17.4.2.3 Assignment of an undefined value
An assignment of the following form results in a variable being initialized with an
architecturally undefined value:
variable UNDEFINED;
After assignment the variable will hold a value which is valid for its type. However,
the value is architecturally undefined. The actual value can be unpredictable; that
is to say the value indicated by UNDEFINED can vary with each use of
UNDEFINED. Architecturally-undefined values can occur in both user and
privileged modes.
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Statements
17.4.3 Conditional
Conditional behavior is specified using IF, ELSE IF and ELSE.
Conditions are expressions that result in a boolean value. If the condition after an
IF is true, then its block of statements is executed and the whole conditional then
completes. If the condition is false, then any ELSE IF clauses are processed, in turn,
in the same fashion. If no conditions are met and there is an ELSE clause then its
block of statements is executed. Finally, if no conditions are met and there is no
ELSE clause, then the statement has no effect apart from the evaluation of the
condition expressions.
The ELSE IF and ELSE clauses are optional. In ambiguous cases, the ELSE matches
with the nearest IF.
For example:
IF (condition1)
block1
ELSE IF (condition2)
block2
ELSE
block3
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17.4.4 Repetition
Repetitive behavior is specified using the following construct:
REPEAT i FROM m FOR n STEP s
block
The block of statements is iterated n times, with the integer i taking the values:
m, m + s, m + 2s, m + 3s, up to m + (n - 1) s.
The behavior is equivalent to textually writing the block n times with i being
substituted with the appropriate value in each copy of the block.
The value of n must be greater or equal to 0, and the value of s must be non-zero.
The values of the expressions for m, n and s must be constant across the iteration.
The integer i must not be assigned to within the iterated block. The STEPs can be
omitted in which case the step-size takes the default value of 1.
17.4.5 Exceptions
Exception handling is triggered by a THROW statement. When an exception is
thrown, no further statements are executed from the operation specification; no
architectural state is updated. Furthermore, if any one of the operations in a bundle
triggers an exception then none of the operations will update any architectural
state.
If any operation in a bundle triggers an exception then an exception will be taken.
The actions associated with the taking of an exception are described in Section 5.2:
Exception handling on page 22.
There are two forms of throw statement:
THROW type;
and:
THROW type, value;
where type indicates the type of exception which is launched, and value is an
optional argument to the exception handling sequence. If value is not given, then it
is undefined.
The exception types and priorities are described in detail in Chapter 5: Traps:
exceptions and interrupts on page 21.
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Architectural state
17.4.6 Procedures
Procedure statements contain a procedure name followed by a list of
comma-separated arguments contained within parentheses followed by a
semi-colon. The execution of procedures typically causes side-effects to the
architectural state of the machine.
Procedures are generally used where it is difficult or inappropriate to specify the
effect of an instruction using the abstract execution model. A fuller description of
the effect of the instruction will be given in the surrounding text.
An example procedure with two parameters is:
proc(param1, param2);
Architectural state
Type is a bit-field
containing:
Description
PC
32 bits
PSW
32 bits
SAVED_PC
32 bits
SAVED_PSW
32 bits
SAVED_SAVED_PC
32 bits
SAVED_SAVED_PSW
32 bits
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Architectural state
RI where i is in [0, 63]
159
Type is a bit-field
containing:
32 bits
Description
64 x 32-bit general purpose registers
R0 reads as zero
Assignments to R0 are ignored
LR
32 bits
BI where I is in [0, 7]
1 bit
Architectural state
Description
32 bits
8 bits
Description
DataBreakPoint(address)
Misalignedn(address)
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Function
Description
NoTranslation(address)
MultiMapping(address)
Results is TRUE if the TLB has more than one mapping for
address, otherwise FALSE.
Translate(address)
SCUHit(paddress)
ReadAccessViolation(address)
WriteAccessViolation(address)
IsCRegSpace(address)
UndefinedCReg(address)
CRegIndex(address)
CRegReadAccessViolation(index)
CRegWriteAccessViolation(index)
BusReadError(paddress)
IsDBreakHit(address)
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Description
ReadCheckMemoryn(address)
ReadMemoryn(address)
DisReadCheckMemoryn(address)
DisReadMemoryn(address)
ReadMemResponse()
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The DisReadMemoryn performs the same functionality for a dismissible read from
memory. The procedure call:
DisReadMemoryn(a);
is equivalent to:
width n / 8;
IF (NOT Misalignedn(a) AND
NOT NoTranslation(a) AND
NOT ReadAccessViolation(a) {
pa = Translate(a);
IF (SCUHit(pa) {
IF (BusReadError(pa))
THROW BUS_DC_ERROR, a; // Non-recoverable
mem_response MEM[pa FOR width];
}
ELSE
mem_response 0;
}
ELSE
mem_response 0;
The function ReadMemResponse returns the data that will have been read from
memory. The assignment:
result ReadMemResponse();
is equivalent to:
result mem_response;
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Description
Prefetch memory if possible.
Table 80: Memory prefetch procedure
This is used for a software-directed data prefetch from a specified effective address.
This is a hint to give advance notice that particular data will be required.
PrefetchMemory, performs the implementation-specific prefetch when the address
is valid:
PrefetchMemory(a);
equivalent to:
IF (NOT NoTranslation(a) AND
NOT MultiMapping(a)
NOT ReadAccessViolation(a)) {
pa = Translate(a);
IF (SCUHit(pa))
Prefetch(a);
}
where Prefetch is a cache operation defined in Section 17.6.4: Cache model on
page 169. Prefetching memory will not generate any exceptions.
17.6.2.4 Writing memory
The following procedures are provided to write memory.
Function
Description
WriteCheckMemoryn(address)
WriteMemoryn(address, value)
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FOR n>;
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Description
ReadCheckCReg(address)
ReadCReg(address)
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Description
WriteCheckCReg(address)
WriteCReg(address, value)
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Description
PurgeIns( )
Sync( )
PurgeAddress(address)
PurgeSet(address)
Prefetch(address)
PurgeInsPg(address)
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Instruction
set
18.1 Introduction
31
stop bit
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reserved
operation
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Bundle encoding
Description
Imm(i)
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Operation specifications
Exceptions: if this operation is able to throw any exceptions, they will be listed
here. The semantics of the operation will detail how and when they are thrown.
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add Immediate
add RIDEST = RSRC1, ISRC2
0
SRC1
6
5
IDEST
12
11
ISRC2
21
20
00000
26
25
0010
31
30
29
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result operand1 + operand2;
RIDEST Register(result);
Description:
Add
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Example operations
The operation is given the subscript Immediate to indicate that one of its source
operands is an immediate rather than both being registers.
The next line of the description shows the assembly syntax of the operation.
Just below is the binary encoding table with fields showing:
The opcode: Bits 29:21.
The operands: An s in bit 31 represents the stop bit (Section 18.2).
-
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3 The final statement, executed if no exceptions have been thrown in the bundle,
updates the architectural state:
ridest <- Register(result);
The function Register (Section 17.3.6: Single-value functions on page 152)
converts the integer result back to a bit-field, discarding any redundant higher
bits. This value is then assigned to the RIDEST register.
After the semantic description is a simple textual description of the operation.
The section listing restrictions for this operation shows that it has no restrictions at
all. This means that up to four of these operations can be used in a bundle, and that
all operands will be ready for use by operations in the next bundle.
Finally, this operation can not generate any exceptions.
18.5 Macros
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
nop
s
00 0 0
add R0 = R0, R0
00000
movInt3R
s
00 0 0
00000
add RDEST = R0, RSRC2
movInt3I
s
00 1 0
00000
add RIDEST = R0, ISRC2
mtb
s
00 0 1 1
orl BBDEST = RSRC1, R0
mfb
s
01 1
001
SCOND
slctf RIDEST = BSCOND, R0, 1
zxtb
s
00 1 0
01001
and RIDEST = RSRC1, 255
syncins
s
10
pswset R0
idle
1
11
goto 0
001
000000
000000
DEST
SRC2
000000
IDEST
000000
000000
SRC1
000000001
IDEST
000000
011111111
IDEST
SRC1
ISRC2
000000
SRC1
ISRC2
1100
10010
000000
BDEST
00000000000000000000000
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30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
178
s
return
11
001
BTARG
goto LR
Figure 17: Macros
18.6 Operations
Each operation is now specified. They are listed alphabetically for ease of use. The
semantics of the operations are written using the notational language defined in
Chapter 17: Specification notation on page 145.
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add Register
add RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00000
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 + operand2;
RDEST Register(result1);
Description:
Add
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
add Immediate
add RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00000
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 + operand2;
RIDEST Register(result1);
Description:
Add
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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addcg
addcg RDEST, BBDEST = RSRC1, RSRC2, BSCOND
0
SRC1
6
11
SRC2
12
DEST
17
18
20
21
23
SCOND BDEST
24
0010
27
28
29
01
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
operand3 ZeroExtend1(BSCOND);
result1 (operand1 + operand2) + operand3;
result2 Bit(result1, 32);
RDEST Register(result1);
BBDEST Bit(result2);
Description:
Add with carry and generate carry
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
and Register
and RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01001
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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and Immediate
and RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01001
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
andc Register
andc RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01010
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (~operand1) operand2;
RDEST Register(result1);
Description:
Complement and bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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andc Immediate
andc RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01010
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (~operand1) operand2;
RIDEST Register(result1);
Description:
Complement and bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
SRC1
6
11
SRC2
12
17
18
20
DEST
21
1010
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 0) AND (operand2 0);
RDEST Register(result1);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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SRC1
6
11
12
SRC2
17
18
20
BDEST
21
1010
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 0) AND (operand2 0);
BBDEST Bit(result1);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
SRC1
6
11
IDEST
12
20
ISRC2
21
1010
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 0) AND (operand2 0);
RIDEST Register(result1);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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SRC1
5
11
IBDEST
12
20
ISRC2
21
1010
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 0) AND (operand2 0);
BIBDEST Bit(result1);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
br
br BBCOND, BTARG
0
BTARG
22
23
25
26
1 0 BCOND
27
28
29
11
30
31
Semantics:
operand1 ZeroExtend1(BBCOND);
operand2 SignExtend23(BTARG);
IF (operand1 0)
PC Register(ZeroExtend32(BUNDLE_PC) + (operand2 << 2));
Description:
Branch
Restrictions:
Must be the first syllable of a bundle.
There is a latency of 2 bundles between an operation writing BBCOND and this
operation being issued.
Exceptions:
None.
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break
break
0
20
21
1111111
27
28
29
01
30
31
Semantics:
THROW ILL_INST;
Description:
Break
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
ILL_INST
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Operations
brf
brf BBCOND, BTARG
0
BTARG
22
23
25
26
1 1 BCOND
27
28
29
11
30
31
Semantics:
operand1 ZeroExtend1(BBCOND);
operand2 SignExtend23(BTARG);
IF (operand1 = 0)
PC Register(ZeroExtend32(BUNDLE_PC) + (operand2 << 2));
Description:
Branch false
Restrictions:
Must be the first syllable of a bundle.
There is a latency of 2 bundles between an operation writing BBCOND and this
operation being issued.
Exceptions:
None.
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bswap
bswap RIDEST = RSRC1
0
SRC1
6
11
IDEST
12
20
000000010
21
01110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
byte0 operand1<0 FOR 8>;
byte1 operand1<8 FOR 8>;
byte2 operand1<16 FOR 8>;
byte3 operand1<24 FOR 8>;
result1 ((byte0 << 24) (byte1 << 16)) ((byte2 << 8) byte3);
RIDEST Register(result1);
Description:
Byte Swap
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
call Immediate
call LR = BTARG
0
BTARG
22
23
0
24
000
26
0
27
28
29
11
30
31
Semantics:
operand1 SignExtend23(BTARG);
NEXT_PC PC;
PC Register(ZeroExtend32(BUNDLE_PC) + (operand1 << 2));
LR NEXT_PC;
Description:
Jump and link
Restrictions:
Must be the first syllable of a bundle.
No latency constraints.
Exceptions:
None.
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00000000000000000000000
22
23
1
24
000
26
0
27
28
29
11
30
31
Semantics:
NEXT_PC PC;
PC Register(ZeroExtend32(LR));
LR NEXT_PC;
Description:
Jump (using Link Register) and link
Restrictions:
Must be the first syllable of a bundle.
There is a latency of 2 bundles between an operation writing LR and this
operation being issued. The only exception to this is a call, for which there are no
latency constraints.
Exceptions:
None.
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Operations
clz
clz RIDEST = RSRC1
0
SRC1
6
11
IDEST
12
20
000000100
21
01110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
result1 CountLeadingZeros(operand1);
RIDEST Register(result1);
Description:
Count leading zeros
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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SRC1
6
11
SRC2
12
17
18
20
DEST
21
0000
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 = operand2;
RDEST Register(result1);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0000
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 = operand2;
BBDEST Bit(result1);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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SRC1
6
11
IDEST
12
20
ISRC2
21
0000
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 = operand2;
RIDEST Register(result1);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0000
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 = operand2;
BIBDEST Bit(result1);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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SRC1
6
11
SRC2
12
17
18
20
DEST
21
0010
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
202
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0010
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
BBDEST Bit(result1);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
203
SRC1
6
11
IDEST
12
20
ISRC2
21
0010
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
204
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0010
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
BIBDEST Bit(result1);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
205
SRC1
6
11
SRC2
12
17
18
20
DEST
21
0011
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
206
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0011
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 operand2;
BBDEST Bit(result1);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
207
SRC1
6
11
IDEST
12
20
ISRC2
21
0011
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
208
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0011
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 operand2;
BIBDEST Bit(result1);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
209
SRC1
6
11
SRC2
12
17
18
20
DEST
21
0100
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 > operand2;
RDEST Register(result1);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
210
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0100
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 > operand2;
BBDEST Bit(result1);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
211
SRC1
6
11
IDEST
12
20
ISRC2
21
0100
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 > operand2;
RIDEST Register(result1);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
212
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0100
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 > operand2;
BIBDEST Bit(result1);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
213
SRC1
6
11
SRC2
12
17
18
20
DEST
21
0101
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 > operand2;
RDEST Register(result1);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
214
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0101
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 > operand2;
BBDEST Bit(result1);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
215
SRC1
6
11
IDEST
12
20
ISRC2
21
0101
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 > operand2;
RIDEST Register(result1);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
216
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0101
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 > operand2;
BIBDEST Bit(result1);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
217
SRC1
6
11
SRC2
12
17
18
20
DEST
21
0110
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
218
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0110
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
BBDEST Bit(result1);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
219
SRC1
6
11
IDEST
12
20
ISRC2
21
0110
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
220
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0110
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
BIBDEST Bit(result1);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
221
SRC1
6
11
SRC2
12
17
18
20
DEST
21
0111
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
222
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0111
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 operand2;
BBDEST Bit(result1);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
223
SRC1
6
11
IDEST
12
20
ISRC2
21
0111
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
224
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0111
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 operand2;
BIBDEST Bit(result1);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
225
SRC1
6
11
SRC2
12
17
18
20
DEST
21
1000
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 < operand2;
RDEST Register(result1);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
226
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
1000
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 < operand2;
BBDEST Bit(result1);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
227
SRC1
6
11
IDEST
12
20
ISRC2
21
1000
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 < operand2;
RIDEST Register(result1);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
228
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
1000
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 < operand2;
BIBDEST Bit(result1);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
229
SRC1
6
11
SRC2
12
17
18
20
DEST
21
1001
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 < operand2;
RDEST Register(result1);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
230
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
1001
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 operand1 < operand2;
BBDEST Bit(result1);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
231
SRC1
6
11
IDEST
12
20
ISRC2
21
1001
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 < operand2;
RIDEST Register(result1);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
232
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
1001
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 operand1 < operand2;
BIBDEST Bit(result1);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
233
SRC1
6
11
SRC2
12
17
18
20
DEST
21
0001
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
234
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
0001
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
BBDEST Bit(result1);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
235
SRC1
6
11
IDEST
12
20
ISRC2
21
0001
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
236
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
0001
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
BIBDEST Bit(result1);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
237
divs
divs RDEST, BBDEST = RSRC1, RSRC2, BSCOND
0
SRC1
6
11
SRC2
12
DEST
17
18
20
21
23
SCOND BDEST
24
0100
27
28
29
01
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
operand3 ZeroExtend1(BSCOND);
temp ZeroExtend32(operand1 2) (operand3 1);
IF (operand1 < 0)
{
result1 temp + operand2;
result2 1;
}
ELSE
{
result1 temp - operand2;
result2 0;
}
RDEST Register(result1);
BBDEST Bit(result2);
Description:
Non-restoring divide stage
Restrictions:
No address/bundle restrictions.
No latency constraints.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
238
Operations
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
239
goto Immediate
goto BTARG
0
BTARG
22
23
0
24
001
26
0
27
28
29
11
30
31
Semantics:
operand1 SignExtend23(BTARG);
PC Register(ZeroExtend32(BUNDLE_PC) + (operand1 << 2));
Description:
Jump
Restrictions:
Must be the first syllable of a bundle.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
240
Operations
00000000000000000000000
22
23
1
24
001
26
0
27
28
29
11
30
31
Semantics:
PC Register(ZeroExtend32(LR));
Description:
Jump (using Link Register)
Restrictions:
Must be the first syllable of a bundle.
There is a latency of 2 bundles between an operation writing LR and this
operation being issued. The only exception to this is a call, for which there are no
latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
241
imml
imml IMM
22
IMM
23
01010
27
28
29
01
30
31
Semantics:
extension ZeroExtend23(IMM);
Description:
Long immediate for previous syllable
Restrictions:
Must be encoded at even word addresses.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
242
Operations
immr
immr IMM
0
22
IMM
23
01011
27
28
29
01
30
31
Semantics:
extension ZeroExtend23(IMM);
Description:
Long immediate for next syllable
Restrictions:
Must be encoded at even word addresses.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
243
ldb
ldb RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
0
24
0011
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ELSE
ReadCheckMemory8(ea);
ReadMemory8(ea);
result1 SignExtend8(ReadMemResponse());
RIDEST Register(result1);
Description:
Signed load byte
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
DBREAK, CREG_ACCESS_VIOLATION, DTLB
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Operations
ldb.d
ldb.d RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
1
24
0011
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT (IsCRegSpace(ea)))
DisReadCheckMemory8(ea);
IF (NOT (IsCRegSpace(ea)))
DisReadMemory8(ea);
IF (IsCRegSpace(ea))
result1 0;
ELSE
result1 SignExtend8(ReadMemResponse());
RIDEST Register(result1);
Description:
Signed load byte dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
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Exceptions:
DBREAK, DTLB
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Operations
ldbu
ldbu RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
0
24
0100
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ELSE
ReadCheckMemory8(ea);
ReadMemory8(ea);
result1 ZeroExtend8(ReadMemResponse());
RIDEST Register(result1);
Description:
Unsigned load byte
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
DBREAK, CREG_ACCESS_VIOLATION, DTLB
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ldbu.d
ldbu.d RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
1
24
0100
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT (IsCRegSpace(ea)))
DisReadCheckMemory8(ea);
IF (NOT (IsCRegSpace(ea)))
DisReadMemory8(ea);
IF (IsCRegSpace(ea))
result1 0;
ELSE
result1 ZeroExtend8(ReadMemResponse());
RIDEST Register(result1);
Description:
Unsigned load byte dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
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Operations
Exceptions:
DBREAK, DTLB
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ldh
ldh RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
0
24
0001
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ELSE
ReadCheckMemory16(ea);
ReadMemory16(ea);
result1 SignExtend16(ReadMemResponse());
RIDEST Register(result1);
Description:
Signed load half-word
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
DBREAK, CREG_ACCESS_VIOLATION, DTLB, MISALIGNED_TRAP
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Operations
ldh.d
ldh.d RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
1
24
0001
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT (IsCRegSpace(ea)))
DisReadCheckMemory16(ea);
IF (NOT (IsCRegSpace(ea)))
DisReadMemory16(ea);
IF (IsCRegSpace(ea))
result1 0;
ELSE
result1 SignExtend16(ReadMemResponse());
RIDEST Register(result1);
Description:
Signed load half-word dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
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Exceptions:
DBREAK, DTLB, MISALIGNED_TRAP
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Operations
ldhu
ldhu RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
0
24
0010
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ELSE
ReadCheckMemory16(ea);
ReadMemory16(ea);
result1 ZeroExtend16(ReadMemResponse());
RIDEST Register(result1);
Description:
Unsigned load half-word
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
DBREAK, CREG_ACCESS_VIOLATION, DTLB, MISALIGNED_TRAP
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ldhu.d
ldhu.d RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
1
24
0010
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT (IsCRegSpace(ea)))
DisReadCheckMemory16(ea);
IF (NOT (IsCRegSpace(ea)))
DisReadMemory16(ea);
IF (IsCRegSpace(ea))
result1 0;
ELSE
result1 ZeroExtend16(ReadMemResponse());
RIDEST Register(result1);
Description:
Unsigned load half-word dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
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Operations
Exceptions:
DBREAK, DTLB, MISALIGNED_TRAP
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ldw
ldw RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
0
24
0000
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
ReadCheckCReg(ea);
ELSE
ReadCheckMemory32(ea);
IF (IsCRegSpace(ea))
ReadCReg(ea);
ELSE
ReadMemory32(ea);
result1 SignExtend32(ReadMemResponse());
RIDEST Register(result1);
Description:
Load word
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
If writing the LR, there is a latency of 3 bundles before a call LR or goto LR is
issued.
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Operations
Exceptions:
DBREAK, DTLB, MISALIGNED_TRAP, CREG_ACCESS_VIOLATION,
CREG_NO_MAPPING
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ldw.d
ldw.d RIDEST = ISRC2[RSRC1]
0
SRC1
6
11
IDEST
12
20
21
ISRC2
22
23
1
24
0000
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT (IsCRegSpace(ea)))
DisReadCheckMemory32(ea);
IF (NOT (IsCRegSpace(ea)))
DisReadMemory32(ea);
IF (IsCRegSpace(ea))
result1 0;
ELSE
result1 SignExtend32(ReadMemResponse());
RIDEST Register(result1);
Description:
Load word dismissable
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
There is a latency of 2 bundles before RIDEST is available for reading.
If writing the LR, there is a latency of 3 bundles before a call LR or goto LR is
issued.
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Operations
Exceptions:
DBREAK, DTLB, MISALIGNED_TRAP, CREG_ACCESS_VIOLATION,
CREG_NO_MAPPING
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max Register
max RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10000
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
IF (operand1 > operand2)
result1 operand1;
ELSE
result1 operand2;
RDEST Register(result1);
Description:
Signed maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
max Immediate
max RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10000
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
IF (operand1 > operand2)
result1 operand1;
ELSE
result1 operand2;
RIDEST Register(result1);
Description:
Signed maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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maxu Register
maxu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10001
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
IF (operand1 > operand2)
result1 operand1;
ELSE
result1 operand2;
RDEST Register(result1);
Description:
Unsigned maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
maxu Immediate
maxu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10001
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
IF (operand1 > operand2)
result1 operand1;
ELSE
result1 operand2;
RIDEST Register(result1);
Description:
Unsigned maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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min Register
min RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10010
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
IF (operand1 < operand2)
result1 operand1;
ELSE
result1 operand2;
RDEST Register(result1);
Description:
Signed minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
min Immediate
min RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10010
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
IF (operand1 < operand2)
result1 operand1;
ELSE
result1 operand2;
RIDEST Register(result1);
Description:
Signed minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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minu Register
minu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10011
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
IF (operand1 < operand2)
result1 operand1;
ELSE
result1 operand2;
RDEST Register(result1);
Description:
Unsigned minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
minu Immediate
minu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10011
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
IF (operand1 < operand2)
result1 operand1;
ELSE
result1 operand2;
RIDEST Register(result1);
Description:
Unsigned minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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mulh Register
mulh RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10111
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 (operand2 >> 16);
RDEST Register(result1);
Description:
Word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
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Operations
mulh Immediate
mulh RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10111
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 (operand2 >> 16);
RIDEST Register(result1);
Description:
Word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
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269
mulhh Register
mulhh RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11101
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 >> 16) (operand2 >> 16);
RDEST Register(result1);
Description:
Upper-half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
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Operations
mulhh Immediate
mulhh RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11101
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 >> 16) (operand2 >> 16);
RIDEST Register(result1);
Description:
Upper-half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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271
mulhhs Register
mulhhs RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10100
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 (operand2 >> 16)) >> 16;
RDEST Register(result1);
Description:
Word by upper-half-word signed multiply, returns top 32 bits of 48 bit result
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
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Operations
mulhhs Immediate
mulhhs RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10100
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 (operand2 >> 16)) >> 16;
RIDEST Register(result1);
Description:
Word by upper-half-word signed multiply, returns top 32 bits of 48 bit result
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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273
mulhhu Register
mulhhu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11110
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 ZeroExtend16(operand1 >> 16) ZeroExtend16(operand2 >> 16);
RDEST Register(result1);
Description:
Upper-half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
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Operations
mulhhu Immediate
mulhhu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 ZeroExtend16(operand1 >> 16) ZeroExtend16(operand2 >> 16);
RIDEST Register(result1);
Description:
Upper-half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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275
mulhs Register
mulhs RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11111
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 ZeroExtend16(operand2 >> 16)) << 16;
RDEST Register(result1);
Description:
Word by upper-half-word unsigned multiply, left shifted 16
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
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Operations
mulhs Immediate
mulhs RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11111
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 ZeroExtend16(operand2 >> 16)) << 16;
RIDEST Register(result1);
Description:
Word by upper-half-word unsigned multiply, left shifted 16
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
277
mulhu Register
mulhu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11000
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 ZeroExtend16(operand2 >> 16);
RDEST Register(result1);
Description:
Word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
278
Operations
mulhu Immediate
mulhu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11000
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 ZeroExtend16(operand2 >> 16);
RIDEST Register(result1);
Description:
Word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
279
mull Register
mull RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10101
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend16(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
280
Operations
mull Immediate
mull RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10101
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend16(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
281
mullh Register
mullh RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11011
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend16(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 (operand2 >> 16);
RDEST Register(result1);
Description:
Half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
282
Operations
mullh Immediate
mullh RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11011
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend16(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 (operand2 >> 16);
RIDEST Register(result1);
Description:
Half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
283
mullhu Register
mullhu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11100
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend16(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 ZeroExtend16(operand2 >> 16);
RDEST Register(result1);
Description:
Half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
284
Operations
mullhu Immediate
mullhu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11100
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend16(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 ZeroExtend16(operand2 >> 16);
RIDEST Register(result1);
Description:
Half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
285
mullhus Register
mullhus RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01111
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 ZeroExtend16(RSRC2);
result1 (operand1 operand2) >> 32;
RDEST Register(result1);
Description:
Word by lower-half-word signed multiply, returns top 16 bits of 48 bit result,
sign extended
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
286
Operations
mullhus Immediate
mullhus RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01111
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 ZeroExtend16(Imm(ISRC2));
result1 (operand1 operand2) >> 32;
RIDEST Register(result1);
Description:
Word by lower-half-word signed multiply, returns top 16 bits of 48 bit result,
sign extended
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
287
mulll Register
mulll RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11001
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend16(RSRC1);
operand2 SignExtend16(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Half-word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
288
Operations
mulll Immediate
mulll RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11001
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend16(RSRC1);
operand2 SignExtend16(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Half-word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
289
mulllu Register
mulllu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11010
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend16(RSRC1);
operand2 ZeroExtend16(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Half-word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
290
Operations
mulllu Immediate
mulllu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11010
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend16(RSRC1);
operand2 ZeroExtend16(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Half-word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
291
mullu Register
mullu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
10110
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend16(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
292
Operations
mullu Immediate
mullu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
10110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend16(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
293
mul32 Register
mul32 RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01110
25
26
0 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
32 by 32 multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
294
Operations
mul32 Immediate
mul32 RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01110
25
26
1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
32 by 32 multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
295
mul64h Register
mul64h RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01111
25
26
0 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 operand2) >> 32;
RDEST Register(result1);
Description:
32 by 32 signed multiply, return the top 32 bits of the 64 bit result.
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
296
Operations
mul64h Immediate
mul64h RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01111
25
26
1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 operand2) >> 32;
RIDEST Register(result1);
Description:
32 by 32 signed multiply, return the top 32 bits of the 64 bit result.
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
297
mul64hu Register
mul64hu RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11110
25
26
0 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(RSRC2);
result1 (operand1 operand2) >> 32;
RDEST Register(result1);
Description:
32 by 32 unsigned multiply, return the top 32 bits of the 64 bit result.
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
298
Operations
mul64hu Immediate
mul64hu RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11110
25
26
1 1
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend32(Imm(ISRC2));
result1 (operand1 operand2) >> 32;
RIDEST Register(result1);
Description:
32 by 32 unsigned multiply, return the top 32 bits of the 64 bit result.
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
299
mulfrac Register
mulfrac RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
11111
25
26
0 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
IF (((-operand1) = 0x80000000) AND ((-operand2) = 0x80000000))
{
result1 0x7FFFFFFF;
}
ELSE
{
result1 operand1 operand2;
result1 result1 + (1 << 30);
result1 result1 >> 31;
}
RDEST Register(result1);
Description:
fractional multiply.
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RDEST is available for reading.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
300
Operations
mulfrac Immediate
mulfrac RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
11111
25
26
1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
IF (((-operand1) = 0x80000000) AND ((-operand2) = 0x80000000))
{
result1 0x7FFFFFFF;
}
ELSE
{
result1 operand1 operand2;
result1 result1 + (1 << 30);
result1 result1 >> 31;
}
RIDEST Register(result1);
Description:
fractional multiply.
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
There is a latency of 2 bundles before RIDEST is available for reading.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
301
SRC1
6
11
SRC2
12
17
18
20
DEST
21
1011
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 NOT ((operand1 0) AND (operand2 0));
RDEST Register(result1);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
302
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
1011
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 NOT ((operand1 0) AND (operand2 0));
BBDEST Bit(result1);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
303
SRC1
6
11
IDEST
12
20
ISRC2
21
1011
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 NOT ((operand1 0) AND (operand2 0));
RIDEST Register(result1);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
304
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
1011
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 NOT ((operand1 0) AND (operand2 0));
BIBDEST Bit(result1);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
305
SRC1
6
11
SRC2
12
17
18
20
DEST
21
1101
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 NOT ((operand1 0) OR (operand2 0));
RDEST Register(result1);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
306
Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
1101
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 NOT ((operand1 0) OR (operand2 0));
BBDEST Bit(result1);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
307
SRC1
6
11
IDEST
12
20
ISRC2
21
1101
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 NOT ((operand1 0) OR (operand2 0));
RIDEST Register(result1);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
308
Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
1101
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 NOT ((operand1 0) OR (operand2 0));
BIBDEST Bit(result1);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
309
or Register
or RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01011
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
or Immediate
or RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01011
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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Operations
311
orc Register
orc RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01100
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (~operand1) operand2;
RDEST Register(result1);
Description:
Complement and bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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PRELIMINARY DATA
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Operations
orc Immediate
orc RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01100
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (~operand1) operand2;
RIDEST Register(result1);
Description:
Complement and bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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313
SRC1
6
11
SRC2
12
17
18
20
DEST
21
1100
24
25
26
0 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 0) OR (operand2 0);
RDEST Register(result1);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
SRC1
6
11
12
SRC2
17
18
20
BDEST
21
1100
24
25
26
0 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 0) OR (operand2 0);
BBDEST Bit(result1);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
315
SRC1
6
11
IDEST
12
20
ISRC2
21
1100
24
25
26
1 1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 0) OR (operand2 0);
RIDEST Register(result1);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
SRC1
5
11
IBDEST
12
20
ISRC2
21
1100
24
25
26
1 1 1
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 0) OR (operand2 0);
BIBDEST Bit(result1);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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Operations
317
pft
pft ISRC2[RSRC1]
0
SRC1
6
11
000000
12
20
21
22
ISRC2
23
01101
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
PrefetchMemory(ea);
Description:
Prefetch
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
None.
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Operations
prgadd
prgadd ISRC2[RSRC1]
0
SRC1
6
11
000000
12
20
21
22
ISRC2
23
01110
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
PurgeAddress(ea);
Description:
Purge the address given from the data cache
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
DTLB
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
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Operations
319
prgins
prgins
0
20
21
27
1111100
28
29
01
30
31
Semantics:
IF (PSW[USER_MODE])
THROW ILL_INST;
PurgeIns();
Description:
Purge the instruction cache
Restrictions:
Must be the only syllable in the bundle.
No latency constraints.
Exceptions:
ILL_INST
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
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Operations
prginspg
prginspg ISRC2[RSRC1]
0
SRC1
6
11
000000
12
20
21
22
ISRC2
23
10001
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
IF (PSW[USER_MODE])
THROW ILL_INST;
ea ZeroExtend32(operand1 + operand2);
PurgeInsPg(ea);
Description:
Purge a 8kb page from the instruction cache
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
ILL_INST
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
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Operations
321
prgset
prgset ISRC2[RSRC1]
0
SRC1
6
11
000000
12
20
21
22
ISRC2
23
01111
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
ea ZeroExtend32(operand1 + operand2);
PurgeSet(ea);
Description:
Purge a set of four cache lines from the data cache
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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Operations
pswset
pswset RSRC2
0
000000
6
11
SRC2
12
20
21
22
000000000
23
10010
27
28
29
10
30
31
Semantics:
operand3 SignExtend32(RSRC2);
IF (PSW[USER_MODE])
THROW ILL_INST;
PswSet(operand3);
Description:
Atomic psw set.
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
Must be the first syllable of a bundle.
No latency constraints.
Exceptions:
ILL_INST
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ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
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Operations
323
pswclr
pswclr RSRC2
0
000000
6
11
SRC2
12
20
21
22
000000000
23
10011
27
28
29
10
30
31
Semantics:
operand3 SignExtend32(RSRC2);
IF (PSW[USER_MODE])
THROW ILL_INST;
PswClr(operand3);
Description:
Atomic psw clear.
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
Must be the first syllable of a bundle.
No latency constraints.
Exceptions:
ILL_INST
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Operations
rfi
rfi
0
00000000000000000000000
22
23
0
24
010
26
0
27
28
29
11
30
31
Semantics:
IF (PSW[USER_MODE])
THROW ILL_INST;
PC Register(ZeroExtend32(SAVED_PC));
PSW SAVED_PSW;
SAVED_PC SAVED_SAVED_PC;
SAVED_PSW SAVED_SAVED_PSW;
Description:
Return from interrupt
Restrictions:
Must be the first syllable of a bundle.
Uses the load/store unit, for which only one operation is allowed per bundle.
Instructions writing SAVED_PC must be followed by 4 bundles before this
instruction can be issued.
Instructions writing SAVED_PSW must be followed by 4 bundles before this
instruction can be issued.
Instructions writing SAVED_SAVED_PC must be followed by 4 bundles before
this instruction can be issued.
Instructions writing SAVED_SAVED_PSW must be followed by 4 bundles before
this instruction can be issued.
Instructions writing PSW must be followed by 4 bundles before this instruction
can be issued.
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ST231 Core and Instruction Set Architecture Manual
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Operations
325
Exceptions:
ILL_INST
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Operations
sbrk
sbrk
0
20
1111101
27
28
29
01
30
31
Semantics:
THROW SBREAK;
Description:
Software breakpoint
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
SBREAK
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ST231 Core and Instruction Set Architecture Manual
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Operations
327
sh1add Register
sh1add RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00101
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 << 1) + operand2;
RDEST Register(result1);
Description:
Shift left one and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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Operations
sh1add Immediate
sh1add RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00101
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 << 1) + operand2;
RIDEST Register(result1);
Description:
Shift left one and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
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Operations
329
sh2add Register
sh2add RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00110
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 << 2) + operand2;
RDEST Register(result1);
Description:
Shift left two and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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PRELIMINARY DATA
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Operations
sh2add Immediate
sh2add RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 << 2) + operand2;
RIDEST Register(result1);
Description:
Shift left two and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
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Operations
331
sh3add Register
sh3add RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00111
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 << 3) + operand2;
RDEST Register(result1);
Description:
Shift left three and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
332
Operations
sh3add Immediate
sh3add RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00111
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 << 3) + operand2;
RIDEST Register(result1);
Description:
Shift left three and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
333
sh4add Register
sh4add RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01000
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 (operand1 << 4) + operand2;
RDEST Register(result1);
Description:
Shift left four and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
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Operations
sh4add Immediate
sh4add RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01000
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 (operand1 << 4) + operand2;
RIDEST Register(result1);
Description:
Shift left four and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
335
shl Register
shl RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00010
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 ZeroExtend8(RSRC2);
IF (operand2 > 31)
result1 0;
ELSE
result1 operand1 << operand2;
RDEST Register(result1);
Description:
Shift left
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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PRELIMINARY DATA
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Operations
shl Immediate
shl RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00010
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 ZeroExtend8(Imm(ISRC2));
IF (operand2 > 31)
result1 0;
ELSE
result1 operand1 << operand2;
RIDEST Register(result1);
Description:
Shift left
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
337
shr Register
shr RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00011
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 ZeroExtend8(RSRC2);
result1 operand1 >> operand2;
RDEST Register(result1);
Description:
Arithmetic shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
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Operations
shr Immediate
shr RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00011
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 ZeroExtend8(Imm(ISRC2));
result1 operand1 >> operand2;
RIDEST Register(result1);
Description:
Arithmetic shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
339
shru Register
shru RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00100
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend8(RSRC2);
result1 operand1 >> operand2;
RDEST Register(result1);
Description:
Logical shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
340
Operations
shru Immediate
shru RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00100
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend32(RSRC1);
operand2 ZeroExtend8(Imm(ISRC2));
result1 operand1 >> operand2;
RIDEST Register(result1);
Description:
Logical shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
341
slct Register
slct RDEST = BSCOND, RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
DEST
20
21
23
SCOND
24
000
26
0
27
28
29
01
30
31
Semantics:
operand1 ZeroExtend1(BSCOND);
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(RSRC2);
IF (operand1 0)
result1 operand2;
ELSE
result1 operand3;
RDEST Register(result1);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
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Operations
slct Immediate
slct RIDEST = BSCOND, RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
ISRC2
20
21
23
SCOND
24
000
26
1
27
28
29
01
30
31
Semantics:
operand1 ZeroExtend1(BSCOND);
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(Imm(ISRC2));
IF (operand1 0)
result1 operand2;
ELSE
result1 operand3;
RIDEST Register(result1);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
343
slctf Register
slctf RDEST = BSCOND, RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
DEST
20
21
23
SCOND
24
001
26
0
27
28
29
01
30
31
Semantics:
operand1 ZeroExtend1(BSCOND);
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(RSRC2);
IF (operand1 = 0)
result1 operand2;
ELSE
result1 operand3;
RDEST Register(result1);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
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Operations
slctf Immediate
slctf RIDEST = BSCOND, RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
ISRC2
20
21
23
SCOND
24
001
26
1
27
28
29
01
30
31
Semantics:
operand1 ZeroExtend1(BSCOND);
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(Imm(ISRC2));
IF (operand1 = 0)
result1 operand2;
ELSE
result1 operand3;
RIDEST Register(result1);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
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Operations
345
stb
stb ISRC2[RSRC1] = RSRC2
0
SRC1
6
11
SRC2
12
20
21
22
ISRC2
23
01100
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(RSRC2);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
WriteCheckMemory8(ea);
WriteMemory8(ea, operand3);
Description:
Store byte
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
DBREAK, CREG_ACCESS_VIOLATION, DTLB
ADCS 7645929A
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
346
Operations
sth
sth ISRC2[RSRC1] = RSRC2
0
SRC1
6
11
SRC2
12
20
21
22
ISRC2
23
01011
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(RSRC2);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
WriteCheckMemory16(ea);
WriteMemory16(ea, operand3);
Description:
Store half-word
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
DBREAK, CREG_ACCESS_VIOLATION, DTLB, MISALIGNED_TRAP
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ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
347
stw
stw ISRC2[RSRC1] = RSRC2
0
SRC1
6
11
SRC2
12
20
21
22
ISRC2
23
01010
27
28
29
10
30
31
Semantics:
operand1 SignExtend32(Imm(ISRC2));
operand2 SignExtend32(RSRC1);
operand3 SignExtend32(RSRC2);
ea ZeroExtend32(operand1 + operand2);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
WriteCheckCReg(ea);
WriteCheckMemory32(ea);
IF (IsCRegSpace(ea))
WriteCReg(ea, operand3);
ELSE
WriteMemory32(ea, operand3);
Description:
Store word
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
DBREAK, DTLB, MISALIGNED_TRAP, CREG_ACCESS_VIOLATION,
CREG_NO_MAPPING
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348
Operations
sub Register
sub RDEST = RSRC2, RSRC1
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
00001
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand2 - operand1;
RDEST Register(result1);
Description:
Subtract
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
349
sub Immediate
sub RIDEST = ISRC2, RSRC1
0
SRC1
6
11
IDEST
12
20
ISRC2
21
00001
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand2 - operand1;
RIDEST Register(result1);
Description:
Subtract
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
350
Operations
sxtb
sxtb RIDEST = RSRC1
0
SRC1
6
11
IDEST
12
20
000000000
21
01110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend8(RSRC1);
result1 operand1;
RIDEST Register(result1);
Description:
Sign extend byte
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
351
sxth
sxth RIDEST = RSRC1
0
SRC1
6
11
IDEST
12
20
000000001
21
01110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend16(RSRC1);
result1 operand1;
RIDEST Register(result1);
Description:
Sign extend half
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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PRELIMINARY DATA
352
Operations
sync
sync
0
000000
6
11
000000
12
20
21
22
000000000
23
10000
27
28
29
10
30
31
Semantics:
Sync();
Description:
Ensure synchronisation
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
353
syscall
syscall
20
1111110
27
28
29
01
30
31
Semantics:
THROW SYSCALL;
Description:
System call
Restrictions:
Must be the only syllable in the bundle.
No latency constraints.
Exceptions:
SYSCALL
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PRELIMINARY DATA
354
Operations
xor Register
xor RDEST = RSRC1, RSRC2
0
SRC1
6
11
SRC2
12
17
18
20
DEST
21
01101
25
26
0 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(RSRC2);
result1 operand1 operand2;
RDEST Register(result1);
Description:
Bitwise exclusive-or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Operations
355
xor Immediate
xor RIDEST = RSRC1, ISRC2
0
SRC1
6
11
IDEST
12
20
ISRC2
21
01101
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 SignExtend32(RSRC1);
operand2 SignExtend32(Imm(ISRC2));
result1 operand1 operand2;
RIDEST Register(result1);
Description:
Bitwise exclusive-or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
ADCS 7645929A
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
356
Operations
zxth
zxth RIDEST = RSRC1
0
SRC1
6
11
IDEST
12
20
000000011
21
01110
25
26
1 0
27
28
29
00
30
31
Semantics:
operand1 ZeroExtend16(RSRC1);
result1 operand1;
RIDEST Register(result1);
Description:
Zero extend half
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Instruction
encoding
A.1 Reserved bits
Any bits that are not defined are reserved. These bits must be set to 0.
A.2 Fields
Each instruction encoding is composed of a number of fields representing the
operands. These are detailed in the following table.
Field name
Offset
BCOND
BDEST
BTARG
DEST
IBDEST
IDEST
ISRC2
IMM
SCOND
SRC1
SRC2
23
18
0
12
6
6
12
0
21
0
6
Size
3
3
23
6
3
6
9
23
3
6
6
Field represents
Branch register containing the branch condition.
Destination branch register for register format operations.
Branch offset value from PC.
Destination general purpose register for register format operations.
Destination branch register for immediate format operations.
Destination general purpose register for immediate format operations.
9-bit short immediate value.
23-bit value used to extend a short immediate.
Source branch register used for select condition or carry.
General purpose source register.
General purpose source register.
Figure 18: Operand fields
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
358
Src1
Dest/Src2
Dest/Src2
Dest
Immediate/
Opcode
Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Stop bit
A.3 Formats
Int3R
Int3I
Monadic
Cmp3R_Reg
Cmp3R_Br
Cmp3I_Reg
Cmp3I_Br
Imm
SelectR
SelectI
cgen
SysOp
SBreak
Load
Store
Call
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
00
00
00
00
00
00
00
01
01
01
01
01
01
10
10
11
0
1
1
0
0
1
1
Branch
11
Mul64R
Mul64I
Asm
s
s
s
00
00
10
0
1
1
0
1
0
0
0
1
1
1
1
OPC
OPC
01110
OPC
OPC
OPC
OPC
0
1
BDEST
0
1
OPC
OPC SCOND
OPC SCOND
OPC
SCOND BDEST
OPC
OPC
OPC
D
OPC
OPC L
N
K
O BCOND
P
C
1
OPC
1
OPC
1
OPC
DEST
ISRC2
OPC
DEST
ISRC2
ISRC2
SRC2
IDEST
IDEST
SRC2
SRC2
IDEST
IBDEST
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC2
IDEST
SRC2
SRC1
SRC1
SRC1
IMM
DEST
ISRC2
DEST
ISRC2
ISRC2
SRC1
SRC1
BTARG
DEST
SRC2
ISRC2
IDEST
Reserved for software use
SRC1
SRC1
Important points:
The stop bit indicates the end of bundle and is set in the last syllable of the
bundle.
The format bits are used to decode the class of operation. There are four formats:
Integer
arithmetic, comparison
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ST231 Core and Instruction Set Architecture Manual
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PRELIMINARY DATA
359
Specific
Memory
load, store
A.4 Opcodes
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
* These operations are not supported by the hardware, but the opcodes are reserved
for software investigations.
add
sub
shl
shr
shru
sh1add
sh2add
sh3add
sh4add
and
s
s
s
s
s
s
s
s
s
s
00
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
360
andc
or
orc
xor
mullhus
max
maxu
min
minu
mulhhs
mull
mullu
mulh
mulhu
mulll
mulllu
mullh
mullhu
mulhh
mulhhu
mulhs
cmpeq
cmpne
cmpge
cmpgeu
cmpgt
cmpgtu
cmple
cmpleu
cmplt
cmpltu
andl
nandl
orl
norl
mul32
mul64h
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
01010
01011
01100
01101
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
01110
01111
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
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ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
361
cmpeq
cmpne
cmpge
cmpgeu
cmpgt
cmpgtu
cmple
cmpleu
cmplt
cmpltu
andl
nandl
orl
norl
mul64hu
mulfrac
add
sub
shl
shr
shru
sh1add
sh2add
sh3add
sh4add
and
andc
or
orc
xor
sxtb
sxth
bswap
zxth
clz
mullhus
max
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01110
01110
01110
01110
01111
10000
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
DEST
DEST
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
000000000
000000001
000000010
000000011
000000100
ISRC2
ISRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
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ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
362
maxu
min
minu
mulhhs
mull
mullu
mulh
mulhu
mulll
mulllu
mullh
mullhu
mulhh
mulhhu
mulhs
cmpeq
cmpne
cmpge
cmpgeu
cmpgt
cmpgtu
cmple
cmpleu
cmplt
cmpltu
andl
nandl
orl
norl
mul32
mul64h
cmpeq
cmpne
cmpge
cmpgeu
cmpgt
cmpgtu
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
01110
01111
0000
0001
0010
0011
0100
0101
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
363
cmple
cmpleu
cmplt
cmpltu
andl
nandl
orl
norl
mul64hu
mulfrac
slct
slctf
addcg
divs
imml
immr
slct
slctf
prgins
sbrk
syscall
break
ldw
ldw.d
ldh
ldh.d
ldhu
ldhu.d
ldb
ldb.d
ldbu
ldbu.d
stw
sth
stb
pft
prgadd
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
1
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
00
00
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0110
0111
1000
1001
1010
1011
1100
1101
11110
11111
000
SCOND
001
SCOND
0010
SCOND BDEST
0100
SCOND BDEST
01010
01011
1
000
SCOND
1
001
SCOND
1111100
1111101
1111110
1111111
0000
0
0000
1
0001
0
0001
1
0010
0
0010
1
0011
0
0011
1
0100
0
0100
1
01010
01011
01100
01101
01110
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
ISRC2
DEST
DEST
DEST
DEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IDEST
IDEST
SRC2
SRC2
SRC2
SRC2
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
IDEST
IDEST
SRC1
SRC1
IMM
IMM
ISRC2
ISRC2
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
SRC2
SRC2
SRC2
000000
000000
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
364
prgset
sync
prginspg
pswset
pswclr
call
icall
goto
igoto
rfi
br
brf
s
s
s
s
s
s
s
s
s
s
s
s
10
10
10
10
10
11
11
11
11
11
11
11
0
0
0
0
0
1
1
01111
10000
10001
10010
10011
000
0
000
1
001
0
001
1
010
0
0 BCOND
1 BCOND
ISRC2
000000000
ISRC2
000000000
000000000
000000
000000
000000
SRC2
SRC2
SRC1
000000
SRC1
000000
000000
BTARG
00000000000000000000000
BTARG
00000000000000000000000
00000000000000000000000
BTARG
BTARG
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Glossary
Branch registers The set of eight 1-bit registers that encode the condition for
conditional branches and carry bits.
Bundle
Operation
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
366
Predication
Speculative
Superscalar
Syllable
VLIW
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
Index
A
add 18
address space 30
AND 152
architecture 366
Arrays 147
ASID 29
B
B 159
Bit-fields 147
Boolean 147
Boolean operators 152
br 10
branch 26, 366
breakpoint registers 77
brf 10
bundle 365-366
Bundle decode 142
bus errors 21
bypassing 17
C
cache 30, 365
call 10, 13, 19, 26
ADCS 7645929A
carry 365
CMC 63
Commit point 139, 173
compiler 365
compression 366
conditional 365
conditional branch 10
CONTROL 73
control registers 78
Control transfer 359
Core 105
core memory controller 49, 63
COUNT 73
CR 159
CREG_ACCESS_VIOLATION 77-78
CREG_NO_MAPPING 77-78
D
DATA 73
Data cache 33-34, 54
DBREAK_CONTROL 108
DBREAK_LOWER 107
DBREAK_UPPER 107
debug interrupt 11
Debug ROM 105
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
368
DEBUG_ENABLE 113
DEBUG_INTERRUPT 109
DEBUG_INTERRUPT_TAKEN 109
DEBUG_MODE 107
decode 140
dismissible 366
dismissible loads 10, 27, 77
dispersal 366
DSR0 111
DSR1 4, 111
DSR2 112
DSU 105, 109
DSU_CALL_OR_RETURN 105, 114
DSU_FLUSH 105, 114
DSU_PEEK 105, 114
DSU_POKE 105, 114
DSU_VERSION 4
DTLB 29-30, 34, 57
DYNAMIC 57
E
ELSE 156
encoding 173
event 105, 117, 119, 121
EXADDRESS 23
EXCAUSE 24
EXCAUSENO 24, 73
ExceptAddress 23
exception 11, 21-22, 27, 366
exception registers 77
execute 140
execution pipeline 17
expressions 145, 148
extended immediates 172
EXTERN_INT 21, 24
external interrupt 11
F
fetch 140
Fields 357
flush 53
FOR 150-151, 154, 157, 161, 163-164, 166
FROM 157
Function
Bit(i) 154
BusReadError(address) 160
Commit(n) 142
ControlRegister(address) 160
CregReadAccessViolation(index) 160
CregWriteAccessViolation(index) 160
DataBreakPoint(address) 159
DisReadCheckMemory(address) 162
DisReadMemory(address) 162
DPUNoTranslation(address) 160
Imm(i) 172
InitiateDebugIntHandler() 143
InitiateExceptionHandler() 143
IsControlSpace(address) 160
IsDBreakHit(address) 160
Misaligned(address) 159
NumExtImms(address) 142
NumWords(address) 142
Pre-commit(n) 142
Prefetch(address) 169
PrefetchMemory(address) 165
PurgeAddress(address) 169
PurgeIns( ) 169
PurgeSet(address) 169
ReadAccessViolation(address) 160
ReadCheckControl(address) 167
ReadCheckMemory(address) 162
ReadControl(address) 167
ReadMemory(address) 162
Register(i) 154
SignExtend(i) 153
Sync( ) 169
UndefinedControlRegister(address) 160
WriteAccessViolation(address) 160
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
369
WriteCheckControl(address) 168
WriteCheckMemory(address) 165
WriteControl(address, value) 168
WriteMemory(address, value) 165
ZeroExtend(i) 153
G
goto 10-11, 19, 359
H
HANDLER_PC 22
HighestPriority 23
Host debug interface 105, 117
host target interface 117
HTI 105, 117
I
IBREAK_CONTROL 108
IBREAK_LOWER 107
IBREAK_UPPER 107
icall 19
idle 3, 11
IF 156, 163-164
igoto 19
illegal bundle 26
illegal instruction exception 26
Imm 172
Immediate 172-173
immediate 366
imml 172
immr 172
instruction 365
instruction buffer 51
instruction cache 31-32, 51
INT 152
Int3I 359
Int3R 359
ADCS 7645929A
INTCLR 101
INTCLR0 101
INTCLR1 101
integer 1, 358
Integer arithmetic operators 148
Integer bitwise operators 150
Integer shift operators 149
integer variable 146
interrupt 21
Interrupt clear register 101
interrupt controller 95
Interrupt mask clear register 98
Interrupt mask register 97
Interrupt mask set register 98
Interrupt pending register 96
Interrupt set register 101
Interrupt test register 100
interrupts 24
INTMASK 97
INTMASK0 97
INTMASK1 98
INTMASKCLR 98
INTMASKCLR0 98
INTMASKCLR1 99
INTMASKSET 98
INTMASKSET0 99
INTMASKSET1 99
INTPENDING 96
INTPENDING0 97
INTPENDING1 97
INTSET 101
INTSET0 102
INTSET1 102
INTTEST 100
INTTEST0 100
INTTEST1 100
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
370
ITLB 29-30, 32
L
ldb 26
ldh 26
ldw 26
legal bundle 26
LFSR 40
LIMIT 40
Link register 13
Load 8, 58-59, 359
load 5, 9-10, 18-19, 26-27, 47, 52, 54-55, 69,
77, 89, 173, 359, 366
load store unit 7-8, 53, 69
load/store 17
loads 55, 57, 68
long immediates 173
LR 159
M
machine state register 83
MEM 159, 161, 163-164, 166
memory 359
mov 19
mul 26
mullhu 40
multiply 18-19
multiply operations 173
multiply units 7
N
NO_MAPPING 57
nops 56
NOT 152
P
parallel 365
PARTITION 37
PC 13, 158
peek 105, 117-118
peeked 105, 117
PERIPHERAL_BASE 90
pft 55-56, 64
physical addresses 30
PM_CNTi 125
PM_CR 11, 124
poke 105, 117-118
POLICY 36
prefetch 53, 108
prgadd 26, 64
prgins 26, 64
prginspg 3, 26, 64
prgset 26, 64
Program counter 13
PROT_SUPER 37
PROT_USER 37
PROT_VIOLATION 54
PSW 3, 15, 27, 34, 57, 77, 107, 158
psw 14
pswclr 3, 26
pswset 3, 26
purge 108
R
O
R 159
Opcodes 359
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
371
R63 13
READY 73
Register 173
register 365-366
Relational operators 151
REPEAT 157
REPLACE 40
RESETACK 73-74
RESETREQUEST 73-74
RESTACK 73
return 13
return from interrupt 23
rfi 15, 19, 23, 26
S
SAVED_PC 15, 158
SAVED_PSW 15, 158
SAVED_SAVED_PC 158
SAVED_SAVED_PSW 158
sbrk 3, 26
SCU 27
SCU_BASEx 48
SCU_LIMITx 48
SDI 67, 69
SDI interface 68
SDI ports 68
SDI_CONTROL_PRIV 72
SDIi_CONTROL 70-71
SDIi_COUNT 70-72
SDIi_DATA 69, 71-72
SDIi_READY 69, 71
SDIi_TIMEOUT 70-72
select 366
semantics 173
single-value functions 152
SIZE 36
ADCS 7645929A
SLR 19
specific 359
SPECLOAD_MALIGNTRAP_EN 27
speculation 366
speculative loads 54
statements 145, 154
STATUS 85
stb 26
STBus 55, 68, 77, 110, 113
STBUS_DC_ERROR 57
STBUS_IC_ERROR 53
STEP 157
sth 26
stop bit 142, 171
store 5, 26, 52, 68-69, 77, 89, 98, 101, 108,
173
stw 26
subtract 18
supervisor 1, 3, 15, 71
syllable 365-366
sync 26, 64
syncins 3, 64
syscall 3, 26
T
THROW 23, 157, 163-164
TIMECONSTi 86
TIMECONTROLi 87
TIMECOUNTi 86
TIMEDIVIDE 86
TIMEOUT 73
TLB 3, 8, 29-30, 34, 77
TLB configuration 30
TLB sizes 30
TLB_ASID 41
TLB_CONTROL 41
TLB_ENABLE 34
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
372
TLB_ENTRY0 35
TLB_ENTRY1 38
TLB_ENTRY2 38
TLB_ENTRY3 39
TLB_INDEX 34
TLB_NO_MAPPING 55
TLB_REPLACE 39
trap handler 22
trap point 21
traps 21
types 146
usage restrictions 17
user 1, 15, 71
USER_MODE 15
UTLB 29-30, 55
XYZ
UNDEFINED 154-155
XOR 152
V
value 23
variables 146
VERSION 4, 84
virtual addresses 30
VLIW 1
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A
PRELIMINARY DATA
373
ADCS 7645929A
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
PRELIMINARY DATA
374
STMicroelectronics
ST231 Core and Instruction Set Architecture Manual
ADCS 7645929A