USN 06EC4s

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Fourth Semester B.E. Degree Examination, Dec.09-Jan.10
Fundamlntals of HDL
Time: 3 hrs' M ax. Mar k s :100
Note: Answer any FrvEfull questions, s;electing
q,
.e at least TWO questions'from eachpian.
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_o-
o PART - A
tr -
al,
o I a. Explainthe structureof VHDL moduleandVerilog module. (05Marks)
. ro =
b. GivenA: 1000andB 0011,performthefollowingotrierations:
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ut g)
o .l:
i) AXr{oRB
ii) Shift B t'wopositionleft logical
He iii) ReductionNAND
EE
=tF iv) Verilogconcatenation
{A, B}
.EO
,'i Veriloi ,ooiutu,A%8, (oslvrarks)
'C+F s c. Explain the Verilog datatypes.
QCD d. List thetypesof descriptions.Write VHDLcodeto describe
onebit tull adder
OF
stylq description. "rffiXf]
(06Marks)
=g
;= 2 a. Whatarethe factsof dataflow description? Explainwith anexamplethe executionof signal
9,9
EO assignment statement in HDL. (06Marks)
ME
Y6
()o,
b. Derivea minimizedBooleanfunctionof the systemthat hasthree I bit input 'a' and I bit
o u tp u t'b '.T h eo u tp u t'b 'i s' 1' when input' a'is 1,3, 6,7,other wise
' bi is' o' , w r i te a
s€
Eb
datdflowciescription in VHDL. Whatis thefunctionof this system? (04Marks)
c. Write the block diagram of a 4 bit ripple carry adder and its Boolean functions, Write a
vo
=6
g_: dataflow description in verilog. Assume 3 ns propagation delay for all two input gates.Draw
3(s thesimulationwaveform. (10Marks)
3d
b9
a_
Etu
;i o.
3 a. Explainthe execution of processstatement. (02Marks)
Fo-
b. Distinguishbetween:
,. 5q
( i) VHDL IF andVHDL case iD VHDL Next andExit
e.E iii) verilog repeatandverilog forever
g6 iv) Always andinitial. (08Marks)
.
ae
oc
c. UsingBooth algorithm,find the productof two 4 bit numbers-3 and 8. Write a Verilogcode
LO usingbehaviora!styleof description. (10Marks)
o'-
>E
Po r 4 a. Explainhow bindingis achievedin VHDL between:
'j5 .=
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o.c' i) Entity and component ii) Libraryandmodule (04Marks)
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b. Write a VHDL structuraldescriptionof a full adderusingtwo half addei and ap OR gate.
o< Writethe simulationwaveform. (08Marks)
a- Crl
c. Write a Verilog structuraldescriptionof a N : 3 bit magnitudecomparatorusinggenerate
irt statement. (08Marks)
'o
z.
PART - B
E
o
o
o
5 a. What are the significanceof procedure,tasks and functions?Differentiate between
procedute/task
andfunction. (04Marks)
"b'
Writea codeto converttheunsignedintegerto CN: 4) binaryusingprocedure. iot *".nri
c' Writea VHDL codefor finding the wordwith the lowestASCIIvalueusing file operations.
(08Marks)

I of2
 068C45

6a. of singledimensionalandtwo dimensionalarraysin'Vt{DL. .

Explainthe implementation
. - : --
b. Write a block diagramand functi'ontableof 128 x 16 staticmemory.\Mritea Verilog
code.
V"tfr G""de bl;;;1"ti";;;".f"*t by writing dglain memorylocations8; 18, 46,126
of lwo mem.orllocatlonsl8 and4f,,
andreadthe contents_ - :
c. Explainthe fetchandexebutecyclesof basiccomputer'forthe following operatiorls
' (oSMarks)
Halt, Add, Mult, NAND.

7a. Write mixed-languagedescription of a mastqr slave D nopinvok''* " Y*JIH

from a Verilog module.
b. Write a mixedJanguagedescriptionof an AND gate invoking a venlogt"%frlT*l
VHDL module. '
descriptions? (04Marks)
c. What arethe limitations of mrxed-language ' ' '
,
Whatis synthesis? List the generalstepsinvolvedin synthesis. (08Marks)
8a.
b. Give synthesis
- informationextracted,whenthe input andoutputare definedas: ,
i) bit ii) Std* logic - vector. (04 Marks)
:
rirrit. a behavioralcode in Vrrpr and Verilog for the signal assignmentstatementY X.
(08 Marks)
,.,, Explainthe mappingto gatelevel logic diagrarn.

**d.*:f

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 06EC45

Fundamentals of HDL
Time: 3 hrs. Max' Marks:loo

Note: 7. Answer any FIVE full questions selecting at least TIVO from eachpaft.

PART _A
1 a. Write the result of all shift and rotate operationsin VHDL after applyrngthern to aT bi t
vectorA : 1001010. (06 Marks)
b. ExplaincompositeandAccessdatatypeswith anexamplefor each. (08Marks)
c. Mention different styles (types) of descriptions. Explain mixed type and mixed language
descriptions. (06Marks)
2 a. How do you assign delay to a signal assignmentstatement?Explain with an example in
VHDL and verilog (04Marks)
b. What is a vector? Give an examplefor VHDL and verilog vector data types. (04Marks)
c. With ttre help of a truth table and K-maps write Boolean expression for a 2-bit magnitude
comparator.Write YHDL / verilog code (12 Marks)
3 a. Write VHDL code,f,or a D-latch using variable assignmentand signal assignment
With simulationwaveformsclearlydistinguishbetweenthe2 statements.
statsments.
(10Marks)
b. Explainvailog RepeatandForeverstaternents with anexample. (04Marks)
s. Write verilog codefor a 4-bit with
counter synchronoushold. (06Marks)
4 a. What is binding? Discussbinding betweentwo modulesin verilog. (06Marks)
b. Write -{HDL behaviorat description of a tristate buffer. Use this as a component for
structuraldescription of a 2to 4 decoderwith histate oufput. (10Marks)
c. Explain the use of GeneriC(in VHEL) and parameter (in verilog) with an example.
(04 Marks)
'
5a. Write verilog codeto converta signedbinary to lntegerusingtask. (08 Marks)
b . Write VHDL / verilog function to find greaterof 2 signednumbers. (04 Marks)
c. Table Q.5(c)below showsa file containingreal numbers.Write a VHDL codefor reading
the file, multiply the first numberby 2, secondby 5, third by 3 andfourthby 4. Theproducts
t
tobestored z,zl,z2 andz3fpfctilelq.
in realvariables (08 Marks)
-t3.4 '5.564 0.23
.55.32
TableQ.5(c)Filefile real. txt
6a. Write a noteon packages in VHDL (05Marks)
usinga package.
b . W:ite VHDL codefor additionof two 5 x 5:rnatrices (07Marks)
c. Write the block diagram and function table of a SRAM. Using these,write a verilog
descriptionfor 16x 8 SRAM. (08Marks)
7a. How to invoke a verilog module from a VHDL module?Explain with an exampleof a
mixedlanguagedescriptionfor a fuIl adderusing2 half adders. (10Marks)
b. Write a mixed languagedescriptionof a 9-bit adderconsistingof three 3-bit carry-look
aheadaddersto showhow a verilogmoduleinvokesVHDL entity. , (10l\rarks)
8a. Explainextractionof synthesisinformationfrom Entity. (04Marks)
b. With an exampleexplainverilog synthesisinformationextractionfrom moduleinputsand
outputs. (04lVlarks)
c. Write VHDL /, verilog code for signal assignmentstatementY : (2* x -t-3) for an entity
with one input X of 2-bits and one output Y of 4-bits. Show mappingof this signal
assignment to gatelevel.
* * * * d.
________-
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06EC45
AN
Fourth Semester B.E. Degree.Examination, Dec 08 / Jan 09
Fundamentals of HDL
Time: 3 hrs.
Note : Answer FIVE full questions, selectingatleast TWO
questionsfrom eachpart.
PART - A
:tlpes of HDL descriptions.
Explaindataflowandbehavioraldescriptions.
(07 Marl{s)
usedin HDLS.
b. Discussdifferentlogical operators (0EMarks)
c. CompareVHDL andVerilog. (05 Marks)

2 a, Explainsignaldeclarationandsignalassignment with relevantexamples.

statelnents
' (06 Marks)
b. Write a data- flow description(in both VHDL and Verilog) for a full adder with active
high enablei (08 Marks)
c. WriteHDL codesfor 2x 2-bit combinationalan4ymultiplier. (06Marks)

a. ExplainIF andCASE statements with examples. (08 Marks)

b. ExplainBooth algorithmwith a flow chart.Write VHDL or Verilog descriptionfor 4x 4-
bit Boothalgorithm. (12 Marks)

a. Whatis Binding?Discussthebindingbetweenlibraryand components. (08 Marks)

b. Write the HDL descrilltionof 2:l multiplexerwith activelow enablein VHDLA/erilog,
usingstructuralstyle; (12Marks)

PART. B
t u: Explainthefoitowing with syntal @ Prgcedures in VHDL (ii) Tasksin Verrlog
(06Marks)
b. Write VHDLA/erilog code to convert a fractional Binary to Real number using
Procedures/Tasks. (08 Marks)
all f,rleprocessing
tasksin Verilog. ' (06 Marks)
c. Describe
of Mixed-typedescription?
a. Whatis thenecessity (04 Marks)
b. Describethe developmentof HDL code for aq Arithrnetic Logic Unit and write
VHDLA/erilogcodefor anALU, showpin fig.6(b). (16 Marks)

|
*- . ,
1-fuL1nP&w gi|t

*'ffihl<tru^,'

Fig.6(b)
Assumethe following operations: - Addition,Multiplication,Division,No Operation.
7a . How to invokea VHDL entityfrom a Verilog module. (08Marks)
'b. Explainmixed languagedescriptionof a JK Flip - Flop with a -clearpin and write the
: (12Marks)
simulationwaveform.
a. Describesynthesisinlbrmation extraction from entity and module with examples.

b. Explainmapping the signal- assignmentand variableassignmentstatements

to Gate=level
with suitableexamples. (10Marks)
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I UsN 06EC4s
I Fourth semester B.E. Degree Examination, June/July 0g
Fundamentals of VHDL
Time:3 hrs. Max. Marks:100
Notc : Ansryet any FIWfuIl questions choosing at least TWefrom each part.

part - A
ta. Explain how data types are classified in HDL. Mention the advantagesof VHDL
data
types over verilog. (06 Marks)
' , , b . Writebehavioral?escripioriofthecircuitofFig.l(b)usingVIDL. (06 Marks)

Fie'l(b) j
F?t th: h".^ry| circuit of Fig.l(c) write-switchlevel descriptionin verilog.Explainthe
advantage of this typedescriptionovertheothertyp:e.
'.. 1oaruart<sy

fr (p 14p$
Y
nr CNrtos)

flr'4
Fig.l(c)

2 &" With illustrationsbriefly discuss

D Signaldeclaration andassignment statements
ii) Concurrent signalassignment statementsand
iii) Constantdeclaration andassigrmentstatements. (09Marks)
l of2
 +
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06EC45
':
b . For the multiplexercircuit of Fig.2(b),write sigrlal declarationand assignmentstatements
in VHDL. Assume10 nsecas propagation delay. Write your comments,wherever it is
applicable.

Fig.2(b)
Explain how an object that has a rvidth of more than I bit is declaredin HDL usingvector
datatypes.Give examples. (05Marks)
a. Write behavioraldescriptionof half adder in VHDL and verilog with propagationdelay of
5 nsec,Discussthe important featuresof their descriptionin VHDL andverilog. (08Marks)
b. Explain the structureof various loop statementsin HDL with examples. (12Marks)
a. What is binding?Discussbindingbetween
i) Entity and architecture
ii) Entity and componentsand
iib ninaing betweenlibraryand modulein VHDL with examples. (09Marks)
b. Write complete VFIDL description for full adder using two half adders.Explain how
bindingis incorporatedwith half adder. (ll Marks)
Part * B
5a. Explainthe following syntaxwith examples:
D Procedure ii) Task and iii) Function (08 Marks)
b . Write VHDL descriptionof an N bit ripple carry adderusing procedure. (12 Marks)
6a. Describeall file processingproceduresin VHDL with examples. (08 Marks)
b . Why mixedtype descriptionis needed?Explain (04 Marks)
c. Write a VIIDL codefor finding largestelementof an array. (08 Marks)
ta . How to invoke a verilog modulefrom VHDL module?Write a mixed languagedescription
of an 'OR' gatewhere VHDL code invokesthe verilog module 'OR3' (3 input OR gate).
(10Marks)
b. Write a mixed languagedescriptionof a 4 bit adderwith zero flag. (10lflarks)
8a . What arethe limitations of mixed languagedescription? (05S{arks)
b. Discusssomeof the importantfactsrelatedto synthesis. (07Marks)
c, Discusssynthesisinformationfrom entity with examples. (08lllarks)
2 of?