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Organization
(SWE 203)
Dr. R. Bhargavi
SCSE
Syllabus
Unit I - FUNDAMENTALS OF COMPUTER ARCHITECTURE
Organization of the von Neumann machine; Instruction formats;
The fetch/execute cycle, instruction decoding and execution;
Registers and register files; Instruction types and addressing
modes; Subroutine call and return mechanisms; Programming in
assembly language; I/O techniques and interrupts; Other design
issues
Unit II - COMPUTER ARITHMETIC
Data Representation, Hardware and software implementation of
arithmetic unit for common arithmetic operations: addition,
subtraction, multiplication, division( Fixed point and floating
point); Conversion between integer and real numbers;
Representation of non-numeric data (character codes, graphical
data)
Syllabus (cont )
Unit III - MEMORY SYSTEM ORGANIZATION & ARCHITECTURE
Memory systems hierarchy; Coding, data compression, and data
integrity; Electronic, magnetic and optical technologies; Main
memory organization, Types of Main memories, and its
characteristics and performance; Latency, cycle time, bandwidth, and
interleaving; Cache memories (address mapping, line size,
replacement and write-back policies); Virtual memory systems;
Reliability of memory systems; error detecting and error correcting
systems
Unit IV - INTERFACING AND COMMUNICATION
I/O fundamentals: handshaking, buffering; I/O techniques:
programmed I/O, interrupt-driven I/O, DMA; Interrupt structures:
vectored and prioritized, interrupt overhead, interrupts and
reentrant code; Buses: bus protocols, local and geographic
arbitration.
Syllabus (cont )
Unit V - DEVICE SUBSYSTEMS
External storage systems; organization and structure of disk drives
and optical memory ; Basic I/O controllers such as a keyboard and a
mouse; RAID architectures; I/O Performance; Processor to network
interfaces.
Reference Books
1.Carl Hamacher, Zvonko Vranesic, Safwat Zaky,
Computer organization, Mc Graw Hill, Fifth
edition ,Reprint 2011.
2.David A. Patterson and . John L. Hennessy
Computer Organization and Design-The
Hardware/Software Interface 5th edition,
Morgan Kaufmann, 2011
3.W. Stallings, Computer organization and
architecture, Prentice-Hall, 8th edition, 2009.
Introduction
Basic functional components of a computer
Input
ALU
Memory
Output
I/O
Control Unit
Processor
IAS - details
1000 x 40 bit words
Binary number
2 x 20 bit instructions
Set of registers (storage in CPU)
Memory Buffer Register
Memory Address Register
Instruction Register
Instruction Buffer Register
Program Counter
Accumulator
Multiplier Quotient
IAS Structure
39
Number word
78
Left Instruction
Opcode
19 20
Address
Instruction word
27 28
Right Instruction
39
Instruction Format
Instruction Fields
Opcode Specifies the operation.
Address Specifies the memory address/
Register.
Mode Specifies the way the operand or
effective address is determined.
ALU
Output
CPU
Memory Unit
Instruction
Memory
Control
Unit
Data
Memory
I/O
Harvard Model
Computer Components:
Top Level View
Instruction Cycle
Two steps:
Fetch Read instruction from memory one at a time
Execute
Fetch Cycle
Program Counter (PC) holds address of next
instruction to fetch
Processor fetches instruction from memory
location pointed to by PC
Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs
required actions
Execute Cycle
Processor-memory
data transfer between CPU and main memory
Processor - I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
e.g. jump
Combination of above
Assumptions:
Instruction/data 16 bits
4 bits opcode
12 bits address
Addressing Modes
Addressing modes: The different ways in which the
location of an operand is specified in an instruction.
Immediate
Direct or Absolute
Indirect
Register
Register Indirect
Displacement (Indexed)
Memory Indirect
Autoicrement
Autodecrement
Base Index
Immediate Addressing
Operand is part of instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range
Instruction
Opcode
Operand
Direct Addressing
Address field contains address of operand
Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective
address.
Limited address space.
Opcode
Address A
Memory
Operand
Indirect Addressing
Memory cell pointed to by address field contains
the address of (pointer to) the operand
EA = (A)
Look in A, find address (A) and look there for
operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A
to accumulator
Large address space
Multiple memory accesses to find operand.
Hence slower
Opcode
Address A
Memory
Pointer to operand
Operand
Register Addressing
Operand is held in register named in address filed
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch
No memory access
Very fast execution
Very limited address space
Register Address R
Registers
Operand
Register Address R
Memory
Registers
Pointer to Operand
Operand
Displacement Addressing
EA = A + (R)
Address field hold two values
A = base value
R = register that holds displacement
or vice versa
Register R
Address A
Memory
Registers
Pointer to Operand
Operand
Indexed Addressing
EA = A + R
A = base
R = displacement
eg. X(Ri)
EA = X + [Ri]
1.
2.
3.
4.
5.
1220
Part of the instruction
5830
4599
1200
CPU organization
Single accumulator organization
One address field
Stack Organization
Zero address fields for operation-type
instructions.
Hybrid Organization
Instruction Types
Three address instructions
operation Destination, source1, source2
Example : Add R, X, Y // R X + Y
Advantages: Results in writing short programs
Disadvantages: More bits are needed to specify three
addresses.
Two address instructions
operation Destination, source
Example: Add R, X // R R + X
Advantages: Results in writing medium size programs
Disadvantages: More bits are needed to specify two
addresses.
Exercise
Consider the expression X = (A + B) * (C + D)
A, B, C, D, and X are the memory addresses.
Write the sequence of instructions to solve the above expression using
3 address, 2 address, 1 address and zero address instruction types
Arithmetic operations : ADD, SUB, MUL, DIV.
Data transfer operations : MOV
Transfer between Accumulator and memory : LOAD, STORE
At least one register operand must be used
// R1 M[A]
// R1 R1 + M[B]
// R2 M[C]
// R1 R1 * R2
// M[X] R1
Byte Addressability
Bit, Byte, Word
Bytes are always 8 bits.
Word length typically ranges from 16 to 64 bits.
Successive memory addressing assignments
refer to successive byte locations in memory
Memory is byte-addressable.
If the word length is 32, successive words are
located at addresses 0, 4, 8,.
Word length
Signed integer:
Most significant bit stores sign information
MSB
b31
LSB
b30
32 bits
b2
b1
b0
Byte address
Byte address
2 - 4
2 - 4
2 - 3
2 - 2
2 - 1
2 - 4
2 - 1
2 - 2
2 - 3
2 - 4
Little endian :
Word address
100
104
100
101
102
103
12
34
56
78
100
101
102
103
78
56
34
12
Translation Hierarchy
C Program
Compiler
Assembly Language Program
Assembler
Linker
Executable: Machine language program
Loader
Memory
Machine Language
Consists of individual instructions that will be executed by
the CPU one at a time
Assembly Language
Machine instructions are represented in 0s and 1s
Very difficult to read, interpret and write.
Mnemonics : Group of bits in machine language.
Assembly Language : Set of mnemonics along with
the rules for using them.
Assembly language format
Label
Operation Operand(s)
Comments
Assembler : Translates Assembly language program
into machine language code.
Assembler
Translates
Assembly language program into
executable machine language object code. This is
done by
Replacing all symbols denoting operations and
addressing modes with the binary codes
Replacing all names and labels with their actual
value.
If the program contains a branch to a later location
in the code (a forward branch), the assembler wont
know where to find the branch target because it
would not have seen it yet.
Assembler (cont )
Most assemblers are two-pass assemblers.
On the first pass, any labels found in the
program are put into the symbol table along
with the corresponding numerical value.
Code labels memory location of instruction
Variable labels memory location of
reserved memory
Constants (EQU) value of constant
On the second pass, all labels in the code are
replaced with their values from the symbol
table.
Example
Label
SUM
N
NUM1
START
LOOP
Operation
EQU
ORIGIN
DATAWORD
RESERVE
ORIGIN
MOVE
MOVE
CLR
ADD
ADD
DEC
BGTZ
MOVE
RETURN
END
Addressing/data information
200
204
100
400
100
N, R1
#NUM1, R2
R0
(R2), R0
#4, R2
R1
LOOP
R0, SUM
Example (cont)
100
104
108
LOOP 112
116
120
124
128
SUM
N
NUM1
NUM2
Numn
200
204
208
212
604
MOVE
MOVE
CLR
ADD
ADD
DEC
BGTZ
MOVE
100
N, R1
#NUM1, R2
R0
(R2), R0
#4, R2
R1
LOOP
R0, SUM
Stack
Stack (cont)
A stack can be organized as a collection of a finite
number of registers.
Stack (cont)
In a 64-word stack, the stack pointer contains 6
bits (2 6 = 64).
The one-bit register FULL is set to 1 when the
stack is full
EMPTY register is 1 when the stack is empty.
The data register DR holds the data to be written
into or read from the stack.
Pop
DR M[SP]
SP SP - 1
If (SP = 0) then (EMPTY 1)
FULL 0
Stack (cont)
The stack normally grows backwards in the memory.
In other words, the programmer defines the bottom
of the stack and the stack grows up into reducing
0
address range.
Stack pointer reg.
Push
Sub #4, sp
Mov ITEM, (SP)
Pop
Mov (sp), ITEM
Add #4, sp
SP
56
29
Stack
Bottom
13
2k - 1
Subroutines
A subroutine is a group of instructions that will be
used repeatedly in different locations of the
program.
Instead of repeating the same instructions several
times, they can be grouped into a subroutine that
can be called from the different locations.
In Assembly language, a subroutine can exist
anywhere in the code.
However, it is customary to place subroutines
separately from the main program.
Subroutines (cont)
Can be called multiple times to perform task
By main program
By another subroutine
Call and Return instructions
Call a subroutine
Return from the subroutine
Subroutines (cont)
Subroutine linkage using link register
CALL instruction performs the following operations
Store the contents of PC in the link register.
Brach to the target address specified by the instruction.
Parameter Passing
Information exchanged between a calling program
and a subroutine
Call by Reference:
The data is stored in one of the registers by the
calling program and the subroutine uses the value
from the register. The register values get modified
within the subroutine. Then these modifications
will be transferred back to the calling program upon
returning from a subroutine
LOOP
[R2]
[R1]
[R0]
Return Address
n
NUM1
Saved [R1]
Saved [R0]
Local Var 2
Local Var 1
FP
Frame
pointer
Saved [FP]
Stack Frame
for called
subroutine
Return Address
Parameter 1
Parameter 2
Parameter 3
Old TOS
Register
Parallel load register
X31 0 : Input
Z31 0 : output
C Control
clk
Input/Output Problems
Wide variety of peripherals
Delivering different amounts of data
At different speeds
In different formats
All slower than CPU and RAM
Need I/O modules
I/O Mapping
Memory mapped I/O
Devices and memory share an address space
I/O access looks just like memory access
No special commands for I/O
Large selection of memory access commands
available
Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special commands for I/O
Limited set
Processor
DATAIN
SIN
Keyboard
DATAOUT
SOUT
Display
Address
Decoder
Control ckt
I/O interface
Input Device
BUS
Move
Testbit
Branch=0
MoveByte
#LOC, R1
#3, INSTATUS
READWAIT
DATAIN, (R1)
Interrupts
Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
Interrupts (cont)
Interrupt request signal
Interrupt-acknowledgement signal
Interrupt service routine
Interrupt latency Delay between the
time an interrupt request signal is received
and the start of the execution of the
interrupt service routine.
Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler
routine
Process interrupt
Restore context and continue interrupted
program
Interrupt Hardware
Interrupt Request
Single Line
Interrupt Request
CPU
Interrupt
Resource
Multiple Line
Interrupt Request
Interrupt
Resource
CPU
Interrupt
Resource
Mixed Interrupt
Request
...
CPU
Interrupt Interrupt
Resource Resource
Interrupt
Resource
...
...
Interrupt Interrupt
Resource Resource
...
Interrupt Nesting
Simultaneous Requests
Quiz 1
1. Consider the following possibilities for saving the return
address of a subroutine.
In a processor register
In a memory location associated with the call, so that a
different location is used when the subroutine is called
from different places.
On a stack.
Which of these possibilities supports subroutine nesting and
which supports subroutine recursion?
2. Why most of the assemblers are two-phase assemblers?
3. Consider 6 devices numbered from 1 through 6 connected to
the bus of a computer. There are priorities to which the devices
belong to. Devices 1, 3 belong to one priority group P1. Similarly
devices 2, 4 belong to priority group P2 and the devices 5 and 6
belong to priority group P3. Among each priority group, the
device with lowest ID has the highest priority. There are three
interrupt lines. With the help of a block diagram implement the
interrupt mechanism for the devices so that the devices can
raise the interrupt whenever required and get served.