Welcome to the AVW 2011

Welcome to the 14thannualIEEJ International Analog VLSI Workshop,

AVLSIWS 2011, at Bali,Indonesia.This workshop is sponsored by the
Research Committee on Electronic Circuits of the Institute of Electrical
Engineers of Japan (IEEJ), and it is being conducted in collaboration
with the IEEE Circuits and Systems Society Japan Chapter,Bandung
Institute of Technology, and IEEE Indonesia Section.
This year, our technical program consists of 2 keynote speeches, 4
invited talks, and 10 regular lecture sessions. Authors from around the
world will be attending the workshop, where they will present their
latest research results. A total of 47 papers fromeightcountries were
submitted for the regular track. This corresponds to an acceptance rate
of 77%.The program has been carefully organized to uphold the
traditional on-track policy.
The AVLSI is an opportunity for our community to congregatein order
share our experiences, exchange ideas and inspirations, discover
research breakthroughs, and establish connections.This workshop has
been organized to overcome difficulties related to analog VLSI among
the main engineering players from universities andindustries, involved
in teaching, research, and technical developments in this field.
We would like to extend our gratitude to all the authors who devoted
considerable time and effortto the preparation of their submitted
papers. We also wish to thank the Technical Program Committee for
AVLSIWS 2011 and the dedicated conference staff for their tireless
support.
Trio Adiono
General Chair
2011 IEEJ International Analog VLSI Workshop

II

III

IV

9:00 - 9:15

Opening Ceremony

9:15 - 10:15

Keynote Speech 1: "Future Power Electronics Possibility for Sustainable Society"

Dr. Hiromichi Ohashi
National Institute of Advanced Industrial Science and Technology, Japan

10:15 - 10:40

Coffee Break

Analog I

10015

An Almost 2VDD Rail-to-Rail Input and Output Operational

Amplifier Using VDD CMOSFETs

Yasuaki Inoue, Zhangcai Huang,

Changquan Jin, Zhao Chen

10027

An Improved Local-Feedback MOS Transconductor for Low

Frequency Applications

Takeshi Ohbuchi, Fujihiko Matsumoto

10031

A Synthesis of Linear Transconductors Using MOSFETs

Operating in Weak-Inversion Region Based on SINH Circuit

Fujihiko Matsumoto, Ryutaro Sugimoto,

Takeshi Ohbuchi, Tomomi Abe

10042

A Constant-gm Rail-to-Rail Operational Amplifier with Lowgain Variation and It's Analysis

Nobuyuki Yokoyama, Cong-Kha Pham

10:40 - 12:00

12:00 - 13:30

Lunch

November 2, 2011
RF Circuit

High Performance SOI CMOS SPMT RF Switch for Cellular

Terminals

Tsuyoshi Sugiura, Kouki Tanji, Norihisa

Otani, Eiichiro Otobe

10022

Power Consumption Improvement of Wideband CMOS

Differential LNAMixer with Two Noise Cancellation

Shintaro Tanaka, Akira Hyogo, Keitaro

Sekine

10023

An Inductorless Variable Gain Mixer with Variable Resistor

for 900-MHz and 2.4-GHz Application

Naoki Tsukahara, Akira Hyogo, Keitaro

Sekine

10025

A Cascode Class-E Power Amplifier with Improved Power

Efficiency by Adding a Parallel Capacitor

Dai Miyauchi, Akira Hyogo, Keitaro

Sekine

Invited I
13:30 - 15:00

15:00 - 15:20

Coffee Break

Converters I

10032

The Multiplier Less Two-path Cross-coupled D-S Modulator

Takeshi Shima, Takumi Ikegami

10038

Continuous-time Delta-sigma Modulator Using Vector Filter in

Feedback Path to Reduce Effect of Clock Jitter and Excess Loop Delay

Yuki Kimura, Akira Yasuda, Michitaka

Yoshino

10041

Complex Bandpass DS Modulator with Bandpass Error

Feedback Structure

Shuhei Kato, Satoshi Saikatsu, Akira

Yasuda, Michitaka Yoshino

10044

Two-Path Delay Line Based Quadrature Band-Pass SigmaDelta Modulator

Nithin Kumar Y.B., Edoardo Bonizzoni,

Amit Patra, Franco Maloberti

15:20 - 16:40

VI

9:00 - 10:10

Keynote Speech 2: "Real-Time WiMAX System on Chip Design, Impelementation and Field Test
Dr. Trio Adiono
Bandung Institute of Technology

10:10 - 10:30

Coffee Break

Sensor & Signal Processing

Power Management of Autonomous Wireless Sensor Node

Prof. Toshihiko Hamasaki

10019

Low-power Wake-up Reciever With Subthreshold CMOS

Circuits for Wireless Sensor Networks

Kazuhiro Takahagi, Hiromichi Matsushita, Tomoki Iida,

Masayuki Ikebe, Yoshihito Amemiya, Eiichi Sano

10020

A CMOS Optical-Flow Image Sensor Based on SpeedAdaptive Multiple-Frame Single-Pixel-Shift Block Matching

Takemasa Komori and Tadashi Shibata

10036

An Analog K-means Learning Processor Employing FullyParallel Self-Converging Circuitry

Renyuan Zhang, Tadashi Shibata

Invited II

10:30 - 12:00

12:00 - 13:40

Lunch

Power Supply & Management

November 3, 2011

13:40 - 15:00

10003

A Novel Low Quiescent Current PFM Method with

Independent Threshold for Buck Switching Converters

Bin Shao

10004

Flexible UFR Island to Prevent Black Out

Rukmito Ari Ardianto, Djuma'iyah

10026

A Small, Low Power Boost Regulator Optimized for Energy

Harvesting Applications

Zachary Nosker, Yasunori Kobori, Haruo Kobayashi, Kiichi

Niitsu, Nobukazu Takai, Takeshi Oomori, Takahiro
Odaguchi, Isao Nakanishi, Kenji Nemoto, Junichi Matsuda

10030

Digital Simulation of the Generalized Unified Power Flow

Controller System with 60-pulse GTO-based VSC

Rakhmad Syafutra Lubis

15:00 - 15:20

Coffee Break

Signal Processing & Communication I

Invited III

15:20 - 16:50

TBD

Prof. Siddik Yarman

10013

Optimum VLSI Architecture of High Performance

Synchronizer for WiMAX OFDMA System

Nana Sutisna , Trio Adiono

10018

Architecture of High-Efficiency Digitally-Controlled Class-E

Power Amplifier

Jiani Ye, Zachary Nosker, Kazuyuki Wakabayashi, Takuya

Yagi, Nobukazu Takai, Kiichi Niitsu, Keisuke Kato, Takao
Ootsuki, Haruo Kobayashi, Osamu Yamamoto, Isao Akiyama

10047

Design of Wide Gain Range CMOS VGA for WLAN Receiver Laksono Widyo Isworo, Cosy Muto,
Hiroshi Ochi, Hiroshi Tanimoto

19:00

Gala Dinner & Award Ceremony

VII

Signal Processing & Communication II

Invited IV

TBD

Dr. Satoru Shingai

10028

Implementation of Low-Noise Switched-Capacitor Low-pass

Filters with Small Area

Nicodimus Retdian, Shigetaka Takagi

10037

Loop Design Optimization of 4th-Order Fractional-N PLL

Frequency Synthesizers

Lee Jun Gyu, Shoichi Masui

10046

Active Inductor Design using Distortion Reduction Technique

Takahide Sato, Toshihiro Ito

10024

A gain improved CMOS LNA using Negative Resistance of

an Active Inductor

Dai Ichihoshi, Akira Hyogo, Keitaro

Sekine

09:00 - 10:50

10:50 - 11:10

Coffee Break

Digital Signal Processing

10017

Design and Implementation 2k/4k/8k FFT-IFFT Core using

Block Floating Point for DVB-T and DVB-H

Ir. Amy Hamidah Salman, MSc, Andyes

Fourman Duta Akbar Sudirdja, ST

10034

An Optimized 8-Level Turbo Decoder Algorithm and VLSI

Architecture for LTE

Ardimas Andi Purwita, Trio Adiono

11:10 - 11:50

November 4, 2011

Lunch

11:50 - 13:50

Converters II

10040

Robust Switched-Capacitor ADC Based on Betaexpansion

Tsubasa Maruyama, Hao San and

Masao Hotta

13:50 - 15:10
10012

Non-Binary Pipelined ADC with b-Encoding

Hao San, Tomonari Kato, Tsubasa

Maruyama, Masao Hotta

10014

Substrate Noise Measurement and Analysis on the

Components of the Pipeline Analog to Digital Converter

Annisa Karima, Kazuyuki Wada

10029

Telescopic Op-Amp Design with CMFB for 1.5 bit/stage

Pipelined ADC

Mohd Hairi, Zulfiqar Ali Abdul Aziz

15:10 - 15:30

Coffee Break

Analog II

10039

Temperature Coefficient Improvement of PTAT Voltage

Generator Based on Temperature Dependence of
MOSFET Threshold Voltage

Junichi Fujitsuka, Kawori Sekine

10043

A Linearity Optimization Method for CMOS R-2R Ladder

Network

Yuta Kato, Cong-Kha Pham

10009

A Novel Bulk Input Four Quadrant Analog Multiplier in

Weak Inversion

Antaryami Panigrahi, Prashanta Kumar

Paul

15:30 - 16:30

16:30

Closing Ceremony

VIII

Map of AVW 2011

Bali Room at Melia Hotel

IX

Contents
Invited Paper II : High Performance SOI CMOS SPMT RF Switch for
Cellular Terminals ..........................................................................................1
Invited Paper II : Power ManagementofAutonomous of Wireless
Sensor Node.....................................................................................................1
10003 : A Novel Low Quiescent Current PFM Method with Independent
Threshold for Buck Switching Converters ......................................................2
10009 : A Novel Bulk-input Low Voltage and Low Power Four
Quadrant Analog Multiplier in Weak Inversion ...........................................2
10012 : Non-Binary Pipeline ADC with b-Encoding ..................................................2
10013 : Optimum VLSI architecture of high performance
Synchronizer for WiMAX OFDMA system ....................................................3
10014 : Substrate Noise Measurement and Analysis on the
Components of the Pipeline Analog to Digital Converter .............................3
10015 : An Almost 2VDD Rail-to-Rail Input and Output Operational
Amplifier Using VDD CMOSFETs ................................................................3
10017 : Design and Implementation 2k/4k/8k FFT-IFFT Core using
Block Floating Point .......................................................................................4
10018 : Architecture of High-Efficiency Digitally-Controlled Class-E
Power Amplifier
................................................................................4
10019 : Low-power Wake-up Receiver With Sub-threshold CMOS
Circuits for Wireless Sensor Networks ..........................................................5
10020 : A CMOS Optical-Flow Image Sensor Based on SpeedAdaptive Multiple-Frame Single-Pixel-Shift Block Matching .....................5
10022 : Power Consumption Improvement of Wideband CMOS
Differential LNAMixer with Two Noise Cancellation ................................6
10023 : An Inductorless Variable Gain Mixer with Variable Resistor
for 900-MHz and 2.4-GHz application ...........................................................6
10024 : A gain improved CMOS LNA using negative resistance of an
active inductor .................................................................................................6
10025 : A Cascode Class-E Power Amplifier with Improved Power
Efficiency by Adding a Parallel Capacitor .....................................................7
10026 : A Small, Low Power Boost Regulator Optimized for Energy
Harvesting Applications .................................................................................7
10027 : An Improved Local-Feedback MOS Transconductor for Low
Frequency Applications ..................................................................................7
10028 : Implementation of Low-Noise Switched-Capacitor Low-pass
Filters with Small Area ..................................................................................8
10029 : Telescopic Op-Amp Design with CMFB for 1.5 bit/stage
Pipelined ADC .................................................................................................8
10030 : Digital Simulation of the Generalized Unified Power Flow
Controller System with 60-pulse GTO-based VSC .......................................9

Contents
10031 : A Synthesis of Linear Transconductors Using MOSFETs
Operating in Weak-Inversion Region Based on SINH Circuit ......................9
10032 : The Multiplier Less Two-path Cross-coupled - Modulator ....................10
10034 : An Optimized 8-Level Turbo Decoder Algorithm and VLSI
Architecture for LTE .....................................................................................10
10036 : An Analog K-means Learning Processor Employing FullyParallel Self-Converging Circuitry ...............................................................11
10037 : Loop Design Optimization of 4th-Order Fractional-N PLL
Frequency Synthesizers ................................................................................11
10038 : Continuous-time delta-sigma modulator using vector filter
in feedback path to reduce effect of clock jitter and excess
loop delay........................................................................................................12
10039 : Temperature Coefficient Improvement of PTAT Voltage
Generator Based on Temperature Dependence of MOSFET
Threshold Voltage ..........................................................................................12
10040 : Robust Switched-Capacitor ADC based on b-expansion .............................13
10041 : Complex Bandpass Modulator with Bandpass Error
Feedback Structure .......................................................................................13
10042 : A Constant-gm Rail-to-Rail Operational Amplifier with
Low-gain Variation and It's Analysis ...........................................................14
10043 : A Linearity Optimization Method for CMOS R-2R Ladder
Network ..........................................................................................................14
10044 : Two-Path Delay Line Based Quadrature Band-Pass
Modulator .......................................................................................................15
10046 : Active Inductor Design using Distortion Reduction
Technique .......................................................................................................15
10047 : Design of Wide Gain Range CMOS VGA for WLAN Receiver ....................15

XI

Invited Paper I
High Performance SOI CMOS SPMT RF Switch for Cellular
Terminals
Tsuyoshi Sugiura, Kouki Tanji, Norihisa Otani, Eiichiro Otobe
Samsung Yokohama Research Institute, Kanagawa, Japan
AbstractWe have developed a single pole multi-throw (SPMT) RF antenna switch that
is based on high resistivity 0.18-um partially depleted (PD) silicon on insulator (SOI)
CMOS technology with low insertion loss, high linearity, and small chip size. Body
contacted (BC) and multi-stacked FETs are chosen to achieve a high linearity and high
power handling. A switch driver circuit is integrated with a RF switch on the same chip.
The wafer level chip size package (WLCSP) is chosen for its consumer advantage. The
measured data of the RF switch shows that the insertion loss of the TRX/TX port is less
than 0.40 dB at 850 MHZ and 0.55 dB at 1900 MHz in the case of SP7T. For SP12T, the
insertion loss of the TRX/TX port was less than 0.53 dB at 850 MHz, 0.70 dB at 1900
MHz, and 0.74 dB at 2200 MHz. The 2nd & 3rd harmonics are averaged to -60 dBm at
Pin 35 dBm and 850 MHz, and -45 dBm at Pin 33 dBm and 1900 MHZ, respectively. The
RF switch chips are 1.1 x 1.1 mm, 1.2 x 1.6 mm, and 1.2 x 1.8 mm for SP7T, SP10T, and
SP12T, respectively. Our developed SOI CMOS SPMT RF switch is suitable for the
commercial cellular phone market.

Invited Paper II
Power ManagementofAutonomous of Wireless Sensor Node
Toshihiko Hamasaki
Information Systems and Sciences
Hiroshima Institute of Technology, Hiroshima, Japan
AbstractThis paper presents the design concepts of wireless sensor network system
constructed with autonomous sensing nodes, which operates at extremely low power
levels. At first, conventional, wired civil structure health monitoring (SHM) system is
reviewed. Then, the monitoring methodology is discussed focusing quantitative
measurement accuracy. Issues of node synchronized sampling, multi-Layer cluster and
integrated sensor node module are discussed. Also, radio transceiver protocol
candidates are reviewed fromthe point of connection to the internet gateway. Sensor
node consists of microprocessor, sensing analog front end, and radio transceiver. Last
two factors are critical for power consumption. Therefore, low duty cycle measurement
is essential, in order to accomplish the ultra low power level, which is equivalent to
energy harvesting source, such as piezoelectric and solar cells, sensor node power
management device circuit design is demonstrated for the high-spec measurement.

10003
A Novel Low Quiescent Current PFM Method with Independent
Threshold for Buck Switching Converters
Bin Shao.
Analog Devices, Shanghai Design Center, Shanghai, China
Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
AbstractEfficiency is the key parameter of the switching regulators. PFM (Pulse
Frequency Modulation) is often used to reduce the dynamic loss at the light load
condition, while PWM (Pulse Width Modulation) is used in heavy load case. The
efficiency at the heavy load is usually process dependent, however there are many
circuits design considerations for the efficiency improvement and other electrical
performances in light load case. This paper will propose a method which can get the
accurate PFM threshold independent to input voltage, output voltage, switching
frequency and inductor value; as well as the accurate zero cross comparator and very
low quiescent current consumption in the skip period.

10009
A Novel Bulk-input Low Voltage and Low Power Four Quadrant
Analog Multiplier in Weak Inversion
Antaryami Panigrahi, Prashanta Kumar Paul.
Department of Electronics and Communication
Engineering, National Institute of Technology, Silchar, Assam, India
AbstractA new four quadrant voltage mode bulk input analog multiplier is presented
.The proposed multiplier is designed to operate in weak inversion. Multiplication is done
by driving the bulk terminals of the MOS devices which offers higher linear dynamic
range of 80mV.The simulation shows, it has a linearity error of 5.6%, THD of nearly 5%
and -3dB band width of 221 kHz. Total power consumption is very low i.e. 714nW. The
circuit operates at a supply voltage of 0.5V and is designed using AMI .6um CMOS
technology. It is suitable for low power bioelectronics and neural applications.

10012
Non-Binary Pipeline ADC with b-Encoding
Hao San, Tomonari Kato, Tsubasa Maruyama, Masao Hotta.
Integrated System Laboratory, Tokyo City University
Tamazutsumi1-28-1,Setagaya-ku,Tokyo,158-8557Japan
AbstractThis paper proposes a non-binary pipeline ADC architecture based onexpansion. Proposed radix- 1bit pipeline stage with switched-capacitor (SC) multiplying
digital-to-analog converter (MDAC) is similar to the convention alone. However, the
interstage gain of MDACs is (1 << 2) not 2. The redundancy of non-binary ADC with
radix tolerates mismatches of capacitances and finite DC gain of operational amplifier
(op-amp) in MDACs. The power hungry high gain op-amps are not necessary in our
proposed architecture, so that the reliability enhanced pipeline ADC with simple
amplifier can operate faster and with lower power. We analyse the encoding technique
and modify it for pipeline ADC. We also conducted MATLAB simulations to verify the
reliability of the proposed architecture and algorithm.
2

10013
Optimum VLSI architecture of high performance synchronizer for
WiMAX OFDMA system
Nana Sutisna, Trio Adiono.
Bandung Institute of Technology,Bandung 40132 West Java Indonesia
AbstractThis paper proposes an optimum VLSI architecture for frame synchronization
in WiMAX OFDMA downlink system. Proposed synchronization method utilizes
preamble properties by exploiting conjugate symmetry, periodicity of preamble and CP
repetition. Using proposed method, synchronization rate is very high under various
channel condition. Some critical issues in hardware implementation, such as
computational complexity, area efficiency, low latency processing, and low power
design are addressed to obtain optimum architecture design. Design 2 implementation
result shows chip area is about 2.7 mm and achieves targeted 56 MHz clock frequency.

10014
Substrate Noise Measurement and Analysis on the Components of
the Pipeline Analog to Digital Converter
Annisa Karima, Kazuyuki Wada.
Department Information and Computer Science, Toyohashi University of Technology
1-1, Hibarigaoka, Tempaku-cho, Toyohashi, Aichi, JAPAN 441-8580
Abstract Substrate noise around shift register (SR) that designed and fabricated in
ROHM 0.18 m standard CMOS process are measured. Substrate potential has slight
signal changes about several tens milivolts. Resistor networks can be used as substrate
model for system with digital parts working below 80 MHz. Model of substrate noise
propagation can be reproduced by using resistor network and 8 transistors as simple
substrate noise sources. From measurement result of Pipeline Analog to Digital
Converter (ADC), substrate noise didnt affect the system of fully differential amplifier.
Substrate noise also makes uncertainty on decision time delay of comparator known as
jitter. The comparator its self can generate substrate noise due to switching phase.

10015
An Almost 2VDD Rail-to-Rail Input and Output Operational Amplifier
Using VDD CMOSFETs
Yasuaki Inoue, Changquan Jin, Zhao Chen.
Graduate School of Information, Production and Systems
Waseda University, Kitakyushu, Japan
Zhangcai Huang
Fukuoka Industry Science Technology Foundation
Fukuoka, Japan
AbstractIn this paper, we propose a high-voltage tolerant rail-to-rail input and
operational amplifier with almost 2VDD output over the device breakdown voltage VDD.
The proposed amplifier is verified by circuit simulation using a 0.18um standard CMOS
process, where VDD =1.8V. The simulation results show that the proposed circuit has a
common-mode input voltage range and an output voltage swing of almost 2VDD .
3

10017
Design and Implementation 2k/4k/8k FFT-IFFT Core using Block
Floating Point
Amy Hamidah Salman, Andyes Fourman Duta Akbar Sudirdja.
Electrical Engineering, Sekolah Teknik Elektro dan Informatika
Institut Teknologi Bandung, Indonesia
AbstractDVB-H and DVB-T are digital television standard created by DVB consortium
in Europe. DVB-T used for static digital television (terrestrial) whereas DVB-T used for
mobile digital television. These two DVB standard using OFDM modulation technique.
This modulation allow each sub-carrier neighboring without creating inter carrier
interference (ICI). The modulation using IFFT to convert data signal from frequency
domain into time domain. And in demodulation part used FFT module which convert it
back into frequency domain in receiver module. FFT-IFFT 2k/4k/8k using Block Floating
Point (BFP) which made support FFT and IFFT algorithm for 2048 points, 4096 points
and 8192 points mode. The FFT-IFFT core created using radix-2, radix-4 and radix-8.
Designed to receive data continuously without temporary buffer. The design of FFTIFFT module 2k/4k/8k started with MATLAB functional design as a model for the next
stage. Furthermore, the hardware architecture design is made referring to the
functional modelling design using MATLAB . This architectural design will be the
foundation in making bit precision modelling. And then bit precision model design as a
foundation for designing hardware using Register Transfer Level (RTL). The results of
the FFT-IFFT output modules meet standards set by the DVB consortium with the
results of testing the maximum frequency of FFT-IFFT 2k/4k/8k Core using Block
Floating Point (BFP) is 72.83 MHz which has been shown that qualify on the standard
(40 MHZ). In addition the module has a high throughput with an average throughput has
39.7 M symbols / s.

10018
Architecture of High-Efficiency Digitally-Controlled Class-E Power
Amplifier
Jiani Ye, Zachary Nosker, Yasunori Kobori, Haruo Kobayashi, Kiichi Niitsu, Nobukazu
Takai, Takeshi Oomori, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto, Junichi
Matsuda.
Department of Electronic Engineering, Gunma University Faculty of Engineering
1-5-1, Tenjincho, Kiryu, Gunma 376-8515
AbstractThis paper describes the analysis and design of digitally-controlled class-E
power amplifiers, which are suitable for fine CMOS implementation. Two methods for
implementing digitally-controlled class-E(-like) amplifiers have already been proposed:
using NMOS switch arrays or digital PWM. In this paper we analyze the operation and
efficiency of these methods, and then propose combining them to achieve higher
efficiency.

10019
Low-power Wake-up Receiver With Subthreshold CMOS Circuits for
Wireless Sensor Networks
Kazuhiro Takahagi, Hiromichi Matsushita, Tomoki Iida, Masayuki Ikebe, Yoshihito
Amemiya, Eiichi Sano.
Graduate School of Information Science and Technology, Research Center for
Integrated Quantum Electronics, Hokkaido University, Sapporo 0600814 Japan
Abstract We developed a wake-up receiver comprised of subthreshold CMOS
circuits. The proposed receiver includes an envelope detector, a high-gain baseband
amplifier, clock and data recovery (CDR), and a wake-up signal recognition circuit. The
drain nonlinearity in the subthreshold region effectively detects the baseband signal with
a microwave carrier. The offset cancellation method with a biasing circuit operated by
the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A
PWM CDR drastically reduces the power consumption of the receiver. A 2.4-GHz
detector and high-gain amplifier were designed and fabricated with 0.18-m CMOS
process with one poly and six metal layers. The fabricated detector and high-gain
amplifier achieved a tangential sensitivity of - 47.2 dBm while consuming only 6.8 W
from a 1.5 V supply.

10020
A CMOS Optical-Flow Image Sensor Based on Speed-Adaptive
Multiple-Frame Single-Pixel-Shift Block Matching
Takemasa Komori, Tadashi Shibata.
Department of Electrical Engineering and Information Systems, The University of Tokyo
7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan
AbstractA CMOS image sensor for calculating optical flow based on 1-pixel-shift
block matching has been developed. In order to detect multiple-speed objects in the
same scene, a multiple-frame block matching scheme has been explored. Each pixel
stores multiple pixel intensities with different time stamps in analog memories and
provides neighboring pixels with appropriate data when the right timing of motion
detection comes in respective neighbors. As a result, multiple-speed objects detection
has been made possible by best-match search only within 1-pixel range. Optical flow is
efficiently calculated in row parallel processing architecture. The proof-of-concept chip
was fabricated in a 0.18-m CMOS technology, which demonstrated the performance of
139 frame/sec at only 10 MHz of operation.

10022
Power Consumption Improvement of Wideband CMOS Differential
LNAMixer with Two Noise Cancellation
Shintaro Tanaka, Akira Hyogo, Keitaro Sekine.
Department of Electrical Engineering, Faculty of Science and Technology
Tokyo University of Science, Japan
AbstractThis paper presents a low power and wideband differential LNA-Mixer in
0.18-m CMOS technology. This method allows wideband input matching and getting a
high conversion gain. In addition, we design the low power LNA -Mixer using two noise
canceling techniques. The simulation results show that a minimum single- sideband
noise figure is 7.6 dB and a conversion gain of more than 20.6 dB from 0.6 to 4.5 GHz. It
has a third-order intermodulation intercept point of -6 dBm at 3GHz. The proposed circuit
consumes 9.7 mW with a 1.2 V supply voltage. Compared to the conventional circuit, we
can reduce the power consumptions of 30 percent. However, simulation results show
0.2dB worse NFs in average compared to conventional one.

10023
An Inductorless Variable Gain Mixer with Variable Resistor for 900MHz and 2.4-GHz application
Naoki Tsukahara, Akira Hyogo, Keitaro Sekine .
Department of Electrical Engineering, Faculty of Science and Technology
Tokyo University of Science, Japan
Abstract This paper presents an inductorless variable gain mixer for two bands use;
900 MHz and 2.4 GHz. By using variable resistor, the proposed mixer has the same
Conversion Gain (CG) at both bands, and it can select from low noise figure mode to low
current mode. The simulation results in a 0.18-m CMOS technology show that we can
select the CG of 15 dB or 10 dB at both bands respectively, noise figure of less than 12
dB or 15 dB and current consumption of less than 6 mA or 2 mA with a 1.8 V supply.

10024
A gain improved CMOS LNA using negative resistanceof an active
inductor
Dai Ichihoshi, Akira Hyogo, Keitaro Sekine.
Department of Electrical Engineering, Faculty of Science and Technology
Tokyo University of Science, Japan
Abstract This paper presentsaCMOS LNAwhich is improvedgain. The proposed LNA
uses negative resistance of an active inductor to improve its gain. The simulation results
using 0.18-? m CMOS technology show that the gain of proposed circuit achieves S21of
27.8dB which is 11.6dB higher than 16.2dB of a LNA with a load inductor.

10025
A Cascode Class-E Power Amplifier with Improved Power Efficiency
by Adding a Parallel Capacitor
Dai Miyauchi, Akira Hyogo, Keitaro Sekine .
Department of Electrical Engineering, Faculty of Science and Technology
Tokyo University of Science, Japan
Abstract This paper presents a cascode class-E power amplifier (PA) with improved
power efficiency by keeping parallel capacitance of switch to be constant. A conventional
cascode class-E PA has an inductor paralleled to a common-source transistor. The
proposed class-E PA inserts a capacitor between the drain node of common-gate
transistor and the source node of that in addition to the conventional circuit. The
simulation results using 0.18 m CMOS technology show that the proposed circuit
improves the drain efficiency of 1.4% compared to the conventional one at gate length
0.4 m.

10026
A Small, Low Power Boost Regulator Optimized for Energy
Harvesting Applications
Zachary Nosker, Yasunori Kobori, Haruo Kobayashi, Kiichi Niitsu,Nobukazu Takai.
Department of Electronic Engineering, Gunma University
Takeshi Oomori, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto
AKM Technology Corporation
Junichi Matsuda
Asahi Kasei, Power Devices Corporation
Abstract A small, low power bootstrapped boost regulator is introduced that can start
up with an input voltage of 240mV and achieve a maximum efficiency of 96%. The
effectiveness of this approach is shown through Spectre simulation results.

10027
An Improved Local-Feedback MOS Transconductor for Low
Frequency Applications
Takeshi Ohbuchi, Fujihiko Matsumoto.
Department of Applied Physics, National Defense Academy
1-10-20, Hashirimizu, Yokosuka, 239-8686, Japan
Abstract For medical devices, low frequency and low power applications are required.
Thus, a transconductor which has a low transconductance is needed. The conventional
current division scheme wastes the operating current. This paper proposes an improved
local-feedback MOS transconductor operating in subthreshold region. The proposed
transconductor is optimally designed using maximally approximation method. From the
optimization, two optimum values are obtained. The characteristics of proposed
transconductor are confirmed by simulation. The transfer characteristics of the
proposed transconductor are linear, and the CMRR around 60 dB and the THD, the
frequency of the sinusoidal input is 1 kHz, under the -50 dB are satisfactory. Simulation
results show validities and availability of the proposed transconductor.
7

10028
Implementation of Low-Noise Switched-Capacitor Low-pass Filters
with Small Area
Nicodimus Retdian, Shigetaka Takagi.
Global Edge Institute, Dept. of Communications & Integrated Systems
Tokyo Institute of Technology, Tokyo, Japan
Abstract A design methodology for implementation of lownoise switched-capacitor
low-pass filter (SC LPF) with small area consumption is proposed. The proposed
method is focused on the reduction of operational amplifier noise transfer gain at low
frequencies and the reduction of total capacitance. A new SC LPF topology is proposed
in order to adapt the correlated double sampling and capacitance scaling technique at
the same time. A design example shows that proposed filter reduces the total
capacitance by 90.4% compared to the conventional one without having significant
increase in noise transfer gain.

10029
Telescopic Op-Amp Design with CMFB for 1.5 bit/stage Pipelined
ADC
Mohd Hairi, Zulfiqar Ali Abdul Aziz.
Department of Electronic Engineering, Gunma University
AbstractThis paper presents the design of fully differential telescopic op-amp with
outstanding characteristic of high bandwidth and slew rate. The fully deferential
telescopic op-amp with common mode feedback (CMFB) has been design using Silterra
0.18m CMOS technology. The fully differential telescopic op-amp has been used to
simulate the operation of 1.5 bit/stage pipelined ADC for Worldwide Interoperability for
Microwave Access (WiMAX) application successfully.
In this paper, the trade-off between gain, bandwidth and current consumptions is a
challenging task. The amplifier consists of two parts, a fully differential telescopic opamp that provides all the open loop gain and common mode feedback to maintain the
constant output voltage. Designed in CMOS technology, the design required 3.3V power
supply and 112mA current consumption to produce 41dB voltage gain with 54.71MHz
bandwidth and 44.81?phase margin. The design has very high slew rate 2.13k V/s and
fast settling time at 7.5ns.

10030
Digital Simulation of the Generalized Unified Power Flow Controller
System with 60-pulse GTO-based VSC
Rakhmad Syafutra Lubis
Electrical Engineering, Syiah Kuala University
Banda Aceh, Indonesia
Abstract The Generalized Unified Power Flow Controller (GUPFC) is a Voltage
Source Converter (VSC) based Flexible AC Transmission System (FACTS) controller
for shunt and series compensation among the multiline transmission systems of a
substation. The paper proposes a full model comprising of 60-pulse Gate Turn-Off
thyristor VSC that is constructed becomes the GUPFC in digital simulation system and
investigates the dynamic operation of control scheme for shunt and two series VSC for
active and reactive power compensation and voltage stabilization of the electric grid
network. The complete digital simulation of the shunt VSC operating as a Static
Synchronous Compensator (STATCOM) controlling voltage at bus and two series VSC
operating as a Static Synchronous Series Capacitor (SSSC) controlling injected
voltage, while keeping injected voltage in quadrature with current within the power
system is performed in the MATLAB/Simulink environment using the Power System
Blockset (PSB). The GUPFC, control system scheme and the electric grid network are
modeled by specific electric blocks from the power system blockset. The controllers for
the shunt VSC and two series VSC are presented in this paper based on a decoupled
current control strategy. The performance of GUPFC schemes connected to the 500-kV
grid are evaluated. The proposed GUPFC controller schemes is fully validated by digital
simulation.

10031
A Synthesis of Linear Transconductors Using MOSFETs Operating
in Weak-Inversion Region Based on SINH Circuit
Fujihiko Matsumoto, Ryutaro Sugimoto, Takeshi Ohbuchi, Tomomi Abe.
Department of Applied Physics, National Defense Academy
1-10-20, Hashirimizu, Yokosuka, Kanagawa, 239-8686, Japan
AbstractIn this paper a synthesis of linear transconductors using MOSFETs operating
in weak-inversion region is pro-posed. The proposed transconductors are extended
SINH circuits, which are based on a SINH circuit with an intermediate voltage terminal.
The transfer characteristic of the SINH circuit is not linear. The linear input ranges of the
proposed transconductors become wider than the SINH circuit. The proposed
transconductors have several intermediate voltage nodes. The intermediate voltages
are realized by an active voltage divider composed of source coupled pairs. The voltage
divider has high input impedance and it is suitable for low-voltage circuits.The simulation
results show that the proposed technique is effective for improvement of the linearity.

10032
The Multiplier Less Two-path Cross-coupled ? Modulator
Takeshi Shima, Takumi Ikegami.
Department of Electronics and Informatics Frontiers
Kanagawa University, Yokohama, Japan 2218686
Abstract The cross-coupled two-path sigma-delta modulator requires the additional
multipliers to improve the noise shaping performance. In this paper, to reduce additional
multipliers in the conventional cross-coupled two-path sigma-delta modulator, two new
circuits are proposed and their stability test analysis is performed.

10034
An Optimized 8-Level Turbo Decoder Algorithm and VLSI
Architecture for LTE
Ardimas Andi Purwita, Trio Adiono.
School of Electrical Engineering and Informatics, Electrical Engineering Department
Institut Teknologi Bandung, Indonesia
AbstractTurbo code is a high performance channel coding which is able to closely
reach the channel capacity of Shannon limit. It plays an important role to increase the
performance in one of the latest standard in the mobile network technology, such as LTE
[1]. In this paper, Turbo code decoder VLSI Architecture is discussed. The optimization is
done to reduce computational complexity and excessive memory requirement as well as
the latency and delay. In order to increase the processing speed, 8-level parallel
architecture is proposed. Furthermore, to increase the processing parallelization, we
also applied the Maxlog-MAP [2][3][4], Sliding Window Algorithm (SWA) [5], and dual
bank ram for interleaver and deinterleaver block. Based on the simulation result,
proposed algorithm is almost 16 faster than original algorithm [6] and 42 times smaller
for the memory requirement. Additionally, proposed algorithm reduces the size of
interleaver and deinterleaver block by almost 50%. Besides, the decoder are also
reduced by applying shared modules.

10

10036
An Analog K-means Learning Processor Employing Fully-Parallel
Self-Converging Circuitry
Renyuan Zhang, Tadashi Shibata.
Department of Electrical Engineering and Information Systems, The University of Tokyo
7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
Abstract A fast self-converging analog K-means learning processor is presented in
this paper for use in image clustering. The image patterns represented by highdimensional vectors can be clustered into different classes based on our proposed
hardwarefriendly version of the K-means algorithm. In order to speed up the K-means
learning, we developed an analog circuit to carry out the Euclidean distance between
high-dimensional vectors in realtime. Furthermore, a fully-parallel learning and selfconverging structure was built employing these analog circuits. The chiparea and
interconnect explosion problem has been resolved in this proposed structure. Since the
learning autonomously proceeds in a fully-parallel manner via analog free-feedback
signals without any clock control, learning can be accomplished within a single clock
cycle, which is far faster than the conventional iterationbased approaches. A proof-ofconcept system was constructed and verified by the HSPICE and Nanosim simulations.
Sixteen actual images of two objects were randomly selected from the database and
converted into 64-dimensional vectors. Feeding these vectors into our K-means system,
the images were all correctly categorized into two classes within one clock cycle for
several different initialization conditions.

10037
Loop Design Optimization of 4th-Order Fractional-N PLL Frequency
Synthesizers
Lee Jun Gyu, Shoichi Masui.
Research Institute of Electrical Communication,
Tohoku University, Sendai, Japan
AbstractWe propose a methodology of loop design optimization for 4th-order
fractional-N PLL frequency synthesizers featuring a settling time of 5? sec for
applications such as an active RFID and automobile smart-key systems. The optimized
design flow overcomes the inaccuracy to derive the relationship between the settling
time and loop bandwidth in the 4th-order PLL by using MATLAB Control System Toolbox
and features the worst-case design against the process, voltage and temperature (PVT)
variations in the loop filter components. Also the trade off between the phase noise and
area is considered. The optimization process consists of 1) derivation of the accurate
relationship between the settling time and loop bandwidth for various PVT conditions, 2)
derivation of phase noise and area as a function of an area-dominant filter capacitance,
and 3) derivation of all loop filter components. The optimized design result is compared
with circuit simulations using an actually designed 4th-order fractional-N PLL in a 1.8V
0.18? m CMOS technology, and the error has been revealed as less than 5.3%
(0.2? sec) that is suitable for the target applications.

11

10038
Continuous-time delta-sigma modulator using vector filter in
feedback path to reduce effect of clock jitter and excess loop delay
Yuki Kimura, Akira Yasuda, Michitaka Yoshino.
Engineering Research Course, Faculty of Science and Engineering
University of Hosei, Koganei, Japan
Abstract In this paper, we propose a novel delta-sigma modulator (DSM) that reduces
the effects of clock jitter and excess loop delay by using a vector filter in the feedback
path. The vector filter divides the input signal into a high-frequency part and a lowfrequency part. The low-pass signal is placed in the path to the first-stage digital-toanalog converter (DAC) for reducing the effects of the clock jitter, and the high-pass
signal is placed in the feedback path to the last integrator in order to compensate for the
excess loop delay. The DSM using the vector filter in the feedback path (DSM-VF) is
verified using MATLAB/Simulink. Further, a clock jitter (0.1%) in DSM-VF leads to an
improvement in the signal-to-noise-ratio (SNR) to 22.5 dB as compared to the SNR of a
conventional CTDSM. Moreover, the SNR deterioration caused by the excess loop
delay is improved.

10039
Temperature Coefficient Improvement of PTAT Voltage Generator
Based on Temperature Dependence of MOSFET Threshold Voltage
Junichi Fujitsuka, Kawori Sekine.
Department of Electric technology, Meiji University
Kanagawa, Japan
AbstractPTAT Voltage Generator is composed with MOSFETs in subthreshold region
at view of ultra low power supply and small scale. Temperature coefficient is low and has
to be improved. Stacking PTAT circuits improve temperature coefficient. However by
stacking PTAT circuits, the range of sensing temperature would be narrow because of
operation region of MOSFETs. In order to keep the range of sensing temperature, the
way of improving temperature coefficient based on temperature dependence of
MOSFET threshold voltage is proposed. The proposed circuit consisting of CTAT
Voltage Generator and level shifter compensates the temperature dependence of
MOSFET threshold voltage. The n-stacked PTAT Voltage Generator with proposed
compensation circuit can improve the temperature coefficient. The proposed circuit was
fabricated with 0.18m n-well CMOS process and measured. The measured value is
compared with theoretical value and considered. The theoretical value of temperature
coefficient is based on diffusion current of four-terminal MOSFET operating in
subthreshold region.

12

10040
Robust Switched-Capacitor ADC based on b-expansion
Tsubasa Maruyama, Hao San, Masao Hotta.
Integrated System Laboratory, Tokyo City University
Tamazutsumi 1-28-1, Setagaya-ku, Tokyo, 158-8557 Japan
Abstract In this paper, a cyclic ADC architecture with b-encoder is proposed and
circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the
conventional binary ADC, the proposed ADC outputs b-expansion code and has an
advantage of error correction. This feature makes ADC robust against capacitor
mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the
power penalty of highgain amplifier and the required accuracy of circuit elements for
high resolution ADC can be relaxed, the proposed architecture is suitable for deep
submicron CMOS technologies beyond 90 nm. We also propose a -value estimation
algorithm to realize high accuracy ADC based on b-encoder.

10041
Complex Bandpass Modulator with Bandpass Error Feedback
Structure
Shuhei Kato, Satosho Saikatsu, Akira Yasuda, Michitaka Yoshino.
Engineering Research & Faculty of science and Engineering Course
Hosei University, 3-7-2, Kajino-cho, Koganei-shi, Tokyo 184-8584, Japan
AbstractThis paper describes a method for reducing the influence of the mismatch
between the I and Q paths in a complex bandpass modulator. The disadvantage of
such modulators is SNR deterioration due to aliasing of image band noise when a
mismatch exists between I and Q paths. This situation can be improved by adding a new
notch filter to reduce the image band noise. Consequently, a bandpass error feedback
structure is proposed here to add the new notch to an image signal band. This structure
can produce a new notch in the desired signal band and image signal band. Therefore,
this structure not only reduces the influence of the mismatch but also strengthens the
noise-shaping characteristic in the desired signal band. The effectiveness of this
structure is confirmed by a simulation using MATLAB with Simulink.

13

10042
A Constant-gm Rail-to-Rail Operational Amplifier with Low-gain
Variation and It's Analysis
Nobuyuki Yokoyama, Cong-Kha Pham.
Dept. of Engineering Science
The University of Electro-Communications (UEC), Chofu,Japan
Abstract A constant-gm Rail-to-Rail Operational Amplifier with Low-gain Variation is
introduced in this paper. The input stage is based on the dynamic current scaling
technique, and the output stage with feed-forward class-AB output circuit. The dynamic
current scaling technique is proposed as scales the output signal currents of the input
differential pairs dynamically for a constant-gm while keeping tail currents of the input
transistors unchanged. To obtain low gain variation, the feed-forward class-AB output
circuit is added. This proposed Op Amp's configuration suppresses the change of gain
and phase margin over the entire common-mode input range. Moreover, gain,
commonmode rejection ratio (CMRR) and power-supply rejection ratio (PSRR) are
clarified by the equivalent circuit of the proposed circuit. The rail-to-rail Op Amp is
designed with 5V of supply voltage in 1.2um CMOS technology, and simulated by Hspice. The Op Amp has 88 dB gain, 5.3-MHZ bandwidth (PM=71) at 10pF and 100k
output load. Simulations show that, when the input common-mode voltage swings from
rail-to-rail, the OpAmp's input stage gm varies within 7.8%, the output stage gm varies
within 3% and gain varies within 0.6 dB. When simulated values and calculated values
are compared by each of gain, CMRR and PSRR, it is recognized that each equivalent
circuit is clarified.

10043
A Linearity Optimization Method for CMOS R-2R Ladder Network
Yuta Kato, Cong-Kha Pham.
Dept. of Engineering Science
The University of Electro-Communications (UEC), Chofu,Japan
AbstractThis paper presents a optimization method of a linearity for CMOS only R-2R
ladder network. This new approach significantly reduces the integral non-linearity (INL)
and differential non-linearity (DNL) of R-2R ladder by adjusting channel width W for
reducing current mismatch on each node of a bit cell. 8-bit R-2R ladder have been
optimized in BSIM3v3 level 53 (0.18um) model on a circuit simulator in which channel
length L is vaned from 0.18um to 10.0um. The INL value was reduced from 4LSB to
0.4LSB and the DNL value was reduced from 6LSB to 0.7LSB in case which L is
0.18um and initial W is 1.44um. The optimized results and other specifications are
presented and the limitations are discussed.

14

10044
Two-Path Delay Line Based Quadrature Band-Pass Modulator
Nithin Kumar Y.B., Edoardo Bonizzoni, Amit Patray, Franco Maloberti.
Department of Electronics, University of Pavia, Via Ferrata, 1 - 27100 Pavia - ITALY
Department of Electrical and Electronics, IIT Kharagpur - INDIA
Abstract This paper presents a new concept for an efective quadrature band-pass
modulator and discusses the high level implementation for a third order two-path
scheme based on delay line. The methodology uses an architecture which locks IF
frequencies to the sampling frequency. Robustness of the structure against the
mismatch is analyzed. Simulations at the behavioural level verify the architecture
implementation which uses a novel switched capacitor scheme. Index TermsAnalogto-Digital conversion, band-pass modulation, complex filters.

10046
Active Inductor Design using Distortion Reduction Technique
Takahide Sato, Toshihiro Ito.
University of Yamanashi
Interdisciplinary Graduate School of Medicine and Engineering
AbstractThis paper proposes a distortion reduction technique for active inductors.
Bias current of a MOSFET, which acts as transconductor, is controlled to reduce a
distortion of a active inductor. When a input voltage swing of the MOSFET increases, its
bias currents is decreased by a control circuit. As a result of this control,
transconductance of the MOSFET remains constant. An active inductor using this
technique is free from distortion caused by transconductance of a MOSFET. The
proposed technique is applied to two basic conventional active inductors and novel low
distortion active inductors are derived. HSPICE simulations show that distortion of the
proposed active inductor is very low. One of the proposed low distortion active inductors
is applied to a 2nd order bandpass filter. Thanks to the proposed technique, the total
harmonic distortion of the bandpass filter becomes 0.26% at 1 GHz.

10047
Design of Wide Gain Range CMOS VGA for WLAN Receiver
Laksono Widyo Isworo
Kyushu Institute of Technology
Cosy Muto
Nagasaki University

Hiroshi Ochi
Radrix Co. Ltd
Hiroshi Tanimoto
Kitami Institute of Technology

AbstractA design of variable gain amplifier (VGA) for WLAN 802.11 a/b/g receiver has
been reported. The proposed VGA which is designed in 0.18 m CMOS technology under
1.8 V supply voltage has about 70 dB gain range which varies from 0 to 70 dB over 16
MHz bandwidth. This wide gain range is achieved in coarse and fine gain scheme by
combining and controlling digitally high gain amplifiers and a dB-linear gain amplifier
which is driven by a novel pseudo-exponential function generator.

15

Author Index
Akira Hyogo ........................................................................................................5, 6, 7
Akira Yasuda ......................................................................................................12, 13
Amit Patra ................................................................................................................15
Amy Hamidah Salman ...............................................................................................4
Andyes Fourman Duta Akbar Sudirdja ....................................................................4
Annisa Karima ...........................................................................................................3
Antaryami Panigrahi .................................................................................................2
Ardimas Andi Purwita ..............................................................................................10
Bin Shao ......................................................................................................................2
Changquan Jin ...........................................................................................................3
Cong-Kha Pham .......................................................................................................14
Cosy Muto .................................................................................................................15
Dai Ichihoshi ...............................................................................................................6
Dai Miyauchi ..............................................................................................................7
Edoardo Bonizzoni ....................................................................................................15
Eiichi Sano ..................................................................................................................5
Franco Maloberti ......................................................................................................15
Fujihiko Matsumoto ...............................................................................................7, 9
Hao San .................................................................................................................2, 13
Haruo Kobayashi ....................................................................................................4, 7
Hiromichi Matsushita ................................................................................................5
Hiroshi Ochi ..............................................................................................................15
Hiroshi Tanimoto ......................................................................................................15
Isao Akiyama ..............................................................................................................4
Isao Nakanishi ............................................................................................................7
Jiani Ye .......................................................................................................................4
Junichi Fujitsuka .....................................................................................................12
Junichi Matsuda .........................................................................................................7
Kawori Sekine ...........................................................................................................12
Kazuhiro Takahagi .....................................................................................................5
Kazuyuki Wada ...........................................................................................................3
Kazuyuki Wakabayashi .............................................................................................4
Keisuke Kato ...............................................................................................................4
Keitaro Sekine ........................................................................................................6, 7
Kenji Nemoto ..............................................................................................................7
Kiichi Niitsu ............................................................................................................4, 7
Laksono Widyo Isworo .............................................................................................15
Lee Jun Gyu ..............................................................................................................11
Masao Hotta ..........................................................................................................2, 13
Masayuki Ikebe ..........................................................................................................5
Michitaka Yoshino ..............................................................................................12, 13
Mohd Hairi ..................................................................................................................8
Nana Sutisna ..............................................................................................................3
Naoki Tsukahara ........................................................................................................6
Nicodimus Retdian .....................................................................................................8

16

Author Index
Nithin Kumar Y.B. ...................................................................................................15
Nobukazu Takai .....................................................................................................4, 7
Nobuyuki Yokoyama ................................................................................................14
Osamu Yamamoto ......................................................................................................4
Prashanta Kumar Paul ..............................................................................................2
Rakhmad Syafutra Lubis ..........................................................................................9
Renyuan Zhang .........................................................................................................11
Ryutaro Sugimoto .......................................................................................................9
Satoshi Saikatsu ......................................................................................................13
Shigetaka Takagi .......................................................................................................8
Shintaro Tanaka .........................................................................................................6
Shuhei Kato ..............................................................................................................13
Shoichi Masui ...........................................................................................................11
Tadashi Shibata ....................................................................................................5, 11
Takahide Sato
....................................................................................................15
Takahiro Odaguchi .....................................................................................................7
Takao Ootsuki .............................................................................................................4
Takemasa Komori .......................................................................................................5
Takeshi Ohbuchi .....................................................................................................7, 9
Takeshi Oomori ...........................................................................................................7
Takeshi Shima ..........................................................................................................10
Takumi Ikegami ........................................................................................................10
Takuya Yagi .................................................................................................................4
Tomoki Iida .................................................................................................................5
Tomomi Abe .................................................................................................................9
Tomonari Kato ............................................................................................................2
Toshihiro Ito ..............................................................................................................15
Trio Adiono ............................................................................................................3, 10
Tsubasa Maruyama ..............................................................................................2, 13
Yasuaki Inoue .............................................................................................................3
Yasunori Kobori ..........................................................................................................7
Yoshihito Amemiya .....................................................................................................5
Yuki Kimura .............................................................................................................12
Yuta Kato ..................................................................................................................14
Zachary Nosker ......................................................................................................4, 7
Zulfiqar Ali Abdul Aziz ...............................................................................................8
Zhangcai Huang .........................................................................................................3
Zhao Chen ...................................................................................................................3