IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society

SWITCHING REGULATOR WITH DYNAMICALLY ADJUSTABLE

SUPPLY VOLTAGE FOR LOW POWER VLSI
Sandeep Dhar and Dragan Maksimovic
Colorado Power Electronics Center
Department of Electrical and Computer Engineering
University of Colorado, Boulder, CO 80309-0425, dhar,maksimov @colorado.edu

Abstract The paper describes a switching regulator system

for adaptive voltage scaling (AVS) where the supply voltage to a digital VLSI chip is dynamically adjusted to the
minimum value required for the desired system speed. The
control loop includes a variable-frequency Watkins-Johnson
switching DC-DC converter and a model of the critical path
delay of the application. Simple bang-bang control of the
critical path delay allows fast transient response to step
changes in speed, and stable operation over a very wide
range of system clock frequencies. A chip including the AVS
controller and a small digital application has been fabricated
in a standard CMOS process. Experimental results demonstrate operation over the application clock frequency range
from 10 kHz to 20 MHz, and a 12 s transient response for a
step change in speed from standby to maximum throughput
operation.


1. Introduction
The strong demand for low-power computing has been driven
by a growing class of portable, battery-operated applications
that demand ever increasing functionalities with low-power consumption. The power consumption is also a limiting factor in
integrating more transistors in VLSI chips for portable applications. The resulting heat dissipation also limits the feasible
packaging and performance of the VLSI chip and system. Because of the quadratic dependence of power consumption on the
supply voltage [11], reducing the supply voltage level is an effective way to reduce power consumption. However lower supply voltage, for a given technology leads to increased gate delay
and as a result the application has to be operated at a reduced
clock rate.
More recently, adaptive (or dynamic) voltage scaling (AVS)
has been proposed as an effective power management technique
where the system supply voltage and the clock frequency of a
digital VLSI application are dynamically adjusted to meet the
application throughput requirements [1]-[8]. By reducing the
supply voltage and application clock frequency, adaptive voltage
scaling offers, in principle, superior power savings compared to
simple on/off power management. Successful applications have
included digital signal processing systems [1]-[5], I/O interface
[6], and general-purpose microprocessor [7, 8].
At the system level, AVS requires a voltage/frequency scheduler that can intelligently vary the speed depending on the application requirements [7, 8]. At the hardware implementation
level, the key AVS component is a controller that can automatically generate the minimum voltage required for the desired
speed. Desirable features of an AVS controller include [8]-[10]:
high efficiency of the power converter used to generate the variable supply voltage; ability to make voltage adjustments over

0-7803-7108-9/01/$10.00 (C)2001 IEEE

VDD
VDD

VDDmax
VDD min

critical path
delay
System clock period

td

t
safety margin

tdmax
t dmin

Figure 1: Supply voltage and critical path delay waveforms illustrating

steady state operation of the bang-bang delay controller.

a very wide range of clock frequencies to accommodate processing speeds from stand-by to maximum throughput; stable
and fast transient response to minimize latency and losses when
switching between different speed levels.
Voltage regulation systems for adaptive voltage scaling include
frequency locked loop (FLL) based scheme [8], phase locked
loop (PLL) based scheme [2, 9], and a delay-line based speed
detector [3, 5]. In these approaches, the control loop design
requires a careful compromise between the loop stability and
dynamic response times [2, 8, 9] or multiple test clock cycles needed [3, 5]. In addition, the capture range of PLL or
FLL based schemes may limit the achievable range of operating system clock frequencies. Also, since the system clock in
a PLL/FLL scheme is generated by a VCO operating from the
supply voltage [2, 8, 9], the system clock suffers from variable
clock jitter due to supply voltage noise.
The contribution of this paper is to introduce the theory and
concept of a simple digital control scheme for AVS based on
the bang-bang control method. The controlled variable is the
critical path delay of the application. This variable is forced
to be between the limits that correspond to the supply voltage
value being close to the minimum required for the desired system clock frequency. The bang-bang delay control method effectively removes the stability concerns, and allows fast transient response and operation over a very wide range of clock
frequencies. Furthermore, since the system clock and supply
voltage are generated independently, system clock jitter can be
effectively reduced.
This paper is organized as follows. The proposed AVS controller is described in Section 2. Design of the power converter
embedded in the control loop is given in Section 3. Simulation results of the proposed scheme and experimental results obtained from a fabricated chip that combines the AVS controller
and a simple test application are presented in Section 4 followed
by conclusions in Section 5.

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IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society
C PREC

SECTION 1

C TEST

SECTION 2

CRITITCAL PATH MODEL

SAFETY MARGIN

HIGH VDD DETECT

DELAY RIPPLE

D E L A Y - L I N E

Extclk CLOCK C
PREC

CPREC


LOGIC



CTEST

VDD

LEVEL
SHIFTER

CSysclk

LEVEL
SHIFTER

DATAL

DDH

LEVEL
SHIFTER

LEVEL
SHIFTER
DATA1

DATA2

in

delay
cell S

delay
cell 2

delay
cell 1

out

in

out

in

APPLICATION

out

delay
cell N+K

in

in

out

out

DDH

VDDH

DDH

DATAL

DATA2

QL3

C TEST

Figure 2: Block diagram of the AVS scheme. Unless otherwise shown,

as the supply voltage.
all blocks use


out

delay
cell N+ N

CPREC

CONT_DIS

DRIVERS

in

VDDH

DATAH

CONTROL LOGIC

CONT_OUT

delay
cell N+1

out

in

CPREC

CONT_IN

SWITCH-MODE
POWER
CONVERTER

delay
cell N

DATA1

QL2

DATAH

QL1

QL4

Figure 3: Block diagram of the delay-line consisting of delay-cells

and level shifters to obtain the DATAi logic signals. All delay-cells use
.
supply voltage


2. Delay Controller for AVS

ripple
. The remaining
cells are
used to detect the condition when the supply voltage is too high
for the application.
Operation of the delay-line is understood by referring to the
device level schematic of the delay-cell shown in Fig. 4(a) and
the clock waveforms of Fig. 4(b). When the precharge clock
is at logic 0, devices
and
precharge the nodes
and to logic 1 (i.e.
), and 0, respectively. When the
test clock
is at logic 1, the test signal propagates from
to
via devices
and
. For the first cell in the delay
is also connected to
. For the
line, the input node
remaining cells, the node
is connected to the node
.
Referring to Fig. 3, signal taps are taken from the delay-cells
,
,
, and
and are level-shifted to be
compatible with the control logic that operates from
sup, and result in the nodes
ply. These signals drive the devices
DATAi being pulled to logic 0 if
does propagate through
the delay-line within the test period. In the desired steady state
is sufficient for
to propagate through
operation,
cell
but not high enough for it to propagate through cell
.
2.2 Modeling the critical path
It has been shown that the delay of a simple logic gate can
be used to accurately represent the delay in more complicated
structures [8]. Therefore, the delay-line consisting of the cells
shown in Fig. 4(a) can be used to model the critical path of an
application. Modeling the critical path is based on testing the
application at a process corner which allows the application to
work at its maximum speed under worst-case input data condi*

The AVS controller we propose is based on regulating the critical path delay within an application by changing the supply voltage
. Conceptual operation of such a scheme is illustrated
by the waveforms in Fig. 1. Given a certain operating clock frea change of
within the
quency of the application
limits
and
results in the critical path delay
changing in some nonlinear fashion between the limits
and
.
The bang-bang control of the delay operates as follows: when
, a control sigthe critical path delay hits the upper limit
nal is activated to increase the supply voltage
; when the
, the control is deactivated in
delay reaches the lower limit
order to reduce the supply voltage. As long as time variations
in
are monotonic (increasing or decreasing depending on
, the
the control signal), and is a monotonic function of
control loop is stable and the transient response is determined
by the system open-loop response.
Fig. 2 shows a block diagram of the proposed AVS controller.
It consists of five parts:
(1) a variable-frequency switch-mode DC-DC converter that
takes
as the input voltage, and produces the supply voltage
for the application;
(2) a delay-line which operates from supply voltage
and
and the precharge clocks
is driven by the test clock
and
at the desired system clock frequency for
the application;
(3) level shifters that convert the test signal voltages taken from
various taps across the delay-line to voltage levels compatible
with the control logic;
(4) a control logic that closes the loop and is updated every
falling edge of
;
(5) additional logic needed to generate the test clock
which is non-overlapping with the precharge clocks,
and
(Fig.4), and the system clock.


'

'

'

'

VDD

M1

C PREC

2.1 Delay Line Description

The delay-line in the AVS controller is made up of several identical cells grouped in two sections as shown in Fig. 3. The first
section consists of cells that model half the critical path delay
of the application (referred to in this paper as the critical path
model) plus a small safety margin. The next section consists of
cells. The first part consists of
cells that model the delay

M2

in

M4

C PREC

C PREC

C PREC

cell i

(b)

(a)

Figure 4: (a) Device level schematic of the delay-cell used in the

delay-line and (b) the relation of the test clock
and
.
clocks,
d

0-7803-7108-9/01/$10.00 (C)2001 IEEE

out

C TEST

M3

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to the precharge

IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society
DATA2
CONT_IN

DATA1

D2

CTEST

CONT_OUT
4

CONT_DIS

DATAH

1
D
VDDH
CONT_IN 1

CTEST

Figure 5: Implementation of the control logic to generate

devices are assumed to be operating at supply voltage


"

"

"

'

Fig. 5 shows the implementation of the control logic that takes

as inputs the level-shifted delay-line taps DATA2, DATA1, and
DATAH and outputs the control signals for the power converter
switches. As explained in Sec. 2.1, a logic 1 on the input DATAi
implies that the test clock could not propagate to DATAi within
the test clock period. For the outputs, a logic 1 value turns on a
power converter switch. These signals are explained below with
(1,1,1)
(0,1,1)

(0,0,0)

ON

ON

(0,0,1)
(0,0,0)

OFF

(0,0,0)
(0,0,1)
(0,1,1)
CONT_IN

APPLICATION

VDD

Figure 7: modified Watkins Johnson (WJ) converter used in the

AVS scheme
reference to the modified Watkins-Johnson converter shown in
Fig. 7;
CONT IN : controls the input side switch . When turned on,
the switch connects
to the converter network.
CONT OUT : controls the output side switch . When turned
on, the switch allows the charging or discharging of the output
capacitor through the converter.
CONT DIS : controls the output discharge switch
. When
turned on in conjunction with
it allows the capacitor to discharge through the inductor.
Fig. 6 shows the state diagram for the control outputs CONT IN
and CONT DIS. Control output CONT OUT is the logic sum
of these control signals. For example in steady state the inputs
(DATA2, DATA1, DATAH) are at logic values (0,1,1) which
implies that
is sufficient for the test clock to propagate
through the critical path model consisting of
cells, but not
enough to propagate through the additional delay ripple of
cells. Depending on the previous state of the converter switch
and the supply voltage limit (
or
) reached the
power converter switches are turned on or off.
)

(0,0,0)

(0,0,1)

OFF

(0,0,1)
(0,1,1)
(1,1,1)
CONT_DIS

External inputs are (DATA2, DATA1, DATAH)

Figure 6: State diagram showing state of the converter power switches

controlled by (a) CONT IN and (b) CONT DIS. The arcs are labeled
with valid input combinations

0-7803-7108-9/01/$10.00 (C)2001 IEEE

2.3 Control Logic

(1,1,1)

. All

CONT_DIS
3

"

tions, i.e., at the maximum supply voltage, and at the maximum

. The delay-cell is then designed
clock frequency
using the model parameters for that process corner. Next, the
delay-line length
is selected such that the test clock at
the maximum system clock frequency is just able to propagate
through this length when the supply voltage to the delay-line
can be altered by
has the maximum value. The length
choice of the device sizes in the delay-cell design. This choice
as explained in Sec.
also affects the output voltage ripple
3.2.
Since the test takes one half of the test clock period (i.e. when
is at logic 1), the critical path model effectively captures
half of the application worst-case critical path delay. With the
delay-line fabricated on the same chip as the application, the
delay-line characteristics scale with the application for voltage,
process or temperature variations.
value, the
It should be noted that for proper testing of the
must have a 50% duty cycle. Instead of placing
clock
this responsibility on the external clock, in our scheme the test
clock and the system clock are obtained by dividing an external
) by 2.
clock (at
!

CONT_OUT

3. Variable-Frequency Switching Converter

While any step-down switch-mode power converter should suffice, a desirable property of the power converter is that in steady
state operation the output voltage should start increasing when
the control signal CONT OUT is logic 1, and start decreasing
when CONT OUT is logic 0. This allows for a simple, stable
bang-bang control of the delay and therefore of the output voltage ripple.
The switching converter we selected for the AVS controller
(Fig. 7) is a modification of the Watkins-Johnson (WJ) converter
[12]. The WJ converter has the desirable property that the output voltage will always decrease when the converter switches
are turned off as compared to a standard step-down (buck) converter.
The WJ converter is operated in the discontinuous conduction
mode (DCM) in steady state. In this mode of operation the conand
turn on for short durations of time.
verter switches
The inductor current is discontinuous and is zero at the end of
the converter switching period.
)

3.1 Dynamic response to step changes in clock frequency.

3.1.1 Step change from low

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$


to high


$


IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society
L

iL
iC

vDDH

iL

i 0

iC

vDD

Consequently the converter switching frequency

given as,

vDD

(b)

where

Figure 8: LC networks used to model the transient response of

the converter to step changes in frequency, (a) for a step change
and (b) a step change from high to low
from low to high








To minimize latency and/or additional losses, it is desirable to

have fast transient response to step changes in clock frequency.
The converter and the controller transient response to a step
is determined by a simple openchange from low to high
loop model shown in Fig. 8(a). We assume that the converter
operates in DCM so that initially the inductor current is zero.
is too low
During this voltage transient the supply voltage
for the application and the the system clock
is disabled.
During this time, the application consumes almost no current
0) . As a result,
=
during the transient. The
(
capacitor voltage
is at some initial value
.
, the switches
and
are closed and voltage
At
is applied across the terminals of the network. We are interested in the time taken for the capacitor voltage to reach a value
. This can be found by solving the differential
equations for the network, resulting in



!

%


(1)







is the power consumption of the application. However

depends on the delay-line parameters ( and
) and
. This dependence can be found as follows:
the delay through the critiAt its valley voltage value
cal path model is given as,
3


#







(5)



6

is the delay through a delay-cell and is a function of

where
, i.e.
.
At its peak voltage value
the delay through the delayline is







#

(6)


6


, they are
Since these delays represent the test portion of
equal. Equating the two sides and simplifying by keeping only
the linear terms in the Taylor expansion gives us
:

0
6

(7)

Furthermore, the relation between

by a curve-fit to be approximated as,

"

and

(4)
*

can be


(a)



was obtained


<
<

A


to low
3.1.2 Step change from high
Similarly the converter transient response to a step change from
high to low
is determined by the simple open-loop
model shown in Fig. 8(b). The inductor current is initially zero.
and is discharging
The capacitor is at some initial voltage
with load current .
At
, the switches
and
close and the capacitor additionally discharges through the inductor. Once again we are
interested in the time take for the capacitor voltage to reach a
. For simplicity we can ignore the load
value
current giving us the solution,


>

(8)




Taking the derivative and substituting in (7) we have,

(9)









(2)




"

As

increases so does
. The delay-line parameters
and
can thus be set to limit the output voltage ripple at
the maximum supply voltage. The output voltage ripple is not
determined by the converter parameters, which is an advantage
of the scheme since it allows for straightforward design of the
WJ converter.
To a first order the power consumption of the application is,

The actual transient time is less than (2) since it includes the capacitor discharge through the load. Equations (1) and (2) show
.
that the transient responses are of the order of
3.2 Converter Switching Frequency
In steady-state (DCM) operation, the converter switches turn
on for a short time interval
charging the capacitor
to
, followed by a longer period
over which discharges to
. Under this assumption the capacitor charging time period can be ignored and the switching period of the
equals
.
converter

(10)


H

where
yields

is a constant. Substituting for

H

and
*

in (4)

6
H

(11)







Since the test period is also one-half of the system clock period,
can be related to
using (8),

>


!

(3)


<

0-7803-7108-9/01/$10.00 (C)2001 IEEE

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(12)

IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society
IMPLEMENTED ON CHIP
Extclk

CLOCK
LOGIC

precharge
and test
clocks

D E L A Y

L I N E


LEVEL
SHIFTER

Sysclk

LEVEL
SHIFTER

DATA2

6 X 6 MULTIPLIER
WITH OUTPUT
REGISTER

DATA1

CONTROL LOGIC

D2
Q P1

QP2

D1

CONT_IN

DDH

VDD

DRIVER

Figure 9: Block diagram of fabricated chip with external WJ converter

providing AVS of a 6x6 multiplier with registered outputs.

Figure 10: Die photo of chip implementing AVS controller for the test
application

Substituting in (11) gives us,

3

VDD [V]










This relation implies that the converter switching frequency in(and

). This is desirable, because it
creases with
implies that the converter switching frequency scales with the
system clock frequency. As a result, switching losses in the
converter also scale with application load power, and the converter can maintain relatively high efficiency over a wide range
of operating conditions.
3.3 Selection of Converter Components and
As described by (1), (2) and (13),
is inversely proportional
to and the transient responses are of the order of
. Hence
can be selected to set the switching frequency. It is desirable
to have a small
so that the transient response is faster and
the losses in transient are smaller. However a higher switching
frequency also results in higher switching losses [12] which reduces the steady-state power efficiency of the converter. Using
can be inferred from power consumption of the ap(10),
and
.
and
have
plication for the measured
already been selected to limit the output voltage ripple. Hence
can be selected to set the maximum switching frequency at
the maximum supply voltage. Once has been selected, is
selected to adjust the transient response time. How short the
transient response can be is constrained only by the ability of
power switches to conduct increased peak inductor current and
the conduction losses in the converter switches.


2.5

(13)

2
1.5

1
0.5
0
0.01

0.1

10

100

[MHz]

Extclk

Figure 11: Plot of




as a function of
for a test where
was adaptively scaled to its minimum value for operation at the given
is varied from 20KHz to 40MHz.
system clock frequency.
"

"

parameters used in the typical process corner model were then

used to design the critical path model of the delay-line, with
appropriate sizing of the devices in the delay-cell such that for
a test clock pulse at
delay line length
20MHz and
= 2.8 V is just able to propagate to the levelshifted tap DATA2. With these parameters the maximum
is about 150
at 2.8 (cf. equation 7).
A test circuit for AVS of the multiplier was designed with a WJ
converter closing the loop externally as shown in the block diagram representation (Fig. 9). The delay-line for the fabricated


700

P [ mW]

600
500

The entire scheme except for external and was designed in

a standard CMOS process and extensive Spice simulations were
performed.
A chip implementing the AVS controller was designed in a 1.5
standard CMOS process available through MOSIS (Fig. 10).
The area taken by the AVS controller including pads is 0.88
. The chip also contains a 6x6 array multiplier which was
used as a test application for the controller. The outputs of the
multiplier are registered and are updated at the rising edge of
the system clock. A model extracted from layout of the multiplier was simulated at the typical process corner to determine
that under worst-case input data, and at an operating frequency
of 20MHz, the multiplier requires a supply voltage of 2.8 . The

VDD = const (a)

400

300

AVS,
application only (b)

200

100

AVS, including
DC-DC converter (c)

0-7803-7108-9/01/$10.00 (C)2001 IEEE

4. Simulation and Experimental Results

10

20

Extclk

30

40

[MHz]

Figure 12: Comparison of measured power consumption for different

= 3 V, constant, (b) AVS with
schemes. From top to bottom, (a)
power consumption on-chip only and (c) including the power consumption in the WJ-converter.


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IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society
1

0.9
0.8
0.7
0.6
0.5
0.4
0.3

10

30

20
f Extclk [MHz]

40

Figure 13: Measured power efficiency of WJ-converter as a function

of

when used in the closed loop AVS scheme.



chip does not include the delay-cells to detect high

and
the capacitor is
during a step change from high to low
simply allowed to discharge to the lower supply voltage value.
From power consumption measurements of the multiplier,
was estimated to be about 4 pF. It was desired to have a converter
switching frequency about 50 kHz at the maximum supply voltage. = 47 nF was selected by substituting for values in (13).
Also, it was desired to have a worst case transient response
15 s for a step change from the lowest system clock frequency
(10 kHz,
= 0.8 V) to the highest system clock frequency
(20 MHz,
= 2.8 V). Using (1), was selected to be 750
H.
A plot of
as a function of
is shown in Fig. 11. It
over a very
is observed that the control loop provides the
wide range of
, which is an advantage of the proposed
controller. It is possible to realize very low power stand-by operation at very low clock frequency, and the supply voltage close
to the threshold voltage of the devices. Fig. 12 shows the mea, of the AVS
sured power consumption as a function of
application compared to fixed
operation. For illustration,
both the power consumption excluding the converter and including the converter losses are shown. The power levels in Fig. 12
are low due to the small complexity of the multiplier application.
The power efficiency, of the WJ converter over this range of
frequencies is given in Fig. 13. Due to low output power levels
of the converter, the converter losses become significant only at
very low frequencies, resulting in low .
A second test was designed to demonstrate the fast transient
response of the control loop from the lowest operating supply
voltage to the maximum supply voltage. Two external clock
= 20 kHz and
= 40MHz were applied
frequencies
to a switch that alternated between the two frequencies. Details
of this transient response around the vicinity of the step change
= 0.8
in frequency are seen in Fig. 14. The transient from
V to
= 2.8 V takes about 12 , which compares favorably
to the results reported in earlier publications [3, 5, 7, 8, 10].


, control signal CONT IN, and

for the transient time period for a step change in
inductor current
from 20 kHz to 40 MHz.

tency. The Watkins-Johnson converter is shown to be well suited

for closed loop delay-line regulation. The design criteria for the
selection of the converter components is straightforward and is
described. A chip including the AVS controller and a small test
application has been fabricated in a standard CMOS process.
Experimental results demonstrate operation over the clock frequency range from 10KHz to 20MHz, and a 12 s transient response for a step change in system clock frequency from 10 kHz
to 20 Mhz.


References

Figure 14: Plot of supply voltage

5. Conclusions
Adaptive voltage scaling (AVS) of a supply voltage is emerging
as an effective power management technique for digital VLSI
applications. The paper describes a delay-line based regulation
scheme which is simple to implement and allows fast transient
response to step changes in speed, and stable operation over a
very wide range of system clock frequencies. The delay is measured at the system clock rate, which minimizes the system la-

0-7803-7108-9/01/$10.00 (C)2001 IEEE

[1] L. Nielsen, C. Niessen, J. Sparso, K. Van Berkel,Low-power operation using self-timed circuits and adaptive scaling of the supply voltage, IEEE Trans. on VLSI Systems, vol.2, pp. 391-397,
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[5] T. Kuroda et. al., Variable Supply-Voltage Scheme with
95% Efficiency DC-DC converter for MPEG-4 codec, Proc.
ISLPED99, pp. 54-59
[6] G. Wei et. al.,A variable-frequency parallel I/O interface with
adaptive power supply regulation, IEEE Solid-State Circuits
Conference, pp. 298-299, Feb. 2000.
[7] Transmeta Breaks X86 Low-Power Barrier, Microprocessor Report, Feb. 2000.
[8] T. D. Burd, T. A. Pering, A. J. Stratakos, R. W. Brodersen, A
Dynamic Voltage Scaled Microprocessor System, IEEE J. SolidState Circuits, Vol. 35, No. 11, Nov. 2000, pp. 1571-1579.
[9] V. Gutnik, A. Chandrakasan, An Efficient Controller for Variable Supply-Voltage Low Power Processing, 1996 Symposium
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[10] V. Gutnik, A. Chandrakasan, Embedded Power Supply for LowPower DSP, IEEE Transactions on VLSI Systems, vol. 5, No. 4.
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[11] A. Chandrakasan, S. Sheng, R. Broderson, Low-power CMOS
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