336

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 3, MAY 2001

Engineering Design of Lossless Passive Soft

Switching Methods for PWM ConvertersPart I:
With Minimum Voltage Stress Circuit Cells
K. Mark Smith, Jr., Member, IEEE, and Keyue Ma Smedley, Senior Member, IEEE

TABLE I
SOFT SWITCHING CIRCUIT CELLS

AbstractThis paper presents the analysis and design methodology of lossless passive soft switching converters from an engineering perspective. The circuit operation and soft switching loss
analysis are detailed and an intuitive procedure is derived that enables quick and accurate design. Analysis is given for a set of soft
switching circuit cells with minimum switch voltage stress used to
synthesize a family of soft switching converters. The design is based
on minimizing switching losses while maintaining soft switching
over the desired operating range. A new simple loss model is derived to optimize the values of the resonant components for a particular design. As an example of the design procedure, a PFC boost
converter is designed and tested.
Index TermsPassive lossless snubber, PWM converter, soft
switching.

I. INTRODUCTION
O REDUCE the switching losses in high frequency converters, many lossless passive soft switching methods have
been proposed in the literature ([1][4] show several examples).
They use resonant inductors, capacitors, and diodes to provide
soft turn-on and turn-off of the switches. Since these elements
have lower failure rates as compared to methods that use active
elements [i.e., metal oxide semiconductor field effect transistors
(MOSFETS)], their reliability is inherently higher. Although,
there are many different circuits that provide lossless passive
soft switching, they can be characterized by a set of properties
as proposed in [5], [14]. With these properties, the operation of
the circuits can be easily understood and new circuits can be created for specific applications [5], [6], [14], [15]. In [5] and [14],
a set of circuit cells was proposed that gives a synthesis procedure for the creation of a family of soft switching converters.
These circuit cells can be categorized into two groups with different characteristics. One group maintains the same voltage
stress across the active switch as the original hard-switched converter and is called the minimum voltage stress (MVS) circuit
cells (Table I. Cells I, II). The other group allows an over-voltage
stress on the main switch and is called nonminimum voltage
stress (non-MVS) circuit cells (Table I. Cells III, IV, V, VI). Beside the over-voltage stress characteristic, each group has its
own pros and cons.
Soft switching of the main switch is achieved using these cells
by the appropriate insertion of a resonant inductor and capacitor

Manuscript received March 30, 1998; revised November 28, 2000. Recommended by Associate Editor F. D. Tan.
The authors are with the University of California, Irvine, CA 92697 USA
(e-mail: smedley@uci.edu).
Publisher Item Identifier S 0885-8993(01)04032-7.

into the original hard switching converter. The small resonant

inductor provides zero current turn on of the main switch and
the small resonant capacitor provides zero voltage turn off. In
addition, the cells also use other diodes, inductors and capacitors to recover the energy stored in the resonant inductor and
capacitor elements.
To minimize switching losses over the complete operating
range, the optimum design of soft switching converters is only
possible with a compromise between opposing requirements.
For instance, the larger the resonant inductor and capacitor are,
the lower the switching losses. Therefore, one important objective is to make these elements large. However, these resonant elements will also require time to slow the switch current
and voltage and to reset their energy. This will decrease the
usable operating range where soft switching is achieved. The
second opposing constraint is to reduce these elements to preserve a wide soft switching operating range. A model for the soft
switching losses will quantify the optimum balance between the
design objectives.
This paper proposes the analysis and design methodology of
lossless passive soft switching converters from an engineering
perspective. The circuit operation and soft switching loss
analysis are detailed and a simple design procedure is derived
that will provide quick and accurate results. Analysis is given

08858993/01$10.00 2001 IEEE

SMITH AND SMEDLEY: LOSSLESS PASSIVE SOFT SWITCHING METHODS FOR PWM CONVERTERS

in this paper for the minimum voltage stress circuit cells.

The nonminimum voltage stress circuit cells are analyzed in
[7]. The cell equations are given irrespective to their final
placement in a particular converter. This allows the equations
to be used for any PWM converter with the cell inserted. The
turn-on and turn-off losses in a MOSFET switch are described.
A new simple loss model is derived and used to optimize the
design values of the resonant components. The general design
procedure ensures nearly minimum switching losses while
providing soft switching over the required load range. These
soft switching methods also work well for IGBT switches and
therefore the circuit analysis is identical. However, because the
loss models are different, the optimized design procedures are
modified and will be the topic of a future paper.
The paper is divided such that Section II analyzes the minimum voltage stress circuit cells with respect to a new boost converter. Section III derives a loss model for the MOSFET switch
and determines minimized values of the resonant inductor and
capacitor. Section IV discusses the design procedure. Section V
shows a PFC design example. After the Conclusion, an Appendix contains the circuit equations for the analyzed circuit
cells.
II. ANALYSIS OF PASSIVE SOFT SWITCHING CIRCUIT CELLS
The different cell categories in Table I are distinguished by
the circuitry used to recover the energy from the elements that
provide soft turn on ( ) and soft turn off ( ) of the switch.
and
with a relaThe MVS cells manage the energy in
(i.e., 0.010.1 F). The energy in
tively small capacitor
is completely transferred to the input or output each switching
period. The non-MVS cells manage this energy with a large ca(i.e., 15 H) and an inductor . For these circuits,
pacitor
will maintain an average voltage between switching cycles
that ensures the energy flowing in and out of the capacitor is
equal.
Different applications will determine which cells in Table I
are most suitable. The MVS cells minimize the voltage stress
is
across the main switch. They use fewer components,
smaller, and only one inductor is needed. However, their soft
switching range can be limited compared to the non-MVS cells.
Converters that use these cells have shown excellent results
[3], [4] with results that rival more expensive active methods
[8]. The non-MVS cells add stress to the main switch, but in
and
,
comparison to Cells I and II, with the same size
their soft switching range is substantially extended. They have
shown better efficiency than the MVS cells markedly at low
power levels [7]. Therefore, these cells are the choice when
minimized losses and low EMI are necessary over a wider
operating range.
Fig. 1 shows several examples of how the cells can be used in
PWM converters. As described in [5], [14], the cells are placed
in a PWM converter after the basic soft switching topology is
chosen. In Fig. 1 there are three boost converters representing
three of the ten possible basic soft switching topologies for a
boost converter. Fig. 1(d) is an example of how cell I can provide
soft switching for a buck converter.

337

Fig. 1. Soft switching converter examples: (a) boost with cell I; (b) boost using
cell II (c) boost using cell VI, and (d) buck using cell I.

In order to generalize the analysis for any possible placement

of the MVS circuit cells within a particular converter, two topological parameters, and , are used in the equations. is defined as the steady state current that flows through the resonant
inductor, , when the active switch, , is off. In Fig. 1(a),
is , in Fig. 1(b), is . In Fig. 1(c), is zero and in Fig. 1(d),
is .
is the voltage of any constant voltage source (with
respect to the switching period) around the zero voltage turn-off
loop as defined in [5], [14]. When the switch turns off, the current will flow in a path containing every element of this zero
voltage turn-off loop except the switch. This current will flow
is
into the positive terminal of . For instance, in Fig. 1(a),
. In Fig. 1(b), is zero. In Fig. 1(c), is
. In Fig. 1(d),
is zero.
A. Circuit Cells with Minimum Voltage Stress Across the
Active Switch
The operation of MVS cells is discussed specifically for Cell
I when placed in a boost converter shown in Fig. 1(a). Operation
of the MVS cells placed in other PWM converters differs only by
the topological parameters and . For basic circuit cell operation, Figs. 24 show the circuit stages, theoretical waveforms,
and circuit stage flow chart for the boost converter in Fig. 1(a)
respectively. Fig. 2 shows all the circuit stages whether or not
soft switching is achieved. Fig. 4 describes how they operate
together and shows the ending conditions for each stage. For
example, soft switching is achieved when stages 1, 2, 3, 4, 5a,
5b, 6a, 6b, and 7 operate. However, during stages 5b and 6a, if
the circuit conditions are not satisfied, stages 5c, 5d, and 5e will
conduct which will result in a hard switching turn-on of the main
switch. The conditions for soft switching are discussed below in
detail. Fig. 3 shows the waveforms of the converter when soft
switching is achieved. Basic cell operation can be understood
with reference only to these figures. Table III lists the detailed
circuit stage equations of the non minimum voltage stress circuit cells. For the detailed circuit stage equations of Fig. 1(a),
and
.
Table III can be used with
Stage 1 ( )Soft Turn On: This stage starts when the
main switch turns on. Because of , the current in the switch
ramps up slowly providing zero current turn on. This stage ends
when diode turns off. With an ideal diode as assumed in

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 3, MAY 2001

Fig. 2. Circuit stages for the minimum voltage stress converters.

Fig. 3. Theoretical waveforms of boost converter with minimum voltage

stress. V
is the gate voltage of the switch S .

Fig. 3, when the current in

reaches zero, the switch current
equals the input inductor current and stage 2 begins. For the nonideal case, the reverse recovery current of the diode will further
so that stage 2 begins with a negative
inductor
charge
current.
Stage 2 ( ) Resets: The beginning of this stage
stops conducting. During this stage,
occurs when diode

Fig. 4. Circuit stage flow chart with the stages ending conditions.

capacitor
is reset back to
v by resonating with
and
. At the end of this stage, the
voltage is ready
to provide zero voltage turn off of the active switch. The peak
switch current also occurs during this stage and equals

(1)

SMITH AND SMEDLEY: LOSSLESS PASSIVE SOFT SWITCHING METHODS FOR PWM CONVERTERS

339

TABLE II
RESONANT INTERVAL TIMES

TABLE III
MINIMUM VOLTAGE STRESS CIRCUIT CELL STATE EQUATIONS

Stage 3 ( )
Resets: During stage 3,
resets by
giving a peak
voltage at the
transferring its energy to
at the end
end of the stage as shown in Fig. 3. The energy in
. With a nonideal diode, this peak
of this stage equals
will also collect the
voltage and energy will be larger since
energy caused by the reverse recovery current of the diode
,
in Stage 1. The time for the resonant turn on interval,
( ) is listed in Table III.
Stage 4 ( )PWM On: Stage 4 is the normal PWM interval with the switch on.
Stage 5a ( )Soft Turn Off: This stage begins when the
main switch turns off. The current immediately starts charging
, providing zero voltage turn off of the main switch. Once the
,
voltage across the switch equals
stages 5a completes and stage 5b ( ) starts.
Sets: Capacitor
continues to be
Stage 5b ( )
charged during this stage but at small currents it may not reach to
required voltage for soft switching. Because there is a positive
voltage induced across , it will start to conduct. If the curreaches before
is set back to zero
rent in the inductor
, then the input inductor current will not completely
and zero current turn on will be lost during
commutate to

stage 1. To ensure soft switching the following inequality must

be satisfied:
(2)
where

and

As the current or resonant impedance decreases, it is harder to

satisfy this condition. The parameter is the same as described
value to
in [9]. As described in next stage (6a), the largest
. If the input current in (2)
ensure soft switching is
, then the inequality
is set to a defined minimum level
equals
(3)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 3, MAY 2001

With this substitution,

represents the largest maximum to
minimum current ratio possible that will still guarantee soft
switching.
Sets: Assuming that stage 5b comStage 6a ( )
reaching zero. As shown in Fig. 2, in stage 6a,
pletes with
and
are conducting,
is in parallel with .
because
is used to ensure
reaches to allow zero
The energy in
current turn on of the active switch. This quantity will be satis larger than the
isfied as long as the energy in
when current is flowing through it
.
energy in
Using this fact, the condition for soft switching is as follows:

Fig. 5. Soft versus hard turn-on switching waveforms.

(4)
in the equation above, then the energy in
By setting
is guaranteed to charge the
inductor current to . Otherwise, at large currents, some current will flow through diodes
and
, so that zero current turn on of the main
switch will not be satisfied (Stage 5e). Stage 6a finishes when
reaches (goto stage 6b) or
reaches 0 v (goto
either
stage 5e).
Discharges: During stage 6b, the adStage 6b ( )
is transferred to the output. Although this
ditional energy in
stage looks similar to stage 5c, the difference is that for this stage
capacitor voltage is zero (i.e.,
). In stage 5c, the
the
capacitor voltage is not zero and thus causes a hard turn on
of the main switch.
The time duration of the worst case resonant turn-off interval,

is shown in Table II. An exact solution with

stage 5b included does not allow a closed form solution. For
simplicity, the turn-off interval was computed assuming no
. It can
stage 5b where stage 5a ends when
be shown that this simplification will always gives a larger
turn off time then the exact solution. Therefore, by ensuring
will meet our design objectives, the
the approximated
solution will also work.
shorter exact
Stages 5c, 5d, 5eHard Turn On: As shown in Fig. 4 and
described by condition (2), at small currents the converter
may have a hard switching turn-on. This is caused because
,
, and
are still conducting
the snubber diodes
when the switch turns on. If condition (2) is not satisfied
is discharged to
stage 5c begins. Once the voltage across
then stage 5d starts. During stage
will decrease from
and resonate with
and
5d,
until
is 0 v (
). At the end of this stage,
will
will
equal approximately zero and the inductor current
and
(see
equal some value between
not flowing through
will flow
Table III). The portion of
, and
for stage 5e. For this condition,
through
when the main switch is turned on, zero current turn-on is no
longer satisfied.
At the start of stage 5e, the amount of current flowing through
, and
will determine how much deviation from
is much larger than ,
soft switching occurs. For instance, if
although soft switching is lost, the amount of current flowing
and
(i.e.,
) will be relthrough
atively small. It may be so small that the diode drops and input
inductor current ripple will quickly reduce this current to zero.

Fig. 6. Soft versus hard waveforms.

In any case, the amount of losses in the switch at turn on will

still be improved over the complete hard switching case (i.e., no
snubber).
III. RESONANT COMPONENTS FOR MINIMIZED
SWITCHING LOSSES
A. Soft Turn-On and Turn-Off Switching Losses
To properly choosing the soft switching inductor and capacitor, simple yet accurate models are used to determine the
switching losses at turn-on and turn-off. The turn-off model
assumes power MOSFETS are used.
1) Soft Turn-On Losses: When the active switch is turned on
in a hard switching converter, because of the passive nature of
the diode, there is a large voltage and current overlap, and thus
a large power loss occurs in the main switch. By placing the resonant inductor into the circuit appropriately, these losses can be
reduced by slowing the current increase at turn-on. Additionally, the switch voltage is no longer clamped while the current
increases. These improvements are illustrated by the hard and
soft turn-on waveform comparison shown in Fig. 5. Assuming
that the switch voltage decreases linearly to zero in time , the
losses in the switch can be modeled as follows:
(5)
where is the voltage across the switch before turn-on. This
equation is the same as described in [10].
2) Soft Turn-Off Losses: Efficiency improvements can also
be achieved at turn off by placing a resonant capacitor into the
circuit. However, for a MOSFET switch, the resonant capacitor
does not slow the voltage rise across the switch at turn-off, instead it diverts current as shown in the theoretical turn-off waves
capacitor
in Fig. 6. At both turn-on and turn-off, while the
(miller capacitance) is being charged or discharged, the gate
voltage is constant at a plateau voltage slightly higher than the
threshold voltage. Therefore, the rate of increase of the drain to
, is the same as for the drain to gate voltage,
source voltage,
. This observation shows that rate of rise of
at turn-off

SMITH AND SMEDLEY: LOSSLESS PASSIVE SOFT SWITCHING METHODS FOR PWM CONVERTERS

341

(rate of fall at turn-on) is determined by the gate current and

capacitance only
(6)
Equation (6) shows that the rate of voltage rise of the MOSFET
switch is independent of the resonant capacitor added for soft
switching. Instead, this capacitor will divert current through the
MOSFET as follows:
(7)
where is the current in the switch before turn-off and represents an inductive load.
The simple and accurate loss model for switch turn off is de. The gate
rived by finding approximate values for , and
current is defined as follows:

=0

Fig. 7. Switch turn-off current and voltage for different C r . (a) C r

nF;
(b) C r
: nF; (c) C r
nF; (d) C r
: nF; I s is 1 A/div, V ds is 50
v/div horizontal scale is 50 ns/div.

=04

=1

=14

(8)
is the gate plateau voltage (
)
is the gate resistance. Because of the relatively large
and
transconductance of the MOSFET switch ( ), the plateau
voltage can be approximated as a constant, independent of
changes by several orders of magnitude as
switch current.
voltage is increased. However, at higher voltages where
the
V) the
value levels out and
most of the losses occur (
can be approximated with a single value. Integrating (6) to find
the switch voltage and using (7), the losses during turn-off can
be described as
Fig. 8.

when
(9)
is the enOtherwise, the losses are approximately zero.
ergy stored in a parasitic capacitance between the drain of the
MOSFET and ground. As shown in (9), the switching losses are
linearly dependent on the snubber capacitor. When the snubber
capacitor is above a certain value, no noticeable improvement is
found.
3) Experiment Verification of the Turn-Off Loss Model: An
experimental circuit was constructed to measure the turn-off
losses in the switch and compare them to the theoretical losses
using the equation above. The parameters were as follows:
amps,
v,
,
MOSFET: IRFP460,
pf,
W (100 kHz),
v,
kHz, driver UC3710. The gate resistance
was
resistance plus the estimated
found from the sum of a 10
is a single
output resistance of the UC3710 driver (5 ).
value approximation of the capacitance found on the data sheet
V).
at high voltages (
Experimental waveforms of the current through and voltage
across the switch at turn-off are shown in Fig. 7 for several
values of snubber capacitor . The current was measured with

Experimental and Theoretical W

losses versus C .

a Tektronix A6302 Current probe. In addition, the ensure accurate relative timing between the signals, the signal delays between the current probe and voltage probe were matched. For
the hard switching case, the current does not decrease until the
nF,
switch voltage equals the output voltage. When
the switch current is diverted partially through . When
nF, even more of the current is diverted. Finally, when
nF, most of the current has been diverted. It shows that any
will not improve efficiency.
larger value of
Fig. 8 shows the close match between the theoretical and exloss values (in watts), proving that to
perimental
the first order, the losses are linearly dependent on the snubber
capacitor. The discrepancy at larger snubber capacitor values is
caused because as the snubber capacitor is increased, diverting
more current from the switch, the plateau voltage will decrease
slightly, slowing the voltage rise of the switch and increasing the
loses compared to the theoretical values. However, above the 1
most of the improvement
nF capacitance value
over the hard switching condition has been achieved. The turn
off model (9) is simple enough to perform hand calculations.
Even better approximations can be performed on a circuit simand
with piecewise linear or
ulator by modeling
nonlinear equations [11][13]. Circuit simulators can also provide detailed modeling of all other MOSFET characteristics.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 3, MAY 2001

B. Optimum Inductor and Capacitor Values

The soft switching loss models derived in the previous section
help quantify the opposing design objectives in order to obtain
the optimum inductor and capacitor values. Combining the turn
on and turn off losses, the total switching losses are as follows:

otherwise.
(10)
energy is assumed zero. Equation (10)
In this model, the
clearly shows that switching losses are lowered by simply inand
. The drawback, is that as
creasing the values of
the resonant elements increase, the converter will maintain soft
and
inswitching over a smaller duty ratio range (
tervals are larger). The optimum inductor and capacitor values
and
for an acceptable
are found by maximizing
and
intervals.
In order to simplify and mathematically describe these opposing constraints, the inductor and capacitor have been combined into one resonant frequency parameter

Now we can relate inductor and capacitor values with the resonant interval times by suggesting it be less than some fraction
) of the switching period ( )
(
(11)
or
The appropriate value of is chosen for a required
interval.
With the realistic constraint imposed by (11), the total
switching losses in (10) is minimized by setting the resonant
capacitor and inductor to the following:

as long as

(12)

In the ideal case, the design method has been simplified to

finding the value of . In Section IV, the value of will be
simply found by using Fig. 9.
Equations (11) and (12) are the essential equations to achieve
high efficiency soft switching over the required load range and
is the basis for the design procedures that follow in the next section. In retrospect, the result is intuitive. To minimize losses,
is set to
, and
is increased as large as possible while still
and
intervals are within the design
ensuring the
limit. However, depending on the type of circuit cell in the converter, these exact values may not be used.
There may be other constraints that must be satisfied to enis an
sure soft switching. For MVS cells, the ratio of
important constraint to guarantee soft switching [see (4)]. This
constraint is not reflected in (12). For non-MVS cell stress converters, any / ratio is possible so (12) can be used. The next

Fig. 9.

=C

Resonant turn-on and turn-off intervals: IR

=C .

=I

section discusses the added objectives that are to be met in the

generalized design procedures.
IV. DESIGN PROCEDURE OF LOSSLESS PASSIVE SOFT
SWITCHING CIRCUITS
A. Design Objectives
The design objectives for these circuit cells are listed as follows.
1) Ensure soft switching over given current range (
).
2) Minimizes switching losses and stresses.
and
intervals are short enough to
3) Ensure the
allow soft switching within the load and duty ratio range.
B. Design of Minimum Voltage Stress Circuit Cells
The following parameters are assumed to be known.
: The current range for soft switching.
1)
: The duty ratio range for soft switching.
2)
.
3)
The simplified design steps are as follows.
.
1) Set
This will satisfy the upper limit of objective one because of (4) and will minimize current stress across the
main switch (1).
.
2) Set
By (3), this satisfies lower limit of objective one as long
. As discussed previously, although
as
may not completely reset at lower curthe inductor
ratio is still small (0.1), the amount
rents, because
of current error will also be small.
3) Find the smallest value of from Fig. 9 that satisfies the
and
.
largest allowable values of
and
.
Fig. 9 graphically represents the equation for
and
with respect to (Table II). In these equaand
are replaced by with
and
tions,

SMITH AND SMEDLEY: LOSSLESS PASSIVE SOFT SWITCHING METHODS FOR PWM CONVERTERS

kT . For the
interval,
represents the worst case. For the
ratios are shown.
to the following:
4) Set , , and

343

since this
interval, several

(13)
Because of objective one, under most conditions the resulting
and
will not match the results given by (12).
values for
However, the procedure given guarantees soft switching and
minimizes the over current stress and the turn-on losses in the
main switch. This is because the largest is used, which minimized these parameters.
V. A PFC BOOST DESIGN EXAMPLE
To illustrate the procedure, a 750 W PFC boost rectifier
using a unity power factor controller is designed as an exv,
ample. The parameters are as follows:
V
% the switching frequency is 100 kHz.
Before the soft switching values can be chosen the current
range and duty ratio range for soft switching are identified as
follows:
: 11.9 amps2.7 amps;
1)
: 0.250.75;
2)
: 100 kHz.
3)
, occurs when the input voltage
The peak switch current,
V )
is at its minimum rms value ( in
amps
The minimum duty ratio,
V )
(

occurs when

in is a maximum

For a PFC circuit the values of

and
are related and
can be found several ways. For this design it was decided that
under full output power the converter will not lose soft switching
. This gives a minimum current level of 2.7
while
,
V ). The IR ratio (
) is
amps (
4.4. This range of current and duty ratio determines where soft
switching is guaranteed. For this PFC example, the duty ratio
becomes larger than 75% when the input current and voltage are
small. During this time, soft switching is lost. However, since
soft switching is less important at lower current levels it does
not affect performance.
Using the design procedure,
.
1)
.
2)
3)
To find , the largest allowable
and
times
is 0.25, so the
are used. For the parameters given,
interval will be satisfied for any
. For
the maximum duty ratio that soft switching is achieved,

Fig. 10. DCDC efficiency of soft switching PFC boost converter: V

250 V. Load adjusted at each V in value to represent a PFC operating point.

, and using the

curve for the
.
H,
nF,
nF.
4)
is well above the optimum
Notice that the value of
nF, using the IRFP460
value calculated from (12),
MOSFET with the driver information given in Section III-A
is needed to ensure
is set to the input current when
larger
the switch turns off. It also shows that the turn-off losses will
be very small.
An experimental circuit with the components listed above
was constructed to verify the design. Soft switching was verified to work over the designed duty cycle and load condition
range. DCDC efficiency measurements were made for the soft
switching boost converter and a hard switching converter. The
and
results are shown in Fig. 10. For the measurements,
the load were adjusted to represent several PFC operating states
over the given input voltage cycle. When the converter is operating at peak power (1500 W) (i.e., the input voltage and current
are at the highest), the efficiency improvement is 2.5% (35 W).
times gives

VI. CONCLUSION
General analysis and design methodology was presented for
the minimum voltage stress circuit cells. The design objectives
were based on two opposing constraints, minimizing switching
losses while maintaining soft switching over the required operand
lowers the switching losses
ating range. Increasing
as shown with the simple loss model proposed, at the expense
and
intervals. Therefore, by limiting the
of larger
and
to some portion
of
resonant period of
and
values can be found.
the switching period, optimized
is increased above
The loss model also illustrates that when
the optimal value, the decrease in switching losses is negligible.
The analysis of these circuit cells was discussed with respect
to a boost converter. However, since the cells have similar properties, the state equations can be used for any circuit that contains these cells just by giving the proper value for two topological parameters and . Analysis and design of the nonminimum voltage stress circuit cells are given in [7].

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 3, MAY 2001

APPENDIX
The conventions used in the equations below are as follows:
lower case currents and voltages signify quantities that vary over
the one switching cycle, while upper case quantities are con] are referenced to the bestant; Time parameters [i.e.,
is the current that flows through
ginning of each stage.
when the active switch is off.
is the voltage of any permanent voltage source around the zero voltage turn off loop. The
following variables are also used:

[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]

ACKNOWLEDGMENT
The authors would like to thank I. Matsuura, Power Electronics Laboratory, University of California, Irvine, for constructing the experimental boost circuit and performing the efficiency measurements.
REFERENCES
[1] I. Jitaru, Soft transitions power factor correction circuit, in Proc.
HFPC Conf. Rec., 1993.
[2] M. Vilela, E. Coelho, J. Vieira, Jr., L. de Freitas, and V. Farias, PWM
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, Lossless passive soft switching methods for inverters and amplifiers, IEEE Trans. Power Electron, to be published.

K. Mark Smith, Jr. (M93) received the B.S. degree

in electrical and computer engineering from the University of Colorado, Boulder, in 1990 and the M.S.
and Ph.D. degrees in electrical engineering from the
University of California, Irvine, in 1995 and 1999, respectively.
Since 1999, he has been working in industry designing high power converters and amplifiers. He has
published more than 12 conference and journal papers in the area of power electronics. His research
interests include soft switching of power converters,
and precision analog and digital control of switching power amplifiers. He has
been awarded one U.S. patent in the area of power electronics.

Keyue Ma Smedley (SM97) received the B.S. and

M.S. degrees in electrical engineering from Zhejiang
University, China, in 1982 and 1985, respectively,
and and the M.S. and Ph.D. degrees in electrical
engineering from the California Institute of Technology, Pasadena, in 1987 and 1991, respectively.
She was an Engineer at the Superconducting Super
Collider from 1990 to 1992, where she designed and
specified acdc conversion systems for all accelerator
rings. She joined the Faculty of Electrical and Computer Engineering, University of California, Irvine,
in 1992, where she has established the state-of-the-art Power Electronics Laboratory. Her research interest includes control, topologies, and integration of
dcdc converters, high fidelity class-D power amplifiers, active and passive
soft switching techniques, single-phase and three-phase power factor correction
and active power filter methods, grid-connected inverters for alternative energy
sources, etc.
Dr. Smedley is a member of Eta Kappa Nu and the Power Sources Manufacturers Association. She is an At-Large Adcom member of the IEEE Power
Electronics Society, the Chair of IEEE Power Electronics Society Constitution
and Bylaws Committee, and an Associate Editor of the IEEE TRANSACTIONS
ON POWER ELECTRONICS.