4.

HF transistors

Outline
Microwave and mm-wave transistors
High-frequency figures of merit
MOSFET structure & HF equivalent ckt.
SiGe HBT structure & HF equivalent ckt.
FETs vs. Bipolars

Solid-State Electronic Devices

Bipolar

Unipolar

Bipolar Junction Transistor

Heterojunction Bipolar Transistor

Field-Effect Transistor

J-FET

Homojunction
Bipolar Junction
Transistor (BJT)

CMOS

Si

MOSFET
Si, SiGe

Si

MESFET

LDMOS

GaAs

HEMT

Si

Heterojunction
Bipolar Transistor
(HBT)

GaAs, InP, GaN

GaAs, InP, SiGe

MG-MOSFET
Si, SiGe

p-HEMT

m-HEMT

GaAs, InP, GaN

MG m-MOSFET

InGaAs, Ge on Si?

 -wave & mm-wave transistors

SiGe HBT

InP (GaAs) HBT

 -wave & mm-wave transistors

Si MOSFET
tensile stress film

compressive stress film

gate
oxide
STI

source

p-sub

n-MOS

gate
drain

oxide
STI
STI

source
(SiGe)

n-sub

p-MOS

drain
(SiGe)

oxide
STI

22-nm ETSOI IBM/ST/LETI/GF/SOITEC

K. Cheng et al. Paper 18.1, IEDM 2012

S. Narasimha et al. Paper 3.3, IEDM 2012

6

Intel 22-nm FinFET

Fin not thin enough for fully depleted
Fin had to be doped=> bad for speed

C.-H. Jan et al.

Paper 3.1, IEDM 2012

What drives device performance?

Material properties
electron mobility (InP > SiGe > Si)
hole mobility (SiGe > Si > InP)
saturation velocity (InP > Si/SiGe)
breakdown field (InP > Si)
thermal conductivity (Si > SiGe > InP)
Lithography (Si > InP)
Yield & reliability (MOS > SiGe HBT > InP HBT)

FET

vs.

Unipolar: electrons or holes

HBT
Bipolar: electrons & holes
intrinsic device speed is

Intrinsic device speed is

laterally defined by L

vertically defined by WB

lithography driven.

atomic layer growth driven

Emitter

Gate

Qc

Depletion Layer

L
r

-Qch

Base

t
Channel

WB
Depletion Layer

Collector

In both cases, real device speed is affected by 3-D parasitics.

Scaling in 2D and 3D is important.
9

MOSFET

vs.

HEMT

Mostly on silicon

III-V and Si, SiGe

MOS insulator gate

Schottky gate

No gate current *

Gate current (small)

Inversion channel

Accumulation channel

Both p-type and n-type

Mostly n-type
Substrate node not biased,
connected to ground (as in SOI
MOSFETs)

Substrate node must be

biased

The same DC I-V characteristics and small-signal equivalent

circuit
Q =C W V V ; I =Q v E
n

gate

GS

DS

10

Typical Forward HBT Gummel Plot

V BE
V CE
IC =JS A E e xp
1
VT
VA

11

Transfer characteristics in 90-nm n-MOS

Square-law in sub 130-nm MOSFETs invalid for most bias range

IDS=k ' n LW V GSV T

12

Typical HBT output characteristics

Apparent negative ro
due to self-heating

IC =JS AE exp

VBE
VT

V CE
VA

13

45-nm SOI MOSFET output characteristics

Low output
resistance

14

DC Characteristics
FET
vs.
HBT
Transfer Characteristics:
Exponential in subth.

Transfer Characteristics:
Exponential

Square-law or linear in
saturation region
Low turn-on voltage: 0.5 to
0.2 V
Output Characteristics

High turn-on voltage: 0.7 to

0.9 V
Output Characteristics

Small VA (ro)

Large VA (ro)

Low breakdown

Moderate breakdown
15

HF equiv. circuit and y-matrix of intrinsic

CE/CS transistor
Cbc
B
Cbe

C
ro

Vbe

Ccs

Cgd

G
Cgs

vgs
Ri

gmvbeej n
E

[ ][

gme-j vgs

ro

Cdb

] [

y
j C' g sC' g d
j C' g d
g j Cb e Cb c
j Cb c
=
; [ y ]=
W
g ' m j C' g d g ' o j C' d bC' g d
g m j Cb c
g o j CcsCb c

Input admittance and voltage gain for 2-port loaded by

admittance YL

YIN =Y1 1

Y1 2 Y2 1
Y2 1
and Gv =
YL Y2 2
YL Y2 2
16

Common base/gate and cascode

FET/HBT in CG/CB

[ ][

y
g ' g ' o j C' gsC' s b
g ' o
= m
;
W
g ' m g ' o
g ' o j C' d b C' g d

[ y ]=

g m g o g j Cb e
g o
g m g o
g o j CcsCb c

FET/HBT in cascode topology

YIN =Y11, CS

Y12 , CS Y21,CS
Y
Y
Y22 ,CS Y11 ,CG 12, CG 21,CG
YL Y22,CG

Y2 1 , CS

Gv casc=
Y12,CG

Y1 1 , CGY2 2, CS
[ YL Y2 2 , CG]
Y2 1 , CG

17

CE/CS HF circuit useful for hand analysis

Cg d(bc)

Rg(b)
G(B)

Cgs(be)

Rd(c)
D(C)

Vgs(be)

g m ej v g sb e

ro

Cdb(cs)

Cgd(bc)

RG(B)

D(C)

G(B)
Cgs(be)eff

VIN

gmeff VIN

goeff

Cdb(cs)

Rs(e)
S(E)

S(E)

Impact of Rs(rE) included in RG(b), gm, fT and Cgs/Cb e

RG= Rg+Rs (can be used directly in Zi \n, NFMIN, Zsopt)
Zin= Rg+Rs jfT/(fgmeff)

18

Outline
Microwave and mm-wave transistors
High-frequency figures of merit

19

Figures of Merit (FoMs) for HF & High-Speed ICs

Devices: fT, fMAX, FMIN, BV
Circuits:
GIIP3f OIP3f
FoMLNA=
=
F1 P F1 P

RBMUXratio
FoMSERDES =
P
ZIMAX BW3dB
FoM TIA =
rm s
i n P

FoMVCO=

fo

Pout
L fP

FoMPA =Pou t GPAEf

20

Device Figures of Merit

Cutoff frequency definition
Maximum oscillation frequency definition
Minimum noise figure and noise parameters
Intrinsic slew rate

21

fT definition: 20*log10|H21(f=fT)| = 0
Y 21
gm
gm
H21=

Y 11 jCgsCgd jCbeCbc

Y2 1 T
H 2 1=
Y1 1 j

C C gd
1
= gs
C gd R sRd
2 f T
gm
Cbe C bc
1
=
r ErC C bc
2 fT
gm

22

fMAX definition MAGdB(f) =10*log (MAG)=0dB

fMAX is defined as the x-axis intercept of the power gain vs.
frequency plot.
Both MAG(f) and U(f) intercept the x-axis at the same point
10*log10U(f) has constant slope (approx. 20 dB/decade) and is
easier to extrapolate
Both can be calculated from measured S or Y parameters

23

U as a function of transistor 2-port params

(Mason, 1953)

U= 4 [ y

y 21y 12
11

y 22 y 12 y 21 ]

S2 1
2
MAG=
k k 1
S1 2
2

U= 4[ z

z 21z 122
11

z22 z12 z21 ]

1S11 S22 D
k=
2S12S21
D=S11S22S21S12

fMAX (unlike fT) contains information about output impedance

24

fMAX definition: U vs. MAG (same x-axis intcp.)

25

Noise params of intrinsic CE/CS transistor

2
n1

Noiseless
Y-matrix
2-port

2
n2

I2n 1
In 1 In* 2
Gu =

4 kT f 4 kT f Rn Y2 12

Ycor =y 1 1

In 1 I*n 2
4 kT f Rn y 2* 1

Rn =

I 2n 2
2

4 kT f y 2 1

Gu
2
Gsopt =
Gcor
Rn

FMIN =12R n Gcor Gsopt

Gu , Gsopt decrease with correlation, Rsopt increases

FMIN decreases with correlation
26

Noise parameters of the CG/CB transistor

Rn =

Gu =

I2n2
2

4 kT fy 21

2
n1

I
4kT f

*
n1 n2

I I

4 kT f RnY 21
*

Y cor =y 21y 11

In1 In2
4 kT f Rn y *21

Note: y-matrix is that of CG configuration

imag(Y21+Y11) in CG/CB imag(Y11) in CS/CE
27

Important ramifications for LNA design

Rn (CG) = Rn (CS)
Gu (CG) = Gu (CS)
Gcor (CG) = Gcor (CS)
FMIN (CG) FMIN (CS)
If correlation is weak, Imag(Ycor,Ysopt) = Imag (Yin) and can
be tuned out simultaneously

28

Noise equivalent circuit of intrinsic HBT

2
n1

Noiseless
Y-matrix
2-port

B
2
n2

RB
<inB>

ib

C
<inC>

IC

j n 2

i i =2q f IB 1e
*
nB nB

*
inC inC
=2q f IC

*
inB inC
=2qIC [exp j n 1]

29

MESFET (MOSFET) Intrinsic Noise Currents

(Pucel 1975)
af
I
In d2=4 k T f Pg m K f DS
f
2
f
In g2=4 k T f R g m 2
fT

jC=

In g Inx d

P ( ) = 2/3 (long channel)

R ( ) = 4/15 (long channel)
jC = j0.4 (long channel)

I I
2

nd

2
ng

Large noise signal model

30

FET Noise Sources (C. Enz MTT 2002)

= 2/3 (long
channel)
2

In d2=4 k T f g m K f

gm

Cgs
I =4 k T f g
m
2
ng

= 4/15 (long
channel)

Co x l g W f a f
2

jC=

In g Inx d

I I
2

nd

2
ng

jC = j0.4 (long
channel)
31

Pospieszalski T-dependent model (1989)

Vng , Tg, at input due to thermal noise from Ri
Ind, Td, at output to describe drain current noise
Ind and Vng are not correlated
Not large signal model
V2ng

Cgs

2
ngs

=4 k T g f R i

V2n d

Cgd

Rg

I2gs

vgs
Ri

gme-j vgs

I =2q f I g

Cdb

cds

I2nd

V2n b 2

V2n gs

I nd =4 k T d f g o
2
gs

ro

Rd

Rs

Rdsub

Csb

V2n s
V2n b 1

Rssub

32

Generating fT,fMAX and NFMINvs. IC/D plots

Increasing Vbe

fT is the intercept: 113 GHz.

33

n-MOSFET characteristic current densities

invariant across nodes and foundries

34

Characteristic current densities (ii)

JpfT = where fT reaches its max (n-FETs= 0.3-0.4 mA/ m)
JpfMAX=where fMAX reaches its max (n-FETs= 0.2-0.3 mA/ m)
JOPT=where NFMIN reaches its min (n-FETs=0.15-0.2 mA/ m)

Note: All characteristic current densities have started to

increase at the 45-nm node and beyond because of strain
and lack of EOX scaling

35

Characteristic current densities (iii)

In HBTs JOPT is a function of frequency
In HBTs

JpfT, JpfMAX and JOPT increase in every new node)

36

Impact of FET parasitic source/gate

resistances
gm
g m e
1 g m Rs

Cg sCg d
1

Rs Rd Cg d
2 f T
gm

Rs has greater impact than Rg

Rg is always accompanied by Rs

f MAX

Making Rg << Rs is not effective

fT
2 R i R s R g g o2 f T R g C gd

k1 depends on correlation (approx. 0.5)

FMIN1 2 k 1
1
ZSOPT FET
Cgs Cgd

f
g m Rs Rg 1

fT

gm R s R g
f Teff
j =
k1
f g meff

g 'm R 'sW f R 'g W f

j
k1

]
37

HBT fT, fMAX, NFMIN vs. IC characteristics

2
XC
CBE CBC
1
1 WB WB
kT
==

CBE CBC r Cr E CBCr C CCSF

DB v exit 2 v SAT qIC
2 fT
gm

f MAX

fT
8 r B C BC

1
ZSOPT HBT
C beCbc

gm
f Teff
r E R b j =
2
f gmeff

gm
r E R b j
2

1
f
FMIN HBT 1
2 gm R b r E

f Teff
38

Intrinsic Slew Rate

IpfT
SL i =
Co u t

I pfT
SL i =
Cb c Ccs

IpfT
SL i =
Cg d Cd b

Important for output drivers and digital circuits

Degraded by interconnect parasitics

39

Why do we need the HF FoMs?

Want to use the FOMs in circuit design
We have defined fT, fMAX, FMIN and techniques to
calculate them from the measured or simulated S
parameters and noise measurements (FMIN, Rn, opt
(GmIn in Spectre)
We now want to find expressions that link f T, fMAX,
FMIN to device bias current and geometry

40

Outline
Microwave and mm-wave transistors
High-frequency figures of merit
MOSFET structure & HF equivalent ckt.

41

Key nanoscale CMOS process features

STI to reduce active pitch
Retrograde Twin wells (latch-up, device parasitics)
M10

Triple well (deep n-well) for isolating p-well

oxide

Thick gate oxide devices for IO compatibility

M9

N+/P+ poly gate for symmetrical N/P-MOSFETs (HKMG in

<=45nm)

M8
M7

Self-aligned silicided D/S/G (low Rs, Rd, Rg)

M6

Tensile/compressive stress liners for mobility imprvmnt.

M5
M4

Dual Damascene Cu interconnects

tensile
stress liner
nitride spacer

p+

M3
Compressive oxide spacer
stress liner

Tungsten
contact via

nitride spacer

gate

n+
SDE
source
p+
contact

STI

silicide
contact

oxide spacer

SDE
n+
p+ drain

halo implants

p-well

p+

n+

p+

STI

STI

STI

STI

p+

p+

p+

p+
p+

silicide
contact

M2

gate

SDE
p+
source
n+
contact

contact

M1

SDE
p+
n+ drain
contact

halo implants

n-well

n+

STI

STI

p+

p+

Channel stop

Front end

oxide

Back end

Deep n-well
p- substrate

low-k

p- substrate

42

MOSFET structure and large signal circuit

B

gate

RS

p+

STI

STI

Rd
Dsb

RCO

Ddb

p+

STI

STI

Rdsb

Rsb

well

Rdb

Intrinsic
device

Intrinsic transistor
Two pn junctions

D
Rd

Rg
Rsub

Parasitic resistances
Rs

43

Typical MOSFET layout for highfrequency apps.

SOURCE CONTACT

SOURCE STRIPE

Dummy gate

DRAIN STRIPE

DRAIN CONTACT

GATE
CONTACT
10 gate fingers
44

Complete CS mall signal equivalent circuit

G

Cg d

Rg
Cgs

Rd

vgs
Ri

-j

gme

vgs

Rs
S

ro

Cdb

Cds

Rdsub

Csb
Rssub

45

Geometry dependence of equiv. ckt. params

g m =g ' m W ; g d s=g ' d s W ; Cg s=C' g s W ; Cg d=C' g d W ; Cd s=C' d s W
R 'i
R 'g d
R' s
Ri =
; Rg d=
; Rs =
;
W
W
W

R' d
Rd =
;
W

WF is the unit gate finger width.

W = NfxWf is the total gate finger width.
g'm, g'ds, C'gs, C'gd, C'ds, R'i, R'gd, R'd, R's are process-dependent
params
46

MOSFET Capacitances
B

Cdsf

Cf

p+

CJ

STI

STI

Cf

gate

Cov

Cov

CJSW

CJSWG

CJSWG

CJSW
CJ

p+

STI

Cdsb

STI

CJSW

CJSW

Cgate

CJSW

CJ S

Cgso
Wf

CJSW

CJSW

Cgdo D
CJ

Wext

Wext

Cgbo

CJSW

Cgcon
47

MOSFET substrate resistance network is

layout dependent
B

RCON

RCON
gate
p+

STI

p+

STI

RCO

Can be calculated based on

layout geometry and
doping/sheet resistance data

STI

RDBwell
RSBwell R
DSwell

RSTI

RCO

STI

RSTI

well
RCO

B
RSTI

RDBwell

RSBwell

RSTI

Wf

RSTI

RSTI

RCO
S

RSTI
B

RCO
D
RSTI

RCO
B

48

MOSFET source/drain resistance

Not layout dependent
Depends on gate width W
Rs/W remains practically
constant at 200-300 m
across nanoscale nodes

Rsp
Rsco

Rac

Rext

STI

STI

Rac = accumulation region resistance

Rsp = spreading resistance
Rext = resistance of the SDE region
Rsco = contact resistance
49

Gate Resistance: Layout dependent: W f

Nf = 3

Nf

Wf

XGW

XGW

GATE

Wf

Wf
S

XGW

XGW

REXT

RCON

Rgi

Rgi

Rgi

Rgi

XGW

iG

RCON

GATE

REXT
L

RCON, NCON

GATE

REXT

DRAIN
iSD
Rgi Rgi

iG

iSD

RCON

SOURCE

Rgi

DRAIN
iSD
R Rgi

Rgi

gi

iG

NCON = 1

Rgi

Wf
GATE

Rgi

REXT Rgi

RCON

iSD
SOURCE

Rgi

Rgi

Rgi

Rgi

Rgi REXT

Cgi Cgi Cgi Cgi Cgi Cgi

Rchi Rchi Rchi Rchi Rchi Rchi

Cgi

RCON

CHANNEL

Wf
GATE
RCON

REXT Rgi

Rgi

Rgi

Rgi

Rgi

Rgi REXT

Cgi Cgi Cgi Cgi Cgi Cgi Cgi

Rchi Rchi Rchi Rchi Rchi Rchi
CHANNEL

Rg =

Rg =

RCON RSHG
Wf

XGW
NCON
L
3

RCON RSHG
Wf

XGW
NCON
L
6

2 Nf

Nf
50

Numerical Example

10mx90nm device contacted on one side:

RSHG = 10 Ohm, L=65nm, NCON=1, RCON=20 , Wext

=150 nm;

a) Wf=1m; Nf = 10,
Rg =

b) Wf=2m; Nf = 5,
Rg =

20
10
1

0.15
1 0.065
3

10

20
10
2

0.15
1 0.065
3
5

2 074.3
=9.4 O h m
10

2 0126.15
=29.23 O h m
5

Rs=Rd = (1/W) 200 Ohm m = 20 Ohm in both cases.

51

Numerical Example (ii)

10mx90nm device contacted on both sides:

RSHG = 10 Ohm, L=65nm, NCON=1, RCON=20, Wext =150

nm;

a) Wf=1m; Nf = 10,
Rg =

20
10
1

0.15
1 0.065
6

b) Wf=2m; Nf = 5,
Rg =

20

20
10
2

0.15
1 0.065
6
10

2 048.71
=3.43 O h m
20

2 074.32
=9.4 O h m
10

Rs=Rd =(1/W) 200 Ohm m = 20 Ohm in both cases remain

large while Rg can be minimized.

52

JpfT invariant to VT
130/90/65-nm MOSFETs fT, fMAX current density invariant over
devices with
low,
standard,
high VT, and
different nodes

Constant-current-density bias => designs more robust to VT

variation
53

GP vs. LP 65nm CMOS

GP 30% faster than LP
and 300mV lower VGS =>
lower power!
VT variation is large but
mostly irrelevant
Constant-current-density
bias at 0.2-0.5mA/m =>
robust to IDS, VT variation
Need VDS> 0.6 V

54

MOSFET fM AX as a function of layout

f MAX =

fT
2 Ri Rs Rg g d s2 f T Cg d

fT

f MAX
2

RSHG W f
'
'
Ri Rs
g 'd s2 f T C'g d
1 23 l G

55

Impact of using minimum width devices on

fM A X and (likely) on NFM IN
In the 90-nm node fMAX
degrades by 25% as the unit
finger width is reduced from 1
m to 0.5 m.
Even though gate resistance
improves, the degradation in fT
leads to fMAX degradation.

56

MOSFET Impedance Noise Parameters

1Ri Cg s 2
Ru =Rs Rg k 2
gm

f2
Gn =k 1 g m 2
fT

k3
Z cor =Rs Rg k 3 Ri
j Cg s

f
Fm i n 1 2 k 1 g m Rs Rg k 2 1 2 R2i C2g s
fT
PR 1C2
PC PR
k 1 =PR2C PR ; k 2 =
; k 3=
k1
k1

57

MOSFET noise parameters finger width and

bias dependence
FMIN12 k 1

f
fT

'
2
g
R
W
g 'm R's m SHG f k 2 1 2 R2i C2g s
1 23 l G

FMIN12 Const

'
m

1 2 Const

V GSV T

FMIN is a (strong) function of Wf and

lG
FMIN decreases as a function of
VGS until gm (fT) reaches its peak.
58

Scaling of MOSFET HF Performance

C'gs,C'gd, C'db and ZSOPT approx. constant over nodes
g'm, g'o, fT, fMAX increase
FMIN , Rn decrease
RF & high-speed performance (except output swing) improves
with scaling
Leakage is not a problem at mm-waves and high-speed
Scaling is good for high-speed digital/wireline and mmwaves
59

Making Nano-CMOS Designs PVT Independent

CMOS characteristic densities are largely invariant across nodes and
foundries
Constant-current-density biasing in analog/RF/mm-wave CMOS
minimizes impact of L, IDS, T, and VT variation
Characteristic current densities are invariant over topologies (CS, CG,
cascode, CMOS inverter, TIA)
In circuit design, one must fix Wf, L and scale only Nf

Implications for circuit design

CMOS CML gates, LNAs, TIAs, VCOs, Mixers, PAs, Opamps and
filters can be designed algorithmically and ported across nodes and
foundries
60

Outline
Microwave and mm-wave transistors
High-frequency parameter definition
MOSFET structure & HF equivalent ckt.
SiGe HBT structure & HF equivalent ckt.

61

SiGe BiCMOS Technology Cross-section

silicide
contact

n-well

STI

p+

halo implants

p-well

n+

p+

STI

n+

STI

n-well

p+

p+

STI

STI

n+

n+

halo implants

n-well

p+

n+

STI

STI
p+

Deep n-well

STI

n-epi

STI

p+

DTI

n+

n+

emitter

gate

SiGe base

SIC

STI n+
Sinker
(n-plug)

Buried layer n+

p+
STI

DTI

gate

silicide
contact

n-epi

silicide
contact

p- substrate

p- substrate
p+

p+

62

SiGe HBT Cross-section

Deep trench isolation
between devices.

nitride D spacer
p+ external base poly

oxide
mono/poly
emitter

Reduces Ccs

SiGe base

Buried layer
p- substrate

n-epi

SIC

STI

n+

p+

Sinker
(n-plug)

SIC collector
STI

p-well
DTI

DTI

STI

n-epi

n+

p- substrate

Graded Ge base
L/D-shaped spacer
between emitter and
external base contact
Mono+poly emitter (low
RE)
63

SiGe HBT HF Equivalent Circuit

Cbcxt
rbxt
B
Cbox

rbi

rC

Cbe

Rsnk

Rbl

Cbci

gm e

-jn

ro

Ccs
Rsub

rE

64

Geometry Dependence of Small Signal Params

IC JC
IC JC
REsq
IC =JCwElE ; gm= = w ElE ; go = = w ElE ; RE=
;
VT V T
VA V A
lE w E
RSBXwSP
Rsbio wE
Rbx =
; Rbi=
for double-base
2wE lE
12 lE
RSBXw SP
Rsbio wE
Rbx =
; Rbi=
for single-base
wElE
3 lE

Cbe=Cbe ,diff C je =F gmCJEw ElE ; Cbep=CJEP2lE w E

Cbci=C jCiA BCi=C jCilEwE 2bsic
Cb c x =C jCX A BCextC JCX2 w BCspw El E2 w BCsp
65

fT dependence on emitter length

To first order, fT is independent of emitter length
because length dependence cancels out in CR
As a second order effect, fT depends slightly on lE due
to peripheral BE capacitance and Rc.

66

Typical HBT fT-IC plots for devices with

different emitter lengths

67

SiGe HBT fM A X layout dependence

fT
f MAX =
8 Rb Cc b
1
Rb
lE

Cbc l E

RC, Rsub, Ccs affect (degrade) fMAX

fM AX is a (strong) function of wE.
fMAX is a weak function of lE.
68

HBT noise parameters lE dependence

n2 VT
1
Rn =
RERb scales as
2 IC
lE

Ysopt

f
f T Rn

n1 ideality factor

IC
f 2T
n 2 f 2T
n
RERb 1 2
j
2V T
2
f
4 f2

n f
FMIN1
fT

scales as l E

IC
fT
n fT
RERb 1 2
2V T
f
4 f2

FMIN is weak function of lE but a (strong) function of wE

69

HBT noise parameters bias dependence

n2 VT
1
Rn =
RERb scales as
2 IC
IC
f
Ysopt
f T Rn

IC
f 2T
n 2 f 2T
n
RERb 1 2
j
increases with I C
2
2V T
2
f
4 f

n f
FMIN1
fT

IC
f 2T
n 2 f 2T
RERb 1 2
2V T
f
4 f2

FMIN first decreases (due to drop in Rb(IC) thermal noise is

dominant ) and then increases with IC (shot noise dominates)
70

HBT Summary
HBT characteristic densities increase in newer nodes
In a given technology, JOPT increases with frequency
JOPT increases if a series resistance is added to emitter or base
Large fM AX can be obtained at lower JC and with higher BVCEO than fT.

Implications for circuit design

Designs must be modified in each node/foundry, although, for a given
peak fT, JC appears to be similar between foundries.

71

Outline
Microwave and mm-wave transistors
High-frequency figures of merit
MOSFET structure & HF equivalent ckt.
SiGe HBT structure & HF equivalent ckt.
FETs vs. Bipolars

72

Noise Parameters: HBT VS. MOSFET (i)

HBT

MOSFET

1
Rn
r ERb
2 gm

f
Ysopt
f T Rn

gm
n
r ERb j
2
2

1 f gm
FMIN1
r R
fT 2 E b

Rn

Ysopt

P
Rs Rg
gm

f
Pg m Rs Rg j P ]
[

f T Rn

FMIN1

f
Pg m Rs Rg

fT

73

Noise Parameters: HBT VS. MOSFET (ii)

At equal bias current and comparable fT, the MOSFET has
lower gm and hence:
lower FMIN
lower Rn (higher sensitivity to Zsopt mismatch)
higher Rsopt (larger current for 50- noise matching)
In MOSFETs, the peak fMAX and the optimum noise bias
current density coincide. In HBTs the optimum noise current
density increases with frequency but is significantly smaller
than peak fT current density.
74

Low-noise transistor design

Two steps:
Bias transistor at optimal noise current density
Size transistor (while keeping the optimal noise current
density) to make the real part of the optimum noise
impedance (Rsopt) equal to the desired value.
Sizing is achieved by increasing Wf (lE) or connecting gate
fingers (emitter stripes) in parallel.

75

CMOS Technology over Nodes

Param/node

250nm

180nm

130nm:GP/LP

90nm:GP/LP

65nmGP/LP

45nm

250

180

120/120

65/80

45/57

39/35

3.5

2.1/2.3

1.6/2.1

1.3/1.8

1.1/1.3

VDD (V)

2.5

1.8

1.2/1.2

1.0/1.2

1.0/1.2

0.9/1

g'm (mS/m)

0.35

0.55

0.8/0.7

1.2/1

1.6/1.2

1.8?

g'o (mS/m)

0.03

0.05

0.08

0.13

0.18

0.17?

C'gs (fF/m)

1.4

1.4

0.7

0.6

C'gd (fF/m)

0.45

0.45

0.45

0.35

0.35

0.34?

C'db (fF/m)

1.5

1.5

1.5

1.1

0.8

0.6?

R's/R'd (*m)

100

120

150

200

200

200

n-MOS fT (GHz)

40

60

80/80

140/120

190/160

250?

L (nm)
EOT (nm)

76

Parasitic source and gate resistance

scaling
Parameter

65nm GP

65nm LP (GP)

45nm

Physical L (nm)

45

57 (45)

35

EOT (nm)

1.3

1.8 (1.3)

1.3 (1 for HKMG)

Wf (m)

0.7

NCON

Contact on both sides

No

No

No

RCON ()

40

40

60

RSHG (/sq)

15

15

20

Wext (nm)

120

120

100

Nf

RG ()

191

159 (190)

250.5

77