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Semiconductor Device Thermal

Characterization and System Design


Roger Stout, PE <roger.stout@onsemi.com>

Research Scientist
Corporate R&D: Technology Development

RPS • 2010 April Corporate Research & Development Packaging Technology


Course outline
• Part I: Characterization (75 minutes)
– Why Everything you Thought You Knew (about
device thermal characteristics) is Wrong
– Characterization Techniques
– Miscellaneous Measurement Techniques
• Part II: Linear Superposition (120 minutes)
– Basic Theory
– The Reciprocity Theorem
– A Detailed Example and its Implications
– Building a System Model
– Time Varying Heat Sources
• Part III: Thermal Runaway (45 minutes)
– Theory
– Datasheet example
– High-Temperature Reverse Bias “qual” example

Semiconductor Device Thermal Characterization


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Part I

Characterization

Semiconductor Device Thermal Characterization


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Can this device handle 2 W?

Semiconductor Device Thermal Characterization


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Why is ON’s SOT-23 thermal number
so much worse than the other guy’s?

• ON • some other guy


– SOT-23 package – SOT-23 package
– 60x60 die – 20x20 die
– Solder D/A – Epoxy D/A
– Copper leadframe – Alloy 42 leadframe
– Min-pad board – 1” x 2oz spreader
– Still air – Big fan

Semiconductor Device Thermal Characterization


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Fundamental ideas

• Heat flows from higher temperature to lower


temperature
• The bigger the temperature difference, the
more heat that flows
• Three modes of heat transfer
– Conduction (solids, fluids with no motion)
– Convection (fluids in motion)
– Radiation (it just happens)

Semiconductor Device Thermal Characterization


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Thermal-electrical analogy

temperature <=> voltage

power <=> current

Δtemp/power <=> resistance

energy/degree <=> capacitance

Semiconductor Device Thermal Characterization


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“Junction” temperature?

Historically, for discrete devices, the “junction” was literally the


essential “pn” junction of the device. This is still true for basic
rectifiers, bipolar transistors, and many other devices.

More generally, however, by “junction” these days we mean


the hottest place in the device, which will be somewhere on
the silicon (2nd Law of Thermodynamics).

This gets to be somewhat tricky to identify as we move to


complex devices where different parts of the silicon do
different jobs at different times.

Semiconductor Device Thermal Characterization


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What’s wrong with theta-JA?

TJ Ta TJ Ttab
JA Jtab
Pd Pd

TJ JA Pd Ta TJ Jtab Pd Ttab

Semiconductor Device Thermal Characterization


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Theta-JA vs. copper area

Semiconductor Device Thermal Characterization


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Typical thermal test board types

Min-pad board 1-inch-pad board


Minimum metal area to attach Device at center of 1”x1”
device (plus traces to get metal area (typically 1-oz Cu);
signals and power in and out) divided into sections based on
lead count
Semiconductor Device Thermal Characterization
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Theta ( ) vs.. Psi ( )

• JEDEC <http://www.jedec.org/> terminology


– Z JX , R JA older terms ref JESD23-3, 23-4
– JA ref JESD 51, 51-1
– JMA ref JESD 51-6
– JT, TA ref JESD 51-2
– JB, BA ref JESD 51-6, 51-8
– R JB ref JESD 51-8
– Great overview, all terms: JESD 51-12

Semiconductor Device Thermal Characterization


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“Theta” (Greek letter

We know actual heat flowing along path of interest


Tx Ty
xy
qpath

Ty
Tx

true “thermal resistance”


Semiconductor Device Thermal Characterization
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“Psi” (Greek letter
We don’t know actual heat flowing along path of interest

Tx Ty
xy
qtotal

?? Ty
Tx

… all we
know is total
heat input a reference number only

Semiconductor Device Thermal Characterization


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Facts and fallacies

• Basic idea:
– “thermal resistance” is an intrinsic property of a package
• Flaws in idea:
– there is no isothermal “surface”, so you can’t define a
“case” temperature
• Plastic body (especially) has big gradients
– different leads are at different temperatures
– multiple, parallel thermal paths out of package

Semiconductor Device Thermal Characterization


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An example of a device with two
different “Max Power” ratings
• Suppose a datasheet says:
– Tjmax = 150°C
– JA = 100°C/W • But it also says:
– Pd = 1.25W (Tamb=25°C) – JL = 25°C/W
– Pd = 3.0W (TL=75°C)
25 100 *1.25
75 25 * 3
25 125 150
75 75 150

Where’s the “inconsistency”?

Semiconductor Device Thermal Characterization


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Where’s the inconsistency?
TJ =150°C

25°C/W
( JL)
100°C/W
What’s TL? Not 75°C !!
( JA)

(try about 119°C)

…¾ of the way from


TA =25°C ambient to Tj

Semiconductor Device Thermal Characterization


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Back in the good old days ...

metal can --
fair approximation of axial leaded device --
“isothermal” surface only two leads, heat
path fairly well defined

Semiconductor Device Thermal Characterization


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Which lead? Where on case?

Semiconductor Device Thermal Characterization


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“Archetypal” package

10% convection

wire/clip case

silicon

die attach

flag/leadframe

10%
20% 60%
circuit board

Semiconductor Device Thermal Characterization


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Then we change things …

add an external heatsink … flip the die over …


optional optional
heatsink 40% heatsink 60%

mold optional
compound/ “case”
case

wire/clip
die
silicon
attach silicon
die attach
pads/
balls
flag/leadframe
optional
20% 40% underfill
20%
application board 20% application board

Semiconductor Device Thermal Characterization


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A bare “flip chip”

10%

silicon
pads/
balls
underfill 90%
application board

Semiconductor Device Thermal Characterization


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Same ref, different values

J tab 1.2 C/W


J tab 0.8 C/W
Pd 50 W
Pd 1.5W
Tc 25 C
Tc 25 C
1 GPM of H 2 O
still air

Semiconductor Device Thermal Characterization


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Even when it’s constant, it’s not!
1000 thetaJA - var brd only
900 thetaJA - var airflow

Tj 800
700
TJ Tamb
JA
R1 (path down R3 (path through
600 Q total
500
to board) case top) 400 1
constant at 20 constant at 80 300
200 1 1
package
environment TL TC 100 R1 R 2 R3 R 4
0 board

R2 (board R4 (case to air path 1 10 rstnc. [C/W] 100 1000

resistance) vary resistance) constant theta-JA


from 1 to 1000 at 500, or 20x R2
Tamb
psi-JT
25 psi-JL - var brd only 60 psi-JC - var brd only
psi-JL - var airflow psi-JC - var airflow
20 50

psi-JL 40
15 TJ TC
30 JT
T J TL
10
R1 Q total
JL
Q total R1 R 2 20
5 1 R3
R3 R 4 10
R3 R 4
0 0 1
1 10
board
rstnc. [C/W] 100 1000 1 10
board
R1 R 2
rstnc. [C/W] 100 1000

Semiconductor Device Thermal Characterization


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Tj
JA

Ta

Semiconductor Device Thermal Characterization


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Fallacies recap:

• “Package resistance” isn’t fixed:


– multiple heat paths exiting package
– boundary conditions dictate heat flow
• Heat sinks
• Neighboring devices/power dissipation
• Single vs.. double-sided boards
• Local convection vs.. board-edge cooling
• Multiple layers/power/ground planes

• Therefore, different application environments will


see different “package resistance”

Semiconductor Device Thermal Characterization


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Characterization Techniques
Typical TSP behavior

calibrate forward voltage at controlled,


small (say 1mA) sense current
Characterization Techniques
125°C

sense
current T
Vf 25°C

0.5 V Vf 0.7 V

Semiconductor Device Thermal Characterization


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How to measure Tj
true const. current supply approximate const. current supply

(1 mA typical)

10K

DUT
OR 10.7V
DUT

If V f-0.7V, then
I-1mA

Semiconductor Device Thermal Characterization


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How to heat
sample current is off
sample current is always on
while heating current on

10K 10K
heating heating
power power
supply supply

10.7V 10.7V

DUT OR DUT

Semiconductor Device Thermal Characterization


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The importance of 4-wire
measurements
+(1.00 V) 1A
Power
Output = 1 W
supply
-(0 V)

0.18 V
0.82 V

0.64 W 0.90 W
0.70 W
0.05 V 0.15 V 0.85 V
0.95 V
Semiconductor Device Thermal Characterization
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Which raises an interesting question:

+(1.00 V) 3A
Power
Output = 3 W
supply
-(0 V)

0.45 V 0.55 V
1.3 W 1.3 W
0.3 W
0.02 V 0.98 V

Is this a fair characterization of a low-Rds-on device?

Semiconductor Device Thermal Characterization


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Bipolar transistor

• TSP is Vce at designated TSP supply

“constant” current
10K
• Heating is through Vce
• Choose a base current that switch
permits adequate heating
bias resistor
TSP=Vce

bias supply heating supply

Semiconductor Device Thermal Characterization


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Schottky diode

• TSP is forward voltage at “low” current


• Voltages are typically very small (especially as
temperature goes up)
• Highly non-linear, though maybe better as TSP
current increases; because voltage is low, higher
TSP current may be acceptable
• Heating current will be large

Semiconductor Device Thermal Characterization


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MOSFET / TMOS

• Typically, use reverse bias TSP supply

“back body diode” for both


10K
TSP and for heating switch
• May need to tie gate to
source (or drain) for
reliable TSP characteristic
TSP=Vsd -
heating
supply
+

Semiconductor Device Thermal Characterization


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MOSFET / TMOS method 2

• If you have fast switches and


stable supplies TSP supply
• Forward bias everything and use
two different gate voltages 10K
close
switch
to heat

close close
switch switch to
to heat measure

V-gate
+ + TSP=Vds +
V-gate heating
for for supply
heating measure
- - -

Semiconductor Device Thermal Characterization


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RF MOS

• They exist to amplify high frequencies (i.e. noise)!

• Feedback resistors TSP supply


may keep them in DC
10K

close -
switch
to heat
TSP
supply
close close +
switch switch to
to heat measure TSP =
+ body +
V-gate
diode heating
for
supply
heating
- -

Semiconductor Device Thermal Characterization


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IGBT
• Drain-source channel used for TSP supply

both TSP and heating


• Find a gate voltage which “turns 10K

on” the drain-source channel


switch
enough for heating purposes
• Use same gate voltage, but
typically low TSP current for
TSP=Vds
temperature measurement
gate
voltage heating supply

Semiconductor Device Thermal Characterization


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Thyristor

• Anode--to-cathode voltage path TSP supply


used both for TSP and for heating
• typical TSP current probably lower 10K
switch
than “holding” current, so gate
must be turned on for TSP anode
gate
readings; try tying it to the anode
(even so, we used 20mA to test
SCR2146) TSP=Vac
• Hopefully, with anode tied to gate,
enough power can be dissipated to cathode heating
supply
heat device without exceeding
gate voltage limit

Semiconductor Device Thermal Characterization


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Logic and analog

• Find any TSP you can


– ESD diodes on inputs or outputs
– Body diodes somewhere
• Heat wherever you can
– High voltage limits on Vcc, Vee, whatever
– Body diodes or output drivers
– Live loads on outputs
• (be very careful how you measure power!)

Semiconductor Device Thermal Characterization


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Heating curve method
vs..
cooling curve method

Semiconductor Device Thermal Characterization


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Quick review:
Basic Tj measurement
first we heat then we measure

10K 10K
heating heating
power power
supply supply

10.7V 10.7V

DUT DUT

Semiconductor Device Thermal Characterization


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Question

• What happens when you switch


from “heat” to “measure”?

Answer: stuff changes

• More specifically, the junction


starts to cool down

Semiconductor Device Thermal Characterization


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Basic measurements
“heating curve”

current
voltage
transient method
1 ma

power-off cooling

power-off cooling

power-off cooling

power-off cooling
Vf high-
current
high-
current
high- high-
current current
heating heating
calibrate forward voltage heating heating

@ 1mA sense current

steady state reached


125°C

Temperature
convert cooling
T volts to
25°C
temperature measured
temperatures

.5V .7V
Vf Time

Semiconductor Device Thermal Characterization


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voltage Heating curve method #2

current
1 ma

Time

power-off cooling
power-off cooling

power-off cooling

power-off cooling
high- high- high- high-
current current current current
heating heating heating heating
Temperature

measured temperatures Time

Semiconductor Device Thermal Characterization


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measurements
Basic
“cooling curve”

current
transient method
voltage

Vf
1 ma calibrate forward voltage
high- @ 1mA sense current
power-off
current cooling
heating

Temperature
125°C
convert cooling
volts to T
temperature
steady state reached
Temperature

25°C

.5V .7V Time (from


Vf start of cooling)
Time subtract cooling curve from
heating transient cooling peak temperature to obtain
period period (data taken) “heating” curve equivalent

Semiconductor Device Thermal Characterization


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Whoa!
… that last step there …

• Heating vs.. cooling


– Physics is symmetric, as long as the material
and system properties are independent of
temperature

Semiconductor Device Thermal Characterization


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Heating vs.. cooling symmetry

Start of constant Start of (constant)


power input power off
(“step heating”) junction

flag

lead (all the same


curves, flipped
vertically)
back of board

edge of board

Semiconductor Device Thermal Characterization


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• For a theoretically valid cooling curve,
you must begin at true thermal
equilibrium (not uniform temperature,
but steady state)
• So whatever your JA, max power is
limited to:

T j max Tambient
power
JA

Semiconductor Device Thermal Characterization


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By the way …
Steady-state vs.. transient ?

• Since you must have the device at steady state in


order to make a full transient cooling-curve
measurement, steady-state JA is a freebie.
(given that you account for the slight cooling
which took place before your first good
measurement occurred)

Semiconductor Device Thermal Characterization


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Effect of power on heating curve

24x steady- 3x steady-


state power state power

6x steady- 2x steady-state power


state power

Tj-max
steady-state max power
junction temperature

< steady-state max power

Tamb time
Semiconductor Device Thermal Characterization
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Some initial uncertainty

a few initial points


may be uncertain
high-current
heating

but once we’re past


Temperature

steady state reached


the “uncertain” range,
all the rest of the
points are “good”

power-off
cooling
heating period transient cooling period
(data taken)
Time

Semiconductor Device Thermal Characterization


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Heating vs.. cooling tradeoffs

HEATING COOLING
starting
ambient ?
temperature
heating limited by limited to
power tester steady-state
temperature of closer to closer to
fastest data ambient Tj-max
error all points error limited to
control similar error first few points
Semiconductor Device Thermal Characterization
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Still air vs.. moving air

• Varying the air speed is mainly varying the heat


loss from the test board surface area, not from
the package itself
• You just keep re-measuring your board’s
characteristics

Semiconductor Device Thermal Characterization


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100
total system thermal resistance
90

80 little package
package resistance
70

60
theta-JA [C/W]

50

medium-
40
sized
package
30

20

board resistance
10 big package

0
0.1 1 10
air speed [m/s]

Semiconductor Device Thermal Characterization


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Different boards

• Min-pad board

• 1” heat spreader board

• You’re mainly characterizing how copper area


affects every package and board, not how a
particular package depends on copper area

Semiconductor Device Thermal Characterization


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1" pad vs min-pad Roger Stout 5/25/2000
350
Source:
Un-derated thermal data SOD-323

300
from old PPD database

250 SOT-23
TSOP-6
1" pad thetaJA (C/W)

SOT-23

200
SOD-123
SOD-123

TSOP-6(AL42)
SOT-23
150

SO-8 Micro 8
TSOP-6 SOD-123
100
SMA & Pow ermite
SMB
Dpak SMC overall linear fit is:
D2pak & TO220
50 SO-8
SOT-223 1" value = [0.51*(min-pad value) - 7]
Top Can

Top Can

0
0 100 200 300 400 500 600 700
min pad thetaJA (C/W)

Semiconductor Device Thermal Characterization


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Standard coldplate testing

• “infinite” heatsink (that really isn’t) for measuring theta-


JC on high-power devices

• If both power and coldplate temperature are


independently controlled, “two parameter” compact
models may be created

Semiconductor Device Thermal Characterization


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Standard coldplate testing

• Detailed design and placement of “case” TC can


have significant effect on measured value

Semiconductor Device Thermal Characterization


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2-parameter data reduction
Q Q1 Q2
heat up, Q1

T1
1 1
Q
R1
(T j T1 ) R2
(
T j T2 )
R1
This has the form of a two-variable linear equation:
heat in, Q Tj y m1 x1 m2 x2 b

R2 where: 1
m1 x1 (T j T1 )
R1
T2 b 0
1
m2 x2 (T j T2 )
R2
heat down, Q2

Semiconductor Device Thermal Characterization


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A “single coldplate” test

ambient 120. 00 Tj Ta
Ta
100. 00
Rja
80.0 0 Tc coldplate
Tjc ( ¡C)

Tj 60.0 0

40.0 0 Incr easing Power, Chuck H eld


Rjc
Cold
20.0 0 No P ower, Chuck T emper ature
Tc Incr eased
0.00
-20. 00 0.00 20.0 0 40.0 0 60.0 0 80.0 0 100. 00
coldplate -20. 00 Tja (¡C)

Semiconductor Device Thermal Characterization


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A “single coldplate” test,
ambient
package down
Ta
120. 00 Ta
Tj Tb
Rba
100. 00
Tb
80.0 0
Tc coldplate
Tjc ( ¡C)

Rjb
60.0 0
Tj
40.0 0 Incr easing Power, Chuck H eld
Rjc Cold
Tc 20.0 0 No P ower, Chuck T emper ature
Incr eased
0.00
coldplate -10. 00 0.00 10.0 0 20.0 0 30.0 0 40.0 0 50.0 0 60.0 0
-20. 00 Tjb (¡C)

Semiconductor Device Thermal Characterization


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Miscellaneous Measurement Topics

• Thermocouple Theory 101


• Infrared Theory 202

Semiconductor Device Thermal Characterization


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Thermocouple Theory 101

Semiconductor Device Thermal Characterization


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Thermocouple Theory
region “B” - 20cm of wire length
between the junction and the door
region “C” – 10cm of TC wire
of the temperature chamber
length passing from inside of
chamber door to outside of
chamber door
TC junction
B
A C TC scanner
D
perfectly uniform
temperature
chamber at 100°C
perfectly uniform ambient
temperature of 25°C
region “A” - a 1cc box region “D” – 100cm of TC wire
around the junction length from outside of chamber
to TC measuring instrument

Semiconductor Device Thermal Characterization


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Thermocouple Theory
• Question #1:
– where is the temperature actually being “sensed”? or to
put it another way, which region of the four defined above
(A, B, C, D), is the one that matters, as far as generating
the EMF being measured by the TC scanner? Why?
The emf is generated
where there is a
temperature gradient
TC junction
B D
A C

perfectly uniform
temperature
chamber at 100°C perfectly uniform
ambient at 25°C

Semiconductor Device Thermal Characterization


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Thermocouple Theory

• Question #2:
– if the purpose of the TC scanner is to measure an
EMF, theoretically how much current has to flow in the
wire to make the correct measurement?

None. Ideally, a galvanometer circuit balances


the EMF at the scanner until no current flows.

Corollary: wire size, and therefore resistance, may affect


how long it takes the galvanometer circuit to stabilize.

Semiconductor Device Thermal Characterization


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Thermocouple Theory

• Question #3:
– what do the two wires in the TC actually do, and why
do they have to be made of different materials?
100°C ΔV=0.0025V

25°C
Different materials have different Seebeck
coefficients, i.e., V/°C. So if you have two
different materials, the same temperature
gradient appearing in along both wires will
100°C
result in two different EMF’s. 25°C

ΔV=0.0037V

Semiconductor Device Thermal Characterization


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Thermocouple Theory
• Question #4:
– what does the “junction” in a TC actually do?

25°C
ΔV=0.0025V
Provides the common electrical point that
relates the EMF’s in the two wires to
each other, hence the net difference Net
ΔV=0.0012V
100°C
appears at the “open” end of the circuit.

The junction DOES NOT “measure”


the temperature; the wires do!
ΔV=0.0037V

Corollary: if the junction itself is isothermal, 25°C


it can be made of any material whatsoever!
Semiconductor Device Thermal Characterization
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Thermocouple Theory

• Question #5:
– if you really wanted to “calibrate” this thermocouple,
where would you need to apply the test conditions?

Everywhere along
TC junction
its length!
B D
A C

Semiconductor Device Thermal Characterization


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Infrared Theory 202

Semiconductor Device Thermal Characterization


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Infrared Theory

A opaque surface radiates thermal


energy in proportion to its absolute
temperature (to the fourth power),
and some other things

4
q AT
Semiconductor Device Thermal Characterization
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Infrared Theory

It’s also absorbing infrared energy from


everything else around it (since
everything else has a temperature and
is therefore emitting)

It turns out that the


“absorptivity” equals
the “emissivity.”

Semiconductor Device Thermal Characterization


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Infrared Theory
There is thus a net energy transfer which, in
the simplest situations, may be described by:

Aobj (Tobj )
4 4
q obj Tencl

(typically applies to a small,


isothermal object in a big,
isothermal enclosure)

Semiconductor Device Thermal Characterization


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Infrared Theory

But it quickly gets more complicated


when there are multiple objects (or
temperatures) hanging around.

• Each object has a “view factor” of


every other object
• Each object has its own emissivity
(usually NOT unity)

Semiconductor Device Thermal Characterization


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Infrared Theory

The “emissivity,” , is also related


to the “reflectivity,” , as follows:

1
So the worse something emits, the
better it reflects, and vice-versa.

Semiconductor Device Thermal Characterization


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Infrared Theory

In other words, unless you’re looking at a


perfect emitter (aka a “blackbody”), you
don’t simply see less radiation than you
would for a blackbody, you see some of
the radiation of what’s behind you!

Semiconductor Device Thermal Characterization


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Infrared Theory

In even the simplest real-life situation,


you usually have four “objects,” and their
associated temperatures, to consider:

• The test specimen (130°C)


• The surrounding room (25°C)
• You (33°C)
• The detector (-195°C)

Semiconductor Device Thermal Characterization


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Infrared Theory

(the room)

The “target”

(the detector
itself)

(you)

(the room)

Semiconductor Device Thermal Characterization


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Infrared Theory

So if you’re looking at a shiny, low emissivity


specimen, you’ll see a combination of these
four temperatures (that is, the radiation
representing these four temperatures) all
bouncing into the detector!

Depending on the angles involved,


therefore, it is quite possible to see vastly
higher temperatures than are really there, or
vastly lower temperatures are really there.

Semiconductor Device Thermal Characterization


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Hot water loop Footprints

Semiconductor Device Thermal Characterization


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Direct view In mirror

Semiconductor Device Thermal Characterization


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Reflection Emissivity

Semiconductor Device Thermal Characterization


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View at 10 am View at 10 pm

Semiconductor Device Thermal Characterization


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Semiconductor Device Thermal Characterization
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Infrared Theory

Moral:

For accurate temperature measurements, you


must account for the emissivity of the target,

and you must control the background!

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Infrared Theory

Here’s one way to approach it:

isothermal
enclosure, high
emissivity, opaque
IR camera
to infrared

DUT

Semiconductor Device Thermal Characterization


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Infrared Theory

Governing equation Two reference scans


I1 I back a T14
I I back a T 4
I2 I back a T2 4
Solve for Temperature
1 Solve for the unknowns
I I back 4
T I2 I1 T2 4 I1 T14 I 2
a a 4 4
I back
T2 T1 T2 4 T14

In terms of the reference scan quantities:


1
T2 (I I1 ) T1 (I I2 )
4 4 4

T
I 2 I1

Semiconductor Device Thermal Characterization


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Part II

Linear Superposition

Semiconductor Device Thermal Characterization


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Linear superposition
– what is it?

• The total response of a point within the


system, to excitations at all points of
the system, is the sum of the individual
responses to each excitation taken
independently.

Tcomposite Tsource1 Tsource 2  Tsource n

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Linear superposition
– when does it apply?

• The system must be “linear” – in brief, all


individual responses must be proportional to
all individual excitations.

Tnet A TA B TA C TA D

TA 2 qB 3 qC 1.2 qD

Semiconductor Device Thermal Characterization


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Linear superposition doesn’t
apply if the system isn’t linear.

T a(T , q1 ) q1 b(T , q2 ) q2 

n1 n2
T a q1 b q2 

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Linear superposition
– how do you use it?
Tamb

Tref5
Tj6 Tj5

Tj3 Tj2
Tref3

Tref1
Tj4 Tj1

TB

Semiconductor Device Thermal Characterization


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Linear superposition
– when would you use it?

When you have multiple heat sources


(that is, all the time!)

Semiconductor Device Thermal Characterization


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power
junction
input
temperature theta matrix assembled
vector
vector from simplified subsystems

T j1 J 1A 12  1n q1
Tj2 21 J 2A 2n q2
Ta
    
T jn n1 n2  JnA qn
board
self-heating terms interactions
Semiconductor Device Thermal Characterization
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power
junction
input
temperature theta matrix assembled vector
vector from simplified subsystems

T j1 JB1 BA1 12  1n q1
Tj2 21 JB 2 BA2 2n q2
Ta
    
T jn n1 n2  JBn BAn qn
device
resistance board
resistance
Semiconductor Device Thermal Characterization
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visualizing theta and psi
heat in here
measurements
here are s
J1A
measurements
J1B here are s
(idle heat
source “x”)
(idle heat
BA source “y”)
xA
yA

thermal ground
Semiconductor Device Thermal Characterization
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theta matrix doesn’t have to be square
junction one column for
temperature power input
each heat source
vector vector
T j1 JA1 12 13

Tj2 12 JA 2 23 q1
TxA x1 x2 x3 q2 one row
for each
TL1 A L1 1 L1 2 L1 3 q3
heat
TBA B1 B2 B3 source
(why is this
one row for each temperature
and not ?)
location of interest
Semiconductor Device Thermal Characterization
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Electrical reciprocity

+
+

+
?V
-
VV
0.3
+ -
5V
-
I 0.3
2 AV
-

Semiconductor Device Thermal Characterization


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Thermal reciprocity

heat input here

same
response response
here here

Semiconductor Device Thermal Characterization


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Another thermal reciprocity example

heat input here


(r) (s)

response same
here response
here

(s) (r)

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When does reciprocity NOT Apply?

• Upwind and downwind in forced-convection


dominated applications

C
airflow
A
D

Heat in at “A” will raise temperature


“B” and “D” may
of “C” more than heat in at “C” will
still be roughly
raise temperature of “A”
reciprocal

Semiconductor Device Thermal Characterization


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(square part of) matrix is symmetric
columns are the heat sources

J1 75 65 55 60 22 10
J2 65 71 60 55 25 11
J3 55 60 65 61 21 15
J4 60 55 61 73 18 11
rows are the 22 25 21 18 125 14
J5
response
locations J6 10 11 15 11 14 180
R1 73 65 55 59 22 10
R3 55 60 63 61 21 15
R5 20 24 14 19 95 15
B 65 63 62 63 21 12

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Superposition example

Tamb=25

Tref5=47.0
Tj6=36.0 Tj5=49.2

Device 1
Tj3=85.5 Tj2=96.5
heated, 1.1 W
Tref3=85.5

Tref1=105.3
Tj4=91.0 Tj1=107.5

TB=96.5

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Reduce the data

j1A 75
Tj1 Tamb 107.5 25
j1A 75 j2A 65
q1 1.1
j3A 55
Tj2 Tamb 96.5 25
j2 A 65 j4A 60
q1 1.1
j5A 22
10
 j6A

r1A 73
TB Tamb 96.5 25 r3A 55
BA 65
q1 1 .1 20
r5A

BA 65

Semiconductor Device Thermal Characterization


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Device 2 heated, 1.2 W
j1A 65

j2A 71
Tamb=25
j3A 60
Tref5=53.8 j4A 55
Tj6=38.2 Tj5=55.0
j5A 25

j6A 11

r1A 65
Tj3=97.0 Tj2=110.2
r3A 60
Tref3=97.0
r5A 24
Tref1=103.0
Tj4=91.0 BA 63
Tj1=103.0

TB=100.6
Semiconductor Device Thermal Characterization
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Device 3 heated, 1.3 W
j1A 55
Tamb=25
j2A 60
Tref5=43.2 65
j3A
Tj6=44.5 Tj5=52.3
j4A 61

j5A 21

j6A 15
Tj3=109.5 Tj2=103.0
r1A 55
Tref3=106.9
r3A 63
Tref1=96.5
Tj4=104.3 Tj1=96.5 r5A 14

BA 62
TB=105.6

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Device 4 heated, 1.1 W
j1A 60
Tamb=25
j2A 55
Tref5=45.9 61
j3A
Tj6=37.1 Tj5=44.8
j4A 73

j5A 18

j6A 11
Tj3=92.1 Tj2=85.5
r1A 59
Tref3=92.1
r3A 61
Tref1=89.9
Tj4=105.3 Tj1=91.0 r5A 19

BA 63
TB=94.3

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Device 5 heated, 0.7 W
j1A 22
Tamb=25
j2A 25
Tref5=91.5 21
j3A
Tj6=34.8 Tj5=112.5
j4A 18

j5A 125

j6A 14
Tj3=39.7 Tj2=42.5
r1A 22
Tref3=39.7
r3A 21
Tref1=40.4
Tj4=37.6 Tj1=40.4 r5A 95

BA 21
TB=39.7

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Device 6 heated, 0.5 W
j1A 10
Tamb=25
j2A 11
Tref5=32.5 15
j3A
Tj6=115.0 Tj5=32.0
j4A 11

j5A 14

j6A 180
Tj3=32.5 Tj2=30.5
r1A 10
Tref3=32.5
r3A 15
Tref1=30.0
Tj4=30.5 Tj1=30.0 r5A 15

BA 12
TB=31.0

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Collect the / values
columns are the heat sources
J1 75 65 55 60 22 10
J2 65 71 60 55 25 11
J3 55 60 65 61 21 15
J4 60 55 61 73 18 11
rows are the 22 25 21 18 125 14
J5
response
locations J6 10 11 15 11 14 180
R1 73 65 55 59 22 10
R3 55 60 63 61 21 15
R5 20 24 14 19 95 15
B 65 63 62 63 21 12

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Now apply actual power

Tamb=25
Actual power
Tref5=106.3 in application
Tj6=139.1 Tj5=124.7
Qj1 .4
Q j2 .4
Q j3 .4
Tj3=134.9 Tj2=140.1
Q j4 .4
Tref3=134.1
Q j5 .5
Tref1=138.8
Tj4=135.8 Tj1=140.0 Q j6 .2

TB=139.1

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Compute some effective / values
Take Tj1, for instance. Remember when it was
heated all alone, we calculated its self-heating
theta-JA like this:

Tj1 Tamb 107.5 25


j1A 75
q1 1.1

Now let’s see:

Tj1 Tamb 140 25


j1A 288
q1 0.4
Semiconductor Device Thermal Characterization
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And that’s not just a single aberration!
Junction to Reference
Self heating 3.0 vs.
1.5x 2.0
j1-R1

j1A 288 vs. 75 j3-R3 2.0 vs.


1.0x 2.0
3.8x
j2A 288 vs. 71 j5-R5 36.8 vs.
1.2x 30.0
4.1x
274 vs. 65 Junction to Board
j3A
4.2x
277 vs. 73 j1-B 2.2 vs.
0.2x 10.0
j4A 3.8x
j2-B 2.5 vs.
0.3x 8.0
j5A 199 vs.
1.6x 125
j3-B -10.5 vs.
-3.5x 3.0
j6A 309 vs.
1.7x 180
j4-B -8.3 vs.
-0.8x 10.0

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Is the moral clear?
• You simply cannot use published theta-JA values for
devices in your real system, even if those values are
perfectly accurate and correct as reported on the
datasheet and you know the exact specifications of
the test conditions.
• Not unless your actual application is identical to the
manufacturer’s test board – and uses just that one
device all by itself.

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So is it really this bad?
Only sort-of. Let’s revisit the math for one device …
Tj1 J1A 12  1n q1
Tj2 12 J2 A 2n q2
Ta
    
Tjn 1n 2n  JnA qn
Tj1 J1A q1 12 q2  1nqn Ta
n
Tj1 “effective”
J1A q1 1n qn Ta
2 ambient

Semiconductor Device Thermal Characterization


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A graphical view power, q

Isolated
device 1
Tj1 J1A q1 Ta J1A

Ta junction temperature , TJ1


Device in a
system shift in effective
ambient
n
Tj1 1
J1A q1 1n qn Ta
2 still the
J1A
same slope
J1A q1 Ta
junction temperature , TJ1
Ta Ta’

Semiconductor Device Thermal Characterization


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What about that “system” theta
device #1
we saw earlier that was so power/temperature
different? perturbations will
fall on this line
power
q1 NOT this one

the “system”
theta-JA

1
J1A

J1A

1
the isolated-device
n
theta-JA
1n qn TJ1 junction temperature
Ta 2 Ta’

Semiconductor Device Thermal Characterization


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How does effective ambient relate to board temperature?
if any of these are non-zero,
“system” slope for Ta will be higher than Ta
isolated device
n
Tj1 j1a Q1 ( i1 Qi ) Ta
i 2

( j1B B1a )Q 1
effective
Ta
ambient

when Q1 is
j1B Q1 B1a Q1 Ta not zero,
zero, both
both of
of these
these willwill
be
be non-zero
zero
Tj1B TB1a Ta
temperature temperature rise,
rise, board to J1 ambient to board
Semiconductor Device Thermal Characterization
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Predicting the temperature
of high power components
• The device and system are equally
important to get right

Predicting the temperature


of low power components
• The system is probably more
important than the device

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Using the previous board example …
theta array
J1 75 65 55 60 22 10 power
J2 65 71 60 55 25 11 vector
J3 55 60 65 61 21 15
Qj1 0.5
J4 60 55 61 73 18 11
Q j2 0.5
J5 22 25 21 18 125 14
Q j3 0.5
J6 10 11 15 11 14 180
Q j4 0.5
R1 73 65 55 59 22 10
Q j5 0.2
R3 55 60 63 61 21 15
Q j6 0.02
R5 20 24 14 19 95 15
B 65 63 62 63 21 12

Semiconductor Device Thermal Characterization


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Observe the relative contributions

For junction 1 (a high power component) we have:


the device itself …
the other devices …
= (75 x 0.5) +
(65 x 0.5) + (55 x 0.5) + (60 x 0.5) + (22 x 0.2) + (10 x 0.02)
+ 25

= 37.5 + 32.5 + 27.5 + 30 + 4.4 + 0.2 + 25

= 37.5 + 94.6 + 25

Semiconductor Device Thermal Characterization


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Graphically, a high-power device looks like this:

power increasing
power
q1=0.5 W
note the “embedded” decreasing
theta-JA looks like power
264 C/W
1 1

264 C/W 75 C/W

=94.6 C =37.5 C
n
1n qn
(θJ1Aq1) junction temperature
25 C 157 C
2
TJ1

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Relative contributions to TJ6

the other devices …


= (10 x 0.5) + (11 x 0.5) + (15 x 0.5) + (11 x 0.5) + (14 x 0.2)
+ (180 x 0.02)
the device itself … + 25

= 5.0 + 5.5 + 7.5 + 5.5 + 2.8 + 3.6 + 25

= 26.3 + 3.6 + 25

Semiconductor Device Thermal Characterization


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Graphically, low-power device #6 looks like this:

power

and just in case you were


wondering, the “embedded”
theta-JA looks like 1495 C/W !
1
=3.6 C
180 C/W
q6=0.02 W

=26.3 C junction
25 C 54 C temperature
TJ6

Semiconductor Device Thermal Characterization


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Controlling the matrix

How to harness this math in Excel®

Semiconductor Device Thermal Characterization


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3x3 theta matrix, 3x1 power vector Excel® math
obtained by using Matrix MULTiply
Ctrl-Shift-Enter rather multi-cell placement
{=array formula notation} than ordinary Enter of array formula

theta power array reference array reference


matrix vector to theta matrix to power vector

Semiconductor Device Thermal Characterization


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7x3 theta matrix, 3x1 power vector Excel® math
theta matrix is no longer square – don’t forget to use
# of columns still must equal Ctrl-Shift-Enter
array formula now
# of rows of power vector to invoke array formula notation occupies 7 cells

Semiconductor Device Thermal Characterization


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7x3 theta matrix, 3x2 power vector Excel® math
power “vector” is now a 3x2 array –
each column is a different power the single MMULT array formula now occupies
scenario, yet both are still processed 7 rows and 2 columns (one column for each
using a single array (MMULT) formula independent power scenario result)

Semiconductor Device Thermal Characterization


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Temperature direct contributions and totals
120 120

100 100

temperature rise [C] sum of sources


temperature rise [C], each source

80 80

60 60

40 40

20 20

0 0
J1 J2 J3 J4 J5 J6 R1 R3 R5 B J1 J2 J3 J4 J5 J6 R1 R3 R5 B
result location result location
J1 at 0.4 W J2 at 0.4 W J3 at 0.4 W J1 at 0.4 W J2 at 0.4 W J3 at 0.4 W
J4 at 0.4 W J5 at 0.5 W J6 at 0.2 W J4 at 0.4 W J5 at 0.5 W J6 at 0.2 W

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Normalized responses at each
location due to each source
200

180
normalized response [C/W], each source

J1 at 1 W
160 J2 at 1 W
J3 at 1 W
140
J4 at 1 W
120 J5 at 1 W
J6 at 1 W
100

80

60

40

20

0
J1 J2 J3 J4 J5 J6 R1 R3 R5 B
response location

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Filling in the theta-matrix

• Handy formulas for quick estimates

• Utilizing symmetry

Semiconductor Device Thermal Characterization


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Conduction resistance

basic heat transfer relationship for 1-D conduction

dT T
q k A k A
dx L

if we define
T
R
q
then
L
R
k A

Semiconductor Device Thermal Characterization


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Convection resistance

basic heat transfer relationship for surface cooling

q h A T

if we define
T
R
q
then
1
R
hA

Semiconductor Device Thermal Characterization


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Radiation resistance
basic heat transfer relationship for surface radiation
q F A (T 4 Ta4 )
F A (T 2 Ta2 )(T Ta )(T Ta )
F A (T 2 Ta2 )(T Ta ) T
if we define
T
R
q
then
1 temperatures must
R be expressed in
FA (T 2 Ta2 )(T Ta )
degrees “absolute”!

Semiconductor Device Thermal Characterization


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Thermal capacitance and time constant

Capacitance is ability to store energy Based on simple RC concept, relate


specific heat is energy storage/mass rate of storage to rate of flux,
result is
C cp V = RC

so if and if
L 1
R and C ρc p (L A ) R and C ρc p (L A )
k A h A
then then
c pL2 L2 c pL
k h

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Some useful formulas

• conduction resistance…………..……… R L
k A
• convection resistance…………...……… R 1
h A
• thermal capacitance……………...…….. C c pV

• characteristic time…………………..…. c pL2


k
– (dominated by 1-D conduction)
c pL
• characteristic time……………………...
– (dominated by 1-D convection) h
Q 2
• short-time 1-D transient response……... T t
A cp k

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Terms used in preceding formulas
• L - thermal path length
• A - thermal path cross-sectional area
• k - thermal conductivity k
• - density cp
• cp - heat capacity
• - thermal diffusivity
cpk
• - thermal effusivity
• h - convection heat-transfer “film coefficient”)
• T - junction temperature rise
• Q - heating power
• t - time since heat was first applied

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When do these effects enter?
hundreds of seconds

tens of seconds

mainly environmental
a second or so
convection and radiation effects
junction temperature

mainly local
application board
conduction effects
typical heating curve
for device on FR-4
board in still-air
mainly package time
materials/conduction effects

Semiconductor Device Thermal Characterization


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if

then and
2R

4R
Semiconductor Device Thermal Characterization
138 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Cylindrical and spherical conduction (through
radial thickness) resistance formulas

ro 1 1
ln
ri ri ro
Half-cylinder R R Hemisphere
k L 2 k
[solid angle]
[included angle]
1 1
r
ln o ri ro
Full cylinder ri R Full sphere
R 4 k
2 k L
• L – cylinder length
where • ri – inner radius
• ro – outer radius

Semiconductor Device Thermal Characterization


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Package-shrink “gotcha”

Remember how much of theta-JA depends


on what isn’t the package?
Well, what if your cooling depends significantly
on convection from the board surface
(whether free or forced air)?

q
q h A T A
h T
So never mind the package resistance, the board
can only transfer a certain amount of heat to the air:
*Special thanks to Dave Billings for the idea behind this slide

Semiconductor Device Thermal Characterization


140 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Package-shrink “gotcha”

1000 1.0qW
mm
A
2
h
1E-5 mmW2 °C T
100°C

So if 4 SOT23’s each have


1 SOT23 on a
0.25 W, then
250 mm2 spreader,
T=0.25*200=50°C
JA=200°C/W

PROBLEM:
No problem!
4 SOT23’s on a 1000 mm2
board, effective JA=400°C/W

Fortunately, 0.25 W each x 400°C/W→100°C Whew!


*Special thanks to Dave Billings for the idea behind this slide

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Package-shrink “gotcha”
NOW your favorite supplier comes out with the next
generation version (much smaller) of the same component.

SOT23
SOT23’s on a 1000 mm2
4 SOT723’s
board, JA=400°C/W,
T=100°C, power
power == 11 W
W total,
total,
0.25 W each
each
Decrease size
(but
andnot
reduce
power How many SOT723’s can you
power
dissipation)
dissipation put in that same 1000 mm2?

(RDSON or other ANSWER: 4


8
electrical
performance) 8 SOT723’s on a 1000 mm2
board, JA=800°C/W,
T=100°C, power = 1 W total,
0.125 W each
SOT723
*Special thanks to Dave Billings for the idea behind this slide

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PERIODIC and NON-PERIODIC
POWER INPUT

• Duty-cycle curves
– Normalized and non-normalized
• Linear superposition applied to time domain

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Square-wave duty cycles (aka ratios)

• What the heck are they?


– show peak junction temperature as a function of
duty cycle and “pulse width”
• Where do they come from?
– “heating curve” is equivalent to the limiting case of a
0% duty-cycle, where once the “pulse width” is over,
there’s never another cycle
– “linear superposition” allows you to generate the
whole family from the heating curve

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Representative “duty cycle” response chart

2.5
R(t), Thermal Resistance [°C/W]

1.5 d=0.5

1
0.2 0.1

0.05
0.5
Single pulse
0
0.00001 0.0001 0.001 0.01 0.1 1 10
t, time (s)

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It begins with one of these:
100 transient thermal response
for axial lead rectifier
Junction-to-Lead, 1/4" lead length

10
R(t)JL [°C/W]

0.1
0.0001 0.001 0.01 0.1 1 time [s] 10 100 1000

A “single-pulse” response is the same as a 0% duty cycle


- if you think in terms of a 0% duty cycle meaning you have
only one pulse (however long it lasts), but once you turn if
off, you never turn it back on again. So any finite “on” time
is zero percent of infinitely long “off”.
Semiconductor Device Thermal Characterization
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“published” formulas

Non-dimensionalized versions dimensionalized versions


r(t , d ) d (1 d ) * r(t ) R(t , d ) d R (1 d ) R(t )

r(t , d ) d (1 d ) * r(t p) r(t ) r( p)

t t t t
r (t , d ) d (1 d)*r t r (t ) r R(t , d ) d R (1 d) R t R(t ) R
d d d d

lim R(t , d ) d R
t 0

lim R(t , d ) R
t

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A “normalized” curve:

JL=27.4°C/W
r(t)JL [normalized]

0.1
normalized transient thermal response
for axial lead rectifier
Junction-to-Lead, 1/4" lead length

0.01
0.0001 0.001 0.01 0.1 1 time [s] 10 100 1000

Is this really such a bright idea?

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Consider this family of
“non-normalized” curves:

100 Transient thermal response for axial lead rectifier


Junction-to-Lead, varying lead length

10

R(t)-1"
R(t)JL [°C/W]

R(t)-3/8"
R(t)-1/32"
1

0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100

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The danger!
100 Transient thermal response for axial lead rectifier
Junction-to-Lead, varying lead length

10

See what R(t)JL [°C/W] R(t)-1"


R(t)-3/8"
happens to 1
R(t)-1/32"

the short-
time
response 0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100
when you
“normalize”!
1
r(t)JL [normalized]

JL-1/32"=20.0°C/W

JL-3/8"=34.9°C/W

0.1 JL-1"=54.9°C/W

normalized transient thermal response for


r(t)-1/32"
axial lead rectifier, Junction-to-Lead
0.01
r(t)-3/8" varying lead length
r(t)-1"

0.001
0.0001 0.001 0.01 0.1 time [s] 1 10 100

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Compare the families of curves:
100 square-wave duty cycles
for 1/32" lead length
Different
steady 10
single pulse
states 1% duty cycle

R(t)JL [°C/W]
2% duty cycle
5% duty cycle
1
10% duty cycle
20% duty cycle
Same short- 50% duty cycle

time 0% 0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100
(single-pulse)
100 square-wave duty cycles
for 1" lead length

10
Different single pulse
1% duty cycle
everything
R(t)JL [°C/W]

2% duty cycle

between !! 1
5% duty cycle
10% duty cycle
20% duty cycle
50% duty cycle

0.1
0.0001 0.001 0.01 0.1 time [s] 1 10 100

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What to do if you’re given a
normalized curve

• Find out what reference value


it was normalized from
– Undo it
• If you can’t find out
– Throw the curve away

Semiconductor Device Thermal Characterization


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Linear Superposition
Applied to Time Domain

Semiconductor Device Thermal Characterization


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Basic heating curve - a “single pulse”
R(t)

power input corresponding to single pulse heating curve


Semiconductor Device Thermal Characterization
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Single pulse (actually turned off)

Finite pulse, decomposed into two infinite steps


Q Q Q
equals plus
a

a t t t

Temperature response of a finite pulse


(constructed from superposition of two single pulse responses)
R(t) R(t) R(t)

plus a equals
t t t
a

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Two differing pulses

Two finite pulses decomposed into infinite steps

Q1 Q1
Q2
t a Q2 c
is made up of
a b c b -Q2 t
-Q1

Temperature response constructed for two finite pulses


(constructed from superposition of four single pulse responses)

R(t) R(t)

results in this

Semiconductor Device Thermal Characterization


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An arbitrary pulse train

• Temperature at end of nth pulse


n
Tn [
Pi R(t2 n 1 t 2i 2 ) R(t2n 1 t 2i 1 )]
i 1

Notes: times and pulses must be in


strictly increasing chronological order
P1
Pn
When there is no “off” period between
two consecutive pulses, set t 2i 2 t 2i 3
Power

P2 (i.e. do not “combine” them into a single


value)
t0 t1 t2 t3 t2n-2 t2n-1
time
For temperature at the beginning of the
nth pulse, set t 2n 1 t 2n 2

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An example

Item Value unit


P1 80 W
100

P(PK) Peak Power (Watts)


P2 40 W
P1R(t1 )
80 P1 P3
P3 70 W
60
T1
t1 0.0001 s P2
40
t3 0.0013 s
20
t3-1 0.0012 s
t3-2
t5
0.0010
0.0035
s
s
0
t0 t1 t2 1 t3 2
t, Time (ms)
3 t4 t5 4 T2 [
P1 R(t3 ) R(t3 t1 ) ]
t5-1
t5-2
0.0034
0.0032
s
s
P2 R(t3 t 2 )
Junction Temperarure

T3
t5-3 0.0022 s T1
t5-4 0.0002 s
Item Value unit
T2
T3 [
P1 R(t5 ) R(t5 t1 )]
[ ]
t0 0.0000 s
t6 0.0003 s
t0 t1 t2 1 t3 2 3 t4 t5 4
P2 R(t5 t 2 ) R(t5 t3 )
t4 0.0012 s
t, Time (ms)
P3 R(t5 t 4 )

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How to read the curve

• For small time differences, and on a low resolution


log-log plot, what can you do?

100 Transient thermal response for axial lead rectifier


Junction-to-Lead, varying lead length

10 Item Value unit


P1 80 W
R(t)-1"
R(t)JL [°C/W]

P2 40 W
P3 70 W R(t)-3/8"
R(t)-1/32"
1 t1 0.0001 s
t3 0.0013 s
t3-1 0.0012 s
t3-2 0.0010 s
0.1 t5 0.0035 s
0.0001 0.001 t5-1
0.01 0.0034 s0.1 time [s] 1 10 100
t5-2 0.0032 s
t5-3 0.0022 s
t5-4 0.0002 s

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Assume power law
(straight line on log-log plot)

t2 t1
R(t ) a t n

t1 t
R(t1 ) R(t 2 )
a n n
t1 t2 t
n n

R(t ) R(t ) R(t ) 1


t t
R(t 2 )
log
R(t1 )
n R(t ) R(t ) R(t )n
log t2 t
t1

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How to read the curve #2
• For small time differences, and on a low resolution
log-log plot, what can you do?

100 Transient thermal response for axial lead rectifier


anchors
Junction-to-Lead, varying lead length
R(.0001) 0.22
R(.02) 3.3

10
interpolate
R(t)-1"
R(t)JL [°C/W]

R(t1) 0.22 R(t)-3/8"

1
R(t3) 0.82 R(t)-1/32"
R(t3-1) 0.79
R(t3-2) 0.72
R(t5) 1.36
0.1
0.0001 0.001 0.01 0.1 time [s] 1
R(t5-1) 1.34
10 100
R(t5-2) 1.30
R(t5-3) 1.08
R(t5-4) 0.32

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Results

100
T1 P1 R(t1 ) 80 0.22 17 .6 C
P(PK) Peak Power (Watts)

80 P1 P3

60

P1[ R(t3 ) R(t3 t1 )] P2 R(t3 t 2 )


P2
40 T2
20
0 80 (0.82 0.79 ) 40 0.72
t0 t1 t2 1 t3 2 3 t4 t5 4
t, Time (ms) 2.4 28 .8 31 .2 C
Junction Temperarure

T3
T1
T2
T3 P1[ R(t5 ) R(t5 t1 )]
P2[ R(t5 t 2 ) R(t5 t3 )] P3 R(t5 t 4 )
t0 t1 t2
80 (1.36 1.34 ) 40 (1.30 1.08) 70 0.32
1 t3 2 3 t4 t5 4
t, Time (ms)
1.6 8.8 22 .4 32 .8 C

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Another transient analysis example

power
18
25.2W

23 repeat 20 times, then stop for


6800 microseconds
Here’s our
time
power input
scenario:
power
20 pulses 20 pulses
25.2W

time
802
last of 20 pulses ends 7600

Semiconductor Device Thermal Characterization


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equivalence of non-zero average response
with
(constant average) + (zero-average
disturbance)
Actual duty cycle and Superposition of average and
response disturbance
“peak”

Tavg

“valley” Tavg due to Qavg

Power shifted to
average zero
(1-d) · Q
Q
Qavg= d · Q
0 0
-d·Q

Semiconductor Device Thermal Characterization


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Another example, cont’
How do we analyze it? Over three time scales:
power
18 instantaneous excursions
25.2W based on “local” duty cycle

23 “average” Tj based average excursions based


on local avg power on “global” duty cycle
power
burst
25.2W
repeat 20 times time

time
power 7600 15200

25.2W
“average” Tj based
on global avg power

20 pulses
time
802
last of 20 pulses ends 7600

Semiconductor Device Thermal Characterization


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Endless Possibilities

Semiconductor Device Thermal Characterization


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A “ramp”

A finite ramp decomposed into several infinite steps

P P
t
is made up of
a a t

Temperature response constructed for finite ramp


(constructed from superposition of many single pulse responses)

Q Q
t results in this t

a a

Semiconductor Device Thermal Characterization


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An arbitrary pulse

An arbitrary pulse decomposed into several infinite steps


Q Q
t
is made up of
a

Temperature response constructed for this arbitrary pulse

Q Q
t results in this
t

Semiconductor Device Thermal Characterization


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Multiple Time-Varying
Heat Sources

Semiconductor Device Thermal Characterization


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Basically the same theta-matrix idea, only
now everything is a function of time as well

junction one column for


power input
temperature each heat source
vector
vector
T j1 (t ) JA1 (t ) 12 (t ) 13 (t )
T j 2 (t ) 12 (t ) JA 2 (t ) 23 (t ) q1 (t )
TxA (t ) x1 (t ) x 2 (t ) x 3 (t ) q2 (t ) one row
TL1 A (t ) L1 1 (t ) L1 2 (t ) L1 3 (t ) q3 (t ) for each
heat
TBA (t ) B1 (t ) B 2 (t ) B 3 (t )
source
one row for each temperature
location of interest
Semiconductor Device Thermal Characterization
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Each heat source Each temperature needs to be
needs to be measured whether heating itself
independently heated. or being heated by another.

Temperature (°C)
Power input (W)

Time (sec) Measurement cycle(s)

thermal system Time (sec)


boundary
*Special thanks to Dave Billings for this slide

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but first, some words about …

Thermal RC networks

• Grounded (Cauer) vs.. non-grounded


(Foster)
• Orders of magnitude, rungs
• Pulses and periodic waveforms
• Short-time behavior, limits, and limitations

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Thermal capacitance
(grounded vs.. non-grounded)

• In electrical circuit, voltage on a capacitor is


difference between its two terminals, and you have
physical access to both
• A “lumped parameter” thermal model is predicated
on energy storage being determined entirely by one
temperature
• Therefore, in a thermal circuit, you only have access
to one “terminal” of each capacitor, namely the one
where you identify the temperature. The other
terminal is “ground”.

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Models: grounded vs.. non-grounded
“Cauer” ladders “Foster” ladders

• Physical significance: if thermal capacitors are grounded,


they bear some relationship to a physical system; not so
for non-grounded C’s
• Mathematical convenience: certain non-grounded
networks are mathematically “trivial”
• Interchangeability: single-input thermal systems can be
represented as either grounded or non-grounded;
• multiple-input thermal systems are easy to model as
grounded-C networks; it can be done, though with some
intricate bookkeeping, using non-grounded-C networks

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Actual thermal RC networks
Non-grounded C vs.. grounded C comparison
“Foster” ladder Tj “Cauer” ladder Tj

1.7004 ° C/W 7.02E-04 W-sec/°C 2.3207 ° C/W 5.96E-04 W-s ec/°C

2.6627 4.41E-03 2.7397 4.20E-03

3.9740 5.89E-02 8.3551 3.67E-02

10.0255 1.55E-01 14.6949 1.01E-01

11.7747 6.03E-01 21.0538 4.13E-01

35.3008 1.46E+00
39.637 9.20E-01

33.1212 4.16E+00
9.7581 1.14E+01

Ta Ta

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2-rung Foster model

1
1
R1 C1 R1 sC1
1
sC1 R1

R1 R2
R1C1 s 1 R2 C2 s 1

1 R2
R2 C2 R2 sC2 R2 C2 s 1

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2-rung Cauer model

C1 1 1
R1 R1 R1
sC1 sC1

C2 1 R2
R2
R2 sC2 R2 C2 s 1

1
R2 1 1 R1 R2 C2 s R1 R2
R1 sC1
R1C1 R2 C2 s
2
R1C1 R2 C1 R2 C2 s 1
R2 C2 s 1 sC1 R1
R2
R2 C2 s 1

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2-rung models compared
• Time constants are roots of denominators
• "tau" is not RC product when capacitors are grounded !

non-grounded grounded-capacitors: (Cauer)


capacitors: R1 R2
s
(Foster) R1 R2 C2 s R1 R2 1 R1 R2 C 2
2 can be written
R1C1 R2 C2 s R1C1 R2 C1 R2 C2 s 1 C1 1 1
s s
1 2
R1 R2 where time constants are
R1C1 s 1 R2 C2 s 1 2 R1 C1
1 2
can be written 1
c c
2
c r c R1C1 R2C2
1 c 1 c 4
1 1 1 1 r r r
C1 s 1 C2 s 1 100 0.01 0.99 1.01
2 R2 C2 10 0.1 0.91 1.10
1 2 2 2
r r r 3 1 /3 0.73 1.36
1 r 1 r 4
c c c
where time constants are 1 0.1 0.90 1.11
1 R1C1 2 R2 C2
and defining r
R2
c
C1 1 1 0.38 2.62
R1 C2

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Interesting (and important) implications
“Foster” ladder “Cauer” ladder
Rungs can be in any order Order matters, so a “split” can
and Tj has identical behavior! make good physical
Tj sense.
So where do you “split” it?
Tj
2.3207 ° C/W 5.96E-04 W-s ec/°C

1.7004 ° C/W 7.02E-04 W-sec/°C package


2.7397 4.20E-03
2.6627 4.41E-03
8.3551 3.67E-02
3.9740 5.89E-02

10.0255 1.55E-01 ?? 14.6949 1.01E-01

11.7747 6.03E-01
21.0538 4.13E-01
environment
35.3008 1.46E+00
39.637 9.20E-01
33.1212 4.16E+00

9.7581 1.14E+01
Ta
Ta

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Orders of magnitude and rungs

• It is a rare transient curve that cannot be followed very


accurately with time constants no closer than about 1
order of magnitude apart. This means that you need
only about one rung per decade of transient response.

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For what it’s worth ...

Every Cauer (grounded-capacitor) ladder has a


mathematical solution. By definition, its
mathematical solution represents a corresponding
Foster (non-grounded-capacitor) ladder.

Every Foster (non-grounded-capacitor) ladder having


distinct (i.e. non-repeated) time constants, has a
corresponding Cauer (grounded-capacitor)
equivalent. (However, there is no a priori guarantee
that all R’s and C’s will be positive!)

Ref: L. Weinberg, Network Analysis and Synthesis, McGraw Hill Book Company, Inc., 1962

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RC network math

Cauer ladder continued fraction:


1
Z
sC1
1 with some
1
R1
1
algebra, both
sC 2 may be written:
1
R2 ...
... Nn s
Z
Foster ladder, Dn 1 s

sum of simple fractions:


R1 R2 Ri
Z ... ...
R1C1s 1 R2 C 2 s 1 Ri Ci s 1

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Arbitrary repetitive pulse

t
p 2p

p – period of waveform

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Generalized periodic square wave
So consider a general rectangular pulse positioned arbitrarily within a
repetitive cycle of period p. We can derive expressions for the
infinite sum of responses in three regions : m t a

R(t ) Ri 1 e i

i 1
Q t – arbitrary time of interest t a jp

Fi (t ) Ri 1 e i

j 1

m t

R(t ) Ri 1 e i

i 1
p 2p
t′ – measured from edge
of power step
b – pulse turns off
a – pulse turns on m t b

R(t ) Ri 1 e i

i 1

t b jp

0 t a b t p Fi (t ) Ri 1 e i

a t b j 1

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Infinite summation

1 j 1
Utilizing the identities zj and z
j 0 1 z j 1 z 1

and doing some algebra, we can show these results:

0 t a a t b b t p
b t p a t p b t p a t b t a t

e i
e i
e i
e i
e i
e i

Fi (t ) Ri p
Fi (t ) Ri 1 p
Fi (t ) Ri p

1 e i
1 e i
1 e i

In each domain, we then sum over m


all rungs of the Foster model: F (t ) Fi (t )
i 1

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RCEnd
Model for Multiple
result Square periodic
for arbitrary Waves in power
One Cycle

An important point of this


example is that for complex
power inputs, absolute peak
temperatures do not always
correspond to the ends of
the highest power pulse!

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Short-time limits
• What do RC models do at shortest time?
– roll off linearly with time
t t

R(t ) R1 1 e 1
R2 1 e 2

t t2 t t2
R1 1 1 2
 R2 1 1 2
 
1 21 2 2 2
t t2 t t2
R1 2
 R1 2
 
1 21 1 21

R1 R2 R1 R2 t2 So for small t:
R(t ) t 2 2
 
1 2 1 2
2 R(t ) (const) t

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RC models and Surface Heating

• It turns out that if R’s and C’s grow at a uniform ratio, a


sqrt(t) behavior ( b t ) is approached in the limit

• If ratio is 1:3 (increasing with “distance” from junction


node), rung-to-rung time constant ratio will be about
one order of magnitude, and the network will follow
theoretical sqrt(t) within a few percent

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Rungs vs.. sqrt(t) behavior
1.0E+0

Exact sqrt(t) model

1.0E-1

1.0E-2

1 rung

1.0E-3 2 rungs @ 3.0:1


3 rungs @ 3.0:1
4 rungs @ 3.0:1
5 rungs @ 3.0:1
1.0E-4
1.0E-8 1.0E-7 1.0E-6 1.0E-5 1.0E-4 1.0E-3 1.0E-2 1.0E-1 1.0E+0 1.0E+1

Semiconductor Device Thermal Characterization


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Where does that leave us with respect to
the applicability of RC networks?
• We need to pay attention to silicon thickness vs..
device “technology”
– if surface heating is a good model, be sure your RC network
has time constants short enough to land “within” the silicon

L2
– within the silicon timescale , if surface heating is a good
model, you have to “extend” the RC network into that region

– on the other hand, if surface heating is not a good model


(implying that volumetric heating is better), the fastest rung of
your RC network can be set to the actual R&C corresponding
to the volume being heated

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Multiple heat-source RC networks

• You need data (experiment or simulation)


• Fit an RC network (or networks) to the data
– Foster networks, we’ll see an Excel-based approach
– Cauer networks, beyond the scope of this tutorial
• Using SPICE: directly input your RC networks
– Foster networks can be complicated
– Cauer networks are straightforward
• Using Excel:
– Foster networks, we’ll see an Excel-based approach
– Cauer networks are not practical

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Typical 2-input heating/response curves
250
q1 self avg
q2 self avg
interact
200
q1 RC-fit
q1
q2 RC-fit
R(t) [C/W] q1<->q2 fit
150

100

q2 50

0
1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3
heating time [s]

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Fitting Foster ladders in Excel

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Using RMSE as fitting parameter
A B C D E F G H I J K L
1 RMSE 1.9 1.3 0.5
2 test pow er [W] 1.00 1.00 1.00 TABLE 1: Foster model
3 q1 self q2 self q1 RC- q2 RC- q1<- interact
Time avg avg interact fit fit >q2 fit taus q1 R's q2 R's R's
4 1.26E-4 8.48 1.16 0.00 9.18 1.01 -0.03 1.0E-4 11.2 0.8 -0.1
5 1.64E-4 9.68 1.32 0.00 10.51 1.20 -0.03 1.0E-3 7.6 2.9 0.3
6 2.09E-4 10.59 1.50 0.00 11.67 1.40 -0.03 1.0E-2 12.5 2.3 -0.7
7 2.60E-4 11.82 1.67 0.00 12.63 1.59 -0.03 1.0E-1 76.6 45.6 -2.3
8 3.18E-4 14.14 1.84 0.00 13.45 1.79 -0.02 1.0E+0 70.0 67.5 38.4
9 3.82E-4 14.64 2.02 0.00 14.14 1.98 -0.01 1.0E+1 2.3 2.2 4.0
10 4.58E-4 15.37 2.21 0.00 14.80 2.19 0.00 1.0E+2 41.0 37.7 34.1
11 5.48E-4 15.87 2.42 0.00 15.46 2.41 0.01
12 6.57E-4 16.37 2.65 0.00 16.16 2.67 0.02 {=SQRT(SUMSQ(E4:E100-
TABLE 5: results at arbitrary times
13 7.78E-4 16.98 2.89 0.00 16.86 2.92 0.03 B4:B100)/COUNT(E4:E100))}
120.5 100.7
14 9.19E-4 18.45 3.14 0.00 17.60 3.20 0.04 0.00 25.0 25.0
{=$G$2*SUM(interact_Rs
15 1.09E-3 18.58 3.17 0.00 18.39 3.50 0.04 *(1-EXP(-A4/taus)))}
0.01 59.6 30.0
16 1.28E-3 20.29 3.76 0.00 19.21 3.80 0.05 0.05 90.0 39.1

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Excel’s “Solver”
Use Excel’s “solver” to 1000 0.6

minimize the error between the 0.4

input data and the RC model. 100


0.2

Fit error (C/W)


0

R(t) (C/W)
-0.2
10
-0.4

-0.6

1
Simlation data -0.8
R-C model
Fit Error -1

0.1 -1.2
Simulation data
1E- 1E- 1E- 0.001 0.01 0.1 1 10 100 1000
06 05 04
Time (sec)

After optimization

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Using SPICE to exercise the models

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Using Foster RC models in SPICE

Tself1 (volts) Tself2 (volts)

Q1 (amps)

+
Tj1 Tj2

-
Tpos2 Tpos1
time

Tneg2 Tneg1

Q2 (amps)

time

different networks identical networks of identical networks of


of self heating positive interaction negative interaction
elements elements elements

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1/4th of a 4-input Foster RC SPICE model

Piecewise linear current source for power input from


each source generating heat.

Summing tool to add voltages from the separate


interaction networks with the self heating network

Thermal equivalent Foster RC networks


(note that all these R’s are positive)

The output port (OUT1) will be where you want to


monitor the temperature response

Each heat source will require a similar block in order to


simulate the temperature response of the self heating
effect as well as the interactions.

Thermal ground – by adding a voltage potential to the


ground point ambient temperature can be added.

*Special thanks to Dave Billings for this slide

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A 2-input Cauer network model

Tj1 Tj2 Apply q1 to Tj1 node


C11 C21 q1 (watts)
R11 R21
C12 C22
R12 R22
R33 C23
C13
R13 R23
R44 time
C14
C24
R14 R24
C5
R5 q2 (watts) Apply q2 to Tj2 node
C6
R6

C7
R7
time

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Using Excel to exercise Foster models

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Setting up a 2-input Excel model
I J K L M N O P Q R S T U V W X Y Z
1 ambient 25
2 TABLE 1: Foster model TABLE 2: pow er input vs time
3 interact
taus q1 R's q2 R's R's t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
4 1.0E-4 11.2 0.8 -0.1 change_at 0.00 0.10 0.25 0.40 1.00 1.10 1.50 2.00 2.60 3.00 5.00 10.00
5 1.0E-3 7.6 2.9 0.3 q1_pow er 1.0 1.0 0.0 0.8 0.8 0.0 0.0 0.0 0.0 0.6 0.6 0.0
6 1.0E-2 12.5 2.3 -0.7 q2_pow er 0.5 0.0 1.3 0.9 0.0 0.0 1.0 0.0 0.4 0.4 0.7 0.7
7 1.0E-1 76.6 45.6 -2.3 delta q1 1.0 0.0 -1.0 0.8 0.0 -0.8 0.0 0.0 0.0 0.6 0.0 -0.6
8 1.0E+0 70.0 67.5 38.4 delta q2 0.5 -0.5 1.3 -0.4 -0.9 0.0 1.0 -1.0 0.4 0.0 0.3 0.0
9 1.0E+1 2.3 2.2 4.0
10 1.0E+2 41.0 37.7 34.1 time TABLE 3: unit step relative to chosen time
11 0.5 0.50 0.40 0.25 0.10 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
12 TABLE 5: results at arbitrary times TABLE 4: sum of terms
13 120.5 100.7 T1_terms 141.5 -5.1 -109.3 68.4 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
14 0.00 25.0 25.0 T2_terms 51.7 -36.6 75.7 -15.1 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
15 0.01 59.6 30.0
16 0.05 90.0 39.1 Tj1
=SUM(T2_terms)+ambient {=IF(time>change_at,time-change_at,0)}
180 1.4
17 0.10 112.2 47.4 Tj2
{=SUM((S7*q1_Rs+S8*interact_Rs)*
18 0.25 143.6 37.1 160 q1_pow er (1-EXP(-time/taus)))} 1.2
19 0.26 116.5 46.3 q2_pow er
20 0.26 110.0 50.3 140 {=SUM((R7*interact_Rs+R8*q2_Rs)*(1-EXP(-time/taus)))}
21 0.27 101.0 56.9 1
22 =SUM(T1_terms)+ambient
0.29 89.2 67.4 120
{=TABLE(,time)}
perature [C]

100 0.8
Semiconductor Device Thermal Characterization
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80
Results from a 2-input Excel Foster model
Tj1
180.0 1.40
Tj2
160.0 q1_pow er
1.20
q2_pow er
140.0
1.00
120.0
temperature [C]

power [W]
100.0 0.80

80.0 0.60

60.0
0.40
40.0

0.20
20.0

0.0 0.00
0 1 2 3 4 5 6
tim e [s]

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Organizing the sheet for transient solution

A cell for
keeping
track of the
overall time
=IF(Master_Time>Row_Time,Master_time-Row_time,0)
progression
of ALL
blocks.

Self heating column (each cell is a separate array formula)


{=dP-D#*SUM(R1:R10*(1-EXP(-dtime/Tau1:Tau10)))}

Interaction heated columns (each cell is a separate array formula)


{=dP-D#*SUM(R5:R10*(1-EXP(-dtime/Tau5:Tau10)))}

A section for power input A section A section for A section for


to the heat sources for Time power Temperature response
changes
*Special thanks to Dave Billings for this slide changes calculation
Semiconductor Device Thermal Characterization
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Table for plotting temperature output

=SUM(D1:D1_by_D4) +T_ambient

Note!
Time in this column
can be independent of
the time values in the
power input section

Next, Select this


whole region

Apply a
Data > Table option

*Special thanks to Dave Billings for this slide

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Results from a 4-input Excel Foster model
1.4 D1 3
T_D1

Temperature (C)
1.2 T_D2
Power (W)

2.5
1
2 T_D3
0.8
0.6 1.5 T_D4
0.4 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3

1.4 D2 3

Temperature (C)
1.2 Last
Power (W)

2.5
1
0.8 power 2
0.6 1.5
0.4 input 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3

1.4 D3 3

Temperature (C)
1.2
Power (W)

2.5
1
0.8 2
0.6 1.5
0.4 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3

1.4 D4 3
Temperature (C)

1.2
Power (W)

1 2.5
0.8 2
0.6 1.5
0.4 1
0.2 0.5
0 0
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1
Time (Sec) Time (Sec) 0.15 0.2 0.25 0.3

*Special thanks to Dave Billings for this slide

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Recap
• With the right tools, a thermal RC network can be
generated from temperature data which is captured
from measurements or finite element simulation.

• Linear superposition provides a method for generating


transient thermal models with several heat sources.

• Foster networks can be used to simulate the thermal


response of a system using a spreadsheet, whereas
Cauer networks (which are closer to a physical lumped
system) may require special tools (e.g. SPICE).

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Part III

Thermal Runaway

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Thermal runaway

• Non-linear power vs.. junction temperature device


characteristic

• System thermal resistance isn’t low enough to shed


small perturbations

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A linear thermal cooling system

TJ Q Tx junction temperature as function


Jx
of power, theta, and ground

TJ Tx
Q … solving for power
Jx

dQ 1 sensitivity (slope) of power with


dT respect to temperature
Jx

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Effect of device line slope on system stability
system line

power

tendency
to cool
Q
tendency
to heat device line

junction temperature
Tx TJ

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Operating points of thermal system when
device line has negative second derivative
power system line tendency
to cool
the stable (that is,
device line
real) operating point
Q2 power goes up with
increasing temperature
an unachievable
operating point but rate of increase
system falls with increase
temperature
tendency (negative second
cannot
to heat be
system cannot
derivative)
maintained
be successfully
Q1 powered up
tendency
to cool
junction temperature
TJ1 TJ2
Tx

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Operating points of thermal system when
device line has positive second derivative
tendency
to heat
power system line
an unachievable
operating point
even turning any
the device on tendency
perturbation
destroys
the stable it cause
will to cool device line
(that is, real)
runaway power goes up with
operating increasing temperature,
point but rate of increase rises
with increase (positive
second derivative)
Q
tendency
to heat junction temperature
Tx TJ

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Let’s see how it works
stable unstable operating point
operating
2.0
point

device 1.6

operating
Device Power Dissipation [W]

curve
1.2

10°C/W NO
0.8
system operating
point!
0.4
25°C/W
system

40°C/W 0.0
20 40 60 80 100
system Junction Temperature [C]

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A paradox
0.5 W 0.5 W
Case A Case B

100°C junction 100°C junction


identical

50°C/W 50°C/W

75°C lead 75°C lead

100°C/W 0.2°C/W

25°C thermal ground 74.9°C thermal ground

thermal runaway, thermal runaway,


based on Jx=150°C/W, based on Jx=50.2°C/W,
calculated to be at 125°C calculated to be at 150°C

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Paradox lost
raise the power by 0.1 W and see what happens
0.5 W
+ 0.1 0.5 W
+ 0.1

Case A Case B
100 °C
+ 15 junction 100 °C
+ 5.02junction

50°C/W 50°C/W

75 °C
+ 10 lead 75 °C
+ 0.02lead

100°C/W 0.2°C/W

(fixed) 25°C (fixed) 74.9°C

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Illustrating the paradox

Case B
device
line
Case A
common nominal
operating point

0.5 W

25°C 74.9°C 100°C

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Generic power law device and
generic linear cooling system
device system line A
power unstable line system line B
operating system
point 1 line C
Jx1 Jx1 1
Jx2
stable 1
operating runaway point for
point original theta
runaway point for
original thermal ground
Q

junction temperature
Tx TJ Ty TR2 TR1

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Don’t get confused by the terms!

a
device mathematical
power “power law”
y ax
Q V I
an “exponential”
power law (base is e)

y ex

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Definition of power law device
rule of thumb for leakage;
2x increase for every 10°C for constant voltage, power
T does the same
I Io 2 10 T T
T
T 10 Q VRIo e Qo e
( ln 2 )
10 ln 2
I Io e Io e
1st and 2nd derivatives
T
I Io e T 2 T
dQ Qo d Q Qo
T1 T2 e 2 2
e
defining: dT dT
I
ln 1
I2 both always positive
Semiconductor Device Thermal Characterization
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The mathematical essence
Leads to:
System line
Non-dimensionalizing (system)
T Tx q kz
Q
Jx T Tx
z temperature where: Tx
Power law k e
device line Tx JxQo
1
T q e Q power (power law device)
Qo
Q Qo e q ez

Eliminating q: kz ez

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Perfect runaway transformed

ez

at point of tangency,
slope equals height k=ez

k=ez

k=ez
k=ez
T Tx
z
z0 zTz 1 z zT
1 0 0 1 z0 zT zT
1
zT z0 1

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Transforming the nominal system

ez nominal
“operating” system line A
points
k>e
(2 intersections)

k<e
(no intersections)

at point of
tangency, slope
k=e equals height

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Everything transformed
non-dimensional device line
power system line A q=k1z
q=ez
unstable, system line B
non-operating q=k1(z-zx1)
point
1
system line C
stable k1 q=k2z
operating
point

runaway point for


k2 e
original theta
k1 runaway point for
k2 original thermal ground
non-dimensional temperature
1 1
zx1 zR2 zR1
z x1 ln(k1) 1 z R 2 1 zR1 ln(k1)

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“Perfect runaway” results
in original terms

runaway temperature runaway temperature


based on original slope based on original ambient

TR1 ln TR2 Tx
Jx1Q o

max ambient that system resistance


goes with it that goes with it
Tx
1
Tx1 ln Jx2 e
Jx1Q o Qo

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The “operating” points
ez

“operating” kz
points
unstable kzu e zu

stable

1 kzs e zs

zs zu

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Newton’s method for the intersections
kz ez k
ln z i
F(zi ) ln kz z e
zi zi zi 1
1 1
F (z i ) F(z) z ln kz 1
zi
1
F ( z) 1
z

For k/e ranging between 1.01 and 1000, convergence is


to a dozen significant digits in fewer than 10 iterations.

1 1 this initial guess this initial guess


zo k
k k converges to lower, converges to upper, z o ln k 1 ln
e e
e stable point unstable point

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And the intersection points come from

find the non-dimensional intersections first,


then

Tstable Tx z stable

Tunstable Tx z unstable

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Real datasheet example

raw device data† the device power curve parameters


Vr [V] 12 40 @12V @40V
Tmax [°C] 125 125
[°C] 17.9 17.8
Tref [°C] 75 75
Q o [W] 9.4E-5 1.02E-3
Itmax [A] 8.50E-3 2.80E-2
Itref [A] 5.20E-4 1.70E-3
Tmax Tref rule of thumb
gave us: 10
T I 14.4
ln max ln (2)
I I0 e Iref

Tmax Tref
I0 It max e Itref e Q0 VRIo

† MBRS140T3

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Runaway analysis in nominal system
computed results
raw device data† @12V @40V @40V

Vr [V] 12 40 [°C] 17.9 17.8


Tmax [°C] 125 125 Q o [W] 9.4E-5 1.02E-3
Tref [°C] 75 75
k (compare to unity)
Itmax [A] 8.50E-3 2.80E-2 e 10.6 0.97 1.609
Itref [A] 5.20E-4 1.70E-3 given Tx max [°C] 117.2 74.4 83.5
theta TR1[°C] 135.1 92.2 101.3
Tx
k 1
given Jx 2 max [°C/W] 1055 96.6
e Tx 75 ambient
e JxQo TR 2[°C] 92.9 92.8

Jx1 100 Jx1 60


These translate into:
a stable operating point at 80.6°C (and 0.09 W), z 0.312
† MBRS140T3 an unstable point at 116.3°C (0.69 W) z 2.315

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HTRB example

• Bidirectional Thyristor in reliability MT1


stress test (High Temperature +
G

Reverse Bias) 640 V MT2

• Goal is life tests at elevated -


40 kΩ
temperature (say 125°C)

• Problem is, they don’t last very long,


and if junction temperature is
anything like the chamber
temperature, they appear to fail way
HTRB test circuit
too early good!

*Special acknowledgements to Dave Billings and Geoff Garcia for their contributions to this project

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HTRB DUTHTRB
tabdatatemperature vs.. test time
- sockets without heatsinks

200

180
Heatsink (tab) temperature [degC]

160 DUT T1
140 DUT T2
DUT T3
120 DUT T4
DUT T5
100
DUT T6
80 DUT T7
DUT T8
60
DUT T9
40 DUT T10

20

0
0 2000 4000 6000 8000 10000 12000
test time [s]
Semiconductor Device Thermal Characterization
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HTRB data - sockets without heatsinks
HTRB DUT power vs.. test time
3

2.5
DUT W1
DUT W2
2 DUT W3
DUT Power [W]

DUT W4
DUT W5
1.5
DUT W6
DUT W7
1 DUT W8
DUT W9
DUT W10
0.5

0
0 2000 4000 6000 8000 10000 12000
test time [s]

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HTRB example

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Quick calculations from datasheet
Pd I (640 40000 I )
MT1
TJ Ta Pd JA +
G
or

TJ THS Pd J HS
640 V MT2
-
40 kΩ
• At room temp, if IDRM is 5 uA, then Pd is about zero (≈3mW),
and TJ should thus equal chamber set point.
• At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of
0.1W, so depending on theta-JA, TJ could be several
degrees hotter than chamber set point (note, however, that
TJ will still be well within 1°C of heatsink temperature, THS)
• HOWEVER, at 125°C, if IDRM is 2mA, then Pd will be in
HTRB test circuit
excess of 1W. Depending on theta-JA, TJ could be 30-60°C
above chamber set point (though still within a couple of
degrees of heatsink temperature, if known).

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Calculations based on actual measurements
Pd I (640 41000 I )
MT1
TJ Ta Pd JA +
G
Vsense or
I
1000 TJ THS Pd J HS
640 V MT2
-
• At room temp, IDRM (via Vsense) is 0.2uA, thus Pd is about 40 kΩ
zero (≈0.1mW), and TJ should thus equal chamber set
point. +

• At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of Vsense 1 kΩ


0.1W, so depending on theta-JA, TJ could be several
degrees hotter than chamber set point (note, however, that -
TJ will still be well within 1°C of heatsink temperature, THS)
• At 125°C, IDRM is 2-3mA; Pd could be as high as 1.5W Modified HTRB
test circuit
• Max current observed was nearly 8mA (for Pd of 2.5W),
and estimated TJ of 170°C just prior to device failure.

Semiconductor Device Thermal Characterization


235 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Actual “blocking current” data (time implicit)
blocking current when theta-JA=35°C/W (DUT's in unmodified HTRB board)
1E-2

1E-3

DUT I1
DUT I2
1E-4
DUT I3
DUT I4
DUT I5
1E-5 DUT I6
DUT I7
DUT I8
DUT I9
1E-6 current

1E-7
20 40 60 80 100 120 140 160
estimated junction temperature [°C]

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236 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Actual “blocking Pd” data (time implicit)
blocking Pd when theta-JA=35°C/W (DUT's in unmodified HTRB board)
1E+1

1E+0

1E-1 DUT W1
DUT W2
DUT W3
DUT W4
1E-2 DUT W5
DUT W6
DUT W7
DUT W8
1E-3
DUT W9
power

1E-4
20 40 60 80 100 120 140 160
estimated junction temperature [°C]

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Power vs.. temperature (linear scales)

2.5
DUT W1

2 DUT W2
DUT W3

1.5 DUT W4
Pd [W]

DUT W5
DUT W6
1
DUT W7 37°C/W
system
DUT W8 4°C/W
0.5 system
DUT W9 10°C/
W
0 system

20 30 40 50 60 70 80 90 100 110 120 130


estimated junction temperature [°C]

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Proof-of-concept modified HTRB fixture

Semiconductor Device Thermal Characterization


239 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Pd vs.. temperature on better heatsinks
blocking current when theta-JA=10°C/W (using external 12°C/W heatsink)
1E-2

1E-3

DUT I1
DUT I2
1E-4
DUT I3
DUT I4
DUT I5
DUT I6
1E-5
DUT I7
DUT I8
DUT I9
1E-6

1E-7
20 40 60 80 100 120 140 160
estimated junction temperature [°C]

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Semiconductor Device Thermal Characterization
241 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
What if multiple devices on heatsink?
• Each device heats its neighbors to varying
degrees, depending on distance

• This adds background heat, that


is, it raises the “effective ambient”
of each device

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Graphically, background heat does this
2.0

real
runaway
device 1.6
margin
operating what you
Device Power Dissipation [W]

curve thought
1.2
was your
margin
0.8

system with
“background
25°C/W 0.4 heating” of
system other
ij Qi devices
0.0 i j
20 40 60 80 100
Junction Temperature [C]

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Math and Electrical References Thermal-Related Applications Notes available at
1. M. Abramowitz, I. Stegun (eds), Handbook of http://www.onsemi.com/pub/Collateral/ANxxxx-D.PDF
Mathematical Functions, Dover Publications, Inc.,
569: “Transient Thermal Resistance - General Data and its Use,” May
9th Printing, Dec. 1972
2003
2. S.D. Senturia, B.D. Wedlock, Electronic Circuits
1083: “Basic Thermal Management of Power Semiconductors,”
and Applications, John Wiley & Sons, 1975
October 2003
3. M.F. Gardner & J.L. Barnes, Transients in Linear
1570: “Basic Semiconductor Thermal Management,” January 2004
Systems (Studied by the Laplace Transformation),
Vol. I, John Wiley and Sons, 1942 8044: “Single-Channel 1206A ChipFET™ Power MOSFET
Recommended Pad Pattern and Thermal Performance,”
4. R.S. Muller, T.I. Kamins, Device Electronics for
December 2005
Integrated Circuits, 2nd Ed., John Wiley & Sons,
1986 8072: “Thermal Analysis and Reliability of WIRE BONDED ECL,” April
2006
5. Ben Nobel, Applied Linear Algebra, Prentice Hall,
1969 8080: “TSOP vs.. SC70 Leadless Package Thermal Performance,”
January 2004
6. H.H. Skilling, Electric Networks, John Wiley and
Sons, 1974 8199: “Thermal Stability of MOSFETs,” August 2005
7. L. Weinberg, Network Analysis and Synthesis, 8214: “General Thermal Transient RC Networks ,” April 2006
McGraw Hill Book Company, Inc., 1962 8215: “Semiconductor Package Thermal Characterization,” April 2006
8. H. Wayland, Complex Variables Applied in Science 8216: “Minimizing Scatter in Experimental Data Sets,” April 2006
and Engineering, Van Nostrand Reinhold Company 8217: “What's Wrong with %Error in Junction Temperature,” April 2006
8218: “How to Extend a Thermal - RC - Network Model,” April 2006
Thermal Textbooks & References 8219: “How to Generate Square Wave, Constant Duty Cycle, Thermal
9. H.S. Carslaw & J.C. Jaeger, Conduction of Heat In Transient Response Curves,” April 2006
Solids, Oxford Press, 1959 8220: “How To Use Thermal Data Found in Data Sheets,” April 2006
10. E.R.G. Eckert & R.M. Drake Jr., Heat and Mass 8221: “Thermal RC Ladder Networks,” April 2006
Transfer, McGraw Hill, 1959 8222: “Predicting the Effect of Circuit Boards on Semiconductor
11. J.P. Holman, Heat Transfer, 3rd Ed., McGraw Hill, Package Thermal Performance,” April 2006
1972 8223: “Predicting Thermal Runaway,” April 2006
12. J. VanSant, Conduction Heat Transfer Solutions, 8402: “Thermal Considerations for the NCS5650”, June 2009
Lawrence Livermore National Laboratory,
Livermore, CA, 1980 8432: “Thermal Consideration for a 4x4 mm QFN”, December 2009

Semiconductor Device Thermal Characterization


244 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Thermal Test Standards
1. EIA/JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method
Environmental Conditions - Natural Convection (Still Air), Electronic Industries
Alliance, December 1995
2. EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions - Forced Convection (Moving Air), Electronic Industries
Alliance, March 1999
3. EIA/JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method
Environmental Conditions - Junction-to-Board, Electronic Industries Alliance,
October 1999
4. EIA/JEDEC Standard JESD51-12, Guidelines for Reporting and Using
Electronic Package Thermal Information - Electronic Industries Alliance,
May 2005
5. JEDEC Standards No. 24-3, 24-4, 51-1, Electronic Industries Alliance, 1990
6. MIL-STD-883E, Method 1012.1, U.S. Department of Defense, 31 December 1996

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245 and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology
Related Papers by Stout, et al
1. “Two-Dimensional Axisymmetric ANSYS® Simulation for Two- 12.“Part 2:Linear Superposition Speeds Thermal Modeling,” Power
Parameter Thermal Models of Semiconductor Packages,” 7th Electronics Technology, February 2007, R.P. Stout
International ANSYS Conference & Exhibition, May 1996, R.P. 13.“Power Electronics System Thermal Design: Linear
Stout & R.L. Coronado Superposition,” IEEE Expert Now on-line tutorial
2. “End User's Method for Estimating Junction Temperatures Due to <http://ieeexplore.ieee.org/articleSale/modulesabstract.jsp?mdnu
Interactions of Other Dominant Heat Sources in Close Proximity to mber=EW1054>, February 2007, Roger Stout
the Device in Question,” ITHERM, May 1996, D.T. Billings & R.P. 14.“Power Electronics System Thermal Design: Thermal Runaway,”
Stout IEEE Expert Now on-line tutorial
3. “Evaluation of Isothermal and Isoflux Natural Convection <http://ieeexplore.ieee.org/articleSale/modulesabstract.jsp?mdnu
Coefficient Correlations for Utilization in Electronic Package Level mber=EW1055>, February 2007, Roger Stout
Thermal Analysis,” 13th Annual IEEE Semiconductor Thermal 15.“Using Linear Superposition to Understand the True Meaning of
Measurement and Management Symposium, January 1997, B.A. Theta-JA,” 12th Annual Automotive Electronics Council Reliability
Zahn and R.P. Stout Workshop, May 2007, R.P. Stout
4. "Electrical Package Thermal Response Prediction to Power 16.“Using Linear Superposition to Solve Multiple Heat Source
Surge", ITHERM, May 2000, Y.L. Xu, R.P. Stout, D.T. Billings Transient Thermal Problems,” InterPACK 2007, July 2007, D.T.
5. “Accuracy and Time Resolution in Thermal Transient Finite Billings, R.P. Stout
Element Analysis,” ANSYS 2002 Conference & Exhibition, April 17.“Linear Superposition and the True Meaning of Theta-JA,” 1-hr
2002, R.P. Stout & D.T. Billings Seminar at 2007 Power Electronics Technology Exhibition and
6. “Minimizing Scatter in Experimental Data Sets,” ITHERM 2002 Conference, October 2007, R.P. Stout
(Eighth Intersociety Conference on Thermal and
Thermomechanical Phenomena in Electronic Systems), June 18.“Thermal Performance of a Monolithic Thin-Shell Concrete
2002, R.P. Stout Dome,” ASME Heat Transfer Conference, July 2007, R.P. Stout
7. “Combining Experiment and FEA into One, in Device 19.“Beyond the Datasheet: Demystifying Thermal Runaway,” Power
Characterization,” ITHERM 2002 (Eighth Intersociety Conference Electronics Technology, November 2007, R.P. Stout
on Thermal and Thermomechanical Phenomena in Electronic 20.“The Datasheet is Not Your Mother” (Executive Viewpoint article
Systems), June 2002, R.P. Stout, D.T. Billings for) Power Electronics Technology, February 2008, R.P. Stout
8. “A Two-Port Analytical Board Model,” ITHERM 2002 (Eighth 21.“Psi or Theta: Which One Should You Choose?” Power
Intersociety Conference on Thermal and Thermomechanical Electronics Technology, March 2008, R.P. Stout
Phenomena in Electronic Systems), June 2002, R.P. Stout 22.“Don’t Be Misled By Power Device Specs” Power Electronics
9. “On the Treatment of Circuit Boards as Thermal Two-Ports,” Technology, May 2008, R.P. Stout
InterPack2003, July 2003, R.P. Stout 23.“Reliability of NLDMOS Transistors Subjected to Repetitive
10.“A Conjugate Numerical-RC Network Prediction of the Transient Power Pulses,” IEEE International Reliability Physics
Thermal Response of a Power Amplifier Module in Handheld Symposium, April 2008, Poster Session paper, Chris Kendrick,
Telecommunication,” InterPACK 2005, July 2005, T.Y. Lee, V.A. Roger Stout, and Michael Cook
Chiriac, R.P. Stout
11.“Part 1:Linear Superposition Speeds Thermal Modeling,” Power
Electronics Technology, January 2007, R.P. Stout

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