2694

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 7, JULY 2008

Transformerless Single-Phase Multilevel-Based

Photovoltaic Inverter
Roberto Gonzlez, Eugenio Guba, Member, IEEE, Jess Lpez, Member, IEEE, and
Luis Marroyo, Member, IEEE

AbstractThe elimination of the output transformer from gridconnected photovoltaic (PV) systems not only reduces the cost,
size, and weight of the conversion stage but also increases the
system overall efficiency. However, if the transformer is removed,
the galvanic isolation between the PV generator and the grid is
lost. This may cause safety hazards in the event of ground faults.
In addition, the circulation of leakage currents (common-mode
currents) through the stray capacitance between the PV array and
the ground would be enabled. Furthermore, when no transformer
is used, the inverter could inject direct current (dc) to the grid,
causing the saturation of the transformers along the distribution
network. While safety requirements in transformerless systems
can be met by means of external elements, leakage currents and
the injection of dc into the grid must be guaranteed topologically
or by the inverters control system. This paper proposes a new
high-efficiency topology for transformerless systems, which does
not generate common-mode currents and topologically guarantees
that no dc is injected into the grid. The proposed topology has been
verified in a 5-kW prototype with satisfactory results.
Index TermsDirect current (dc)alternating current (ac)
power conversion, half bridge, photovoltaic (PV) systems,
single-phase three-level diode-clamped inverter, transformerless
inverter.

I. I NTRODUCTION

RID-CONNECTED photovoltaic (PV) systems often include a line transformer between the conversion stage and
the grid. The transformer guarantees galvanic isolation between
the grid and the PV system, thus fulfilling safety standards.
Furthermore, it significantly reduces leakage currents between
the PV system and the ground and ensures that no direct
current (dc) is injected into the grid. However, because of its
low frequency (5060 Hz), the transformer is big, heavy, and
expensive. More to the point, it reduces the overall efficiency of
the conversion stage. Because of the cost and size reduction and
overall efficiency improvement, the interest on transformerless
conversion topologies is growing [1].
In order to keep the systems features in transformerless PV
systems, the inverter must cover the purpose of the transformer.
Safety requirements can be fulfilled by including a ground
fault detector in the inverter. A ground fault detector is a
simple but reliable device that disconnects the inverter upon the
detection of an isolation fault in the installation [2], [3].
Manuscript received November 12, 2007; revised March 21, 2008. This work
was supported in part by the Spanish Ministry of Education and Science under
Grant DPI2006-15627-C03-02.
The authors are with the Department of Electrical and Electronic Engineering, Public University of Navarra, 31006 Pamplona, Spain.
Digital Object Identifier 10.1109/TIE.2008.924015

Fig. 1.

Common-mode currents in a transformerless conversion stage.

The galvanic connection between the grid and the PV array

results in the appearance of a common-mode resonant circuit
consisting, on the stray capacitance, of the PV generator to
ground and the filtering elements (Fig. 1) [4], [5]. If the
common-mode voltage generated by the inverter includes frequencies close to that of the circuits resonance, large commonmode currents will appear. These common-mode currents might
cause severe (conducted and radiated) electromagnetic interferences, grid current distortion, and additional losses in the
system. To avoid the circulation of these leakage currents in
transformerless PV systems, it is necessary to use conversion
topologies, which do not generate variable common-mode voltages [4].
The injection of dc into the grid is a matter of great concern for electric utility companies because it might cause the
saturation of the distribution transformers along the grid [6].
Consequently, limitation standards range from several hundred milliamps in the most lenient countries [7][9] down to
20 mA in England [10]. Usually, the grid current is controlled
by means of a PI regulator. This type of regulator eliminates
the error in the permanent regime, i.e., it guarantees that the
error will not have a direct component. However, the current
measurement elements (current sensor, operational amplifiers
for signal conditioning, and an analog-to-digital converter if the
control is digitally implemented) can offset the measurements,
resulting in the appearance of a direct component in the grid
current. The magnitude of this dc is equal to the sum of
all the measuring element offsets. Complying with the most
lenient regulations is easily accomplished by means of the
control system. However, to attain levels of dc current under
20 mA, measurement devices with very low offsets would be
required (20 mA in a 3.6-kW inverter supposes a total offset
of less than 0.125%), significantly increasing the cost of the
hardware. An alternative to the use of such low-offset elements

0278-0046/$25.00 2008 IEEE

GONZLEZ et al.: TRANSFORMERLESS SINGLE-PHASE MULTILEVEL-BASED PHOTOVOLTAIC INVERTER

is to implement conversion topologies, which ensures no dc

injection into the grid.
Several conversion topologies that do not generate variable
common-mode voltages have been proposed for use in transformerless PV systems. One of these topologies is the full
bridge with bipolar pulsewidth modulation [5], [11], [12]. However, bipolar modulation causes large current ripple and high
switching losses, reducing the overall efficiency of the inverter.
Furthermore, this topology would not prevent the injection of
dc current into the grid. References [5], [13], and [14] are
proposals for two modifications of the full-bridge topology,
which reduce the current ripple and improve the efficiency
of the full-bridge topology. However, these topologies do not
resolve the dc problem.
Another topology proposed for transformerless PV systems
is the half-bridge inverter [1], [6], [15], [16]. This topology,
which besides not generating variable common-mode voltage,
guarantees the noninjection of dc current by connecting one
of the grid terminals to the midpoint of a capacity divider.
However, the half-bridge inverter causes a large current ripple
and high switching losses, thus reducing the efficiency of the
inverter. In order to improve the efficiency and reduce the
current ripple, the use of a single-phase three-level diodeclamped inverter has been proposed [6], [17][19]. In this case,
the connection of the clamping diodes to the capacity midpoint
enables the dc to get to the grid.
This paper proposes a modification of the single-phase threelevel diode-clamped inverter. The resulting conversion topology
adds to the advantages of the traditional single-phase three-level
diode-clamped inverter, the topological guarantee of the noninjection of dc into the grid. The functioning of the inverter
and a proposed control strategy are described later. The results
obtained by simulation have been verified in a 5-kW prototype.

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Fig. 2. PV system model in terms of the converter differential and commonmode voltages.

damp environments or on rainy days, can exceed 200 nF/kWp

[11], [17].
To study the leakage current into the ground, it is useful to
describe the system behavior with the help of the common- and
differential-mode concepts. The common-mode output voltage
of any circuit is the average value of the voltages between the
outputs and a common reference. In our case, it is convenient to
use the negative terminal of the dc input, which is point N , as
the common reference. Therefore, the common-mode voltage
of the converter cm is
cm =

1N + 2N
.
2

(1)

The differential-mode output voltage dm is defined as the

voltage between both converter outputs

II. C OMMON -M ODE S YSTEM D ESCRIPTION

dm = 1N 2N = 12 .

When no transformer is used, a galvanic connection between

the ground of the grid and the PV array exists. Under these
conditions and because of the high stray capacitance between
the PV generator and the ground, large ground leakage currents
can appear. The amplitude of these currents can exceed the
legal norms [9]. In [4], a model is proposed for the analysis
of the common-mode system behavior. This model determines
the effect, on ground currents, of the conversion topology and
the arrangement of its elements.
Fig. 1 shows a detailed scheme of a transformerless PV
system, including the most important stray elements influencing ground current dynamics, which are the stray capacitance
between the PV array and the ground CPVg and the series
impedance between the ground connection points of the inverter and the grid ZGcGg . Fig. 1 also shows the inverter
inductor (split in two parts L1 and L2 , which are between
the line and the neutral), the differential-mode filter capacitor
Cdm , and the common-mode filter elements (Lcm and Ccm ).
The effect of the stray capacitances between the inverter outputs and the ground have been disregarded because of their
low value relative to that of the PV generator, which, in

In real PV systems, there are stray capacitances that provide

electrical paths for the ground current, known as the commonmode current icm . The value of the common-mode current is a
function of the common-mode voltage. However, the value of
icm cannot be directly deduced from the value of cm because
icm is also affected by other voltage sources and by elements
such as the system parasitic elements.
The voltages between the outputs of the converter and point
N , which are 1N and 2N , are determined by the switching
modulation sequence. Therefore, both outputs can be studied as
controlled voltage sources connected to the negative terminal of
the dc input (point N ).
By redrawing Fig. 1 and expressing voltages 1N and 2N
as the functions of cm and dm , the model shown in Fig. 2 is
obtained.
The grid affects the voltage across the stray capacitance
between the PV generator and the ground. Considering that
the grid is a low-frequency voltage source (50 Hz60 Hz), its
influence on the common-mode current will be hereby ignored.
Moreover, the capacitance Cdm does not affect the commonmode current. Fig. 3 results from introducing the equivalent

(2)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 7, JULY 2008

Fig. 3. Model of the common-mode.

Fig. 5. Voltage 12 and inductor current in a half-bridge inverter. VPV =

700 V, Fsw = 5 kHz, and L1 = 3 mH.
Fig. 4. Half-bridge inverter.

circuits between points A and B in the model of Fig. 2. This

model is only applicable to the common-mode analysis.
Besides the voltage source cm , the model includes the additional voltage source s1 due to differential-mode impedance
asymmetries, i.e., in the inverter inductors. Therefore, although
an inverter does not generate any common-mode voltage, it is
possible to have common-mode currents if there are asymmetries in the value of the aforementioned impedances. For this
reason, it is convenient to introduce the concept of the total
common-mode voltage tcm in order to study the development
of ground currents
tcm = cm + dm

L2 L1
.
2(L1 + L2 )

(3)

An immediate conclusion is that if the voltage tcm does

not vary, no common-mode current flows through the circuit.
This is because the capacitance CPVg remains charged at
voltage tcm .
III. H ALF -B RIDGE I NVERTER
One of the conversion topologies proposed for PV applications is the half-bridge inverter [1], [6], [15], [16]. The basic
elements of this topology, shown in Fig. 4, are comprised of
two switches (S1 and S2 ), the inverter inductor L1 , and an
input-side capacity divider with its midpoint (2) connected to
the neutral terminal of the grid. Characteristically, with this
topology, the inverter inductor is connected to a single grid
terminal (L2 = 0), obtaining a constant total common-mode
voltage [4].
Taking into account that the gate signals to turn the switches
S1 and S2 on and off must be complementary in order to
avoid a short-circuit of the input voltage, the working principle
of this topology is straightforward. If S1 is on, the voltage
12 = in /2, whereas if S2 is on, the voltage 12 = in /2.

For the correct functioning of the topology, the input voltage

must be at least twice the maximum grid voltage. Fig. 5 shows
the simulation results of the main electrical variables during a
grid period.
The total common-mode voltage of the half bridge, considering that L2 = 0, is
tcm = cm + dm

L2 L1
in
= 2N =
= const. (4)
2(L1 + L2 )
2

By generating a constant total common-mode voltage, the

half bridge guarantees the absence of ground currents.
For the correct functioning of the half bridge, the voltage 2N
must be kept constant and equal to in /2. This is achieved by
implementing a PI to control 2N , adding a direct component
to the grid current reference. The grid current can be expressed
as a function of the capacitors C1 and C2
ig = iC1 + iC2 .

(5)

If the capacitors are equal, the current through each capacitor

will be the same
ig = iC1 + iC2 = 2 iC2 .

(6)

The dc injected into the grid by the inverter during one grid
cycle ig,dc (T) can be expressed in terms of the grid current
1
ig,dc (T ) =
T

T

1
ig dt =
T

T
2 iC2 dt.

(7)

If the voltage 2N is controlled so that its change over one

grid cycle is negligible, we obtain

T
V2N (T ) = 0

iC2 dt = 0.
0

(8)

GONZLEZ et al.: TRANSFORMERLESS SINGLE-PHASE MULTILEVEL-BASED PHOTOVOLTAIC INVERTER

Fig. 6.

2697

Single-phase three-level diode-clamped inverter.

Therefore
1
ig,dc (T ) =
T

T
0

1
ig dt =
T

T
2 iC2 dt = 0.

(9)

From (9), it can be deduced that if 2N is controlled such

that its change over one grid cycle is negligible, then no dc is
injected into the grid. This noninjection is independent of the
current measurement offsets. More precisely, the offsets of the
elements in the current measurement sequence are compensated
by the integral part of the regulator of voltage 2N .
However, the half-bridge inverter has two relevant disadvantages. First, the output voltage 12 is modulated between in /2
and in /2, generating a considerable current ripple. Second,
the semiconductors switch with the whole input voltage, which
reduces the efficiency of the inverter.
IV. S INGLE -P HASE T HREE -L EVEL
D IODE -C LAMPED I NVERTER
To improve the efficiency of the half bridge and reduce
its current ripple, the use of a single-phase three-level diodeclamped inverter has been proposed [6], [17][19]. This topology consists of four switches (S1 S4 ) and two diodes (D5 and
D6 ) connected to the neutral grid terminal at the midpoint (2)
of the input-side capacitive divider (Fig. 6). The diodes D5 and
D6 , which are also referred to as clamping diodes, limit the
voltage seen by the switches S1 S4 to half the input voltage.
As in the case of the half-bridge inverter, the inverter inductor
L1 is placed in the line terminal, and no inductor is placed
in the neutral terminal (L2 = 0). The working principle of the
topology is described in the following.
During the grid voltage positive half cycle, S2 remains on,
whereas S1 and S3 commutate at the switching frequency in
order to modulate the input voltage. In this case, when S1 is
on and S3 is off, the voltage 12 = in 2N = in /2, and the
inductor current flowing through S1 and S2 increases. When S1
switches off and S3 comes on, the current flows through D5
and S2 . In this case, the voltage 12 is clamped to zero, and the
current decreases.
During the grid voltage negative half cycle, S3 remains on,
whereas S2 and S4 commutate at the switching frequency. In
this case, when S4 is on and S2 is off, the voltage 12 =
2N = in /2, and the current flowing through S3 and S4
decreases. When S4 switches off and S2 comes on, the current

Fig. 7. Voltage 12 and inductor current in a single-phase three-level diodeclamped inverter. Vin = 700 V, Fsw = 5 kHz, and L1 = 3 mH.

flows through S3 and D6 , and the voltage 12 is clamped to

zero; thus, the coil current increases.
Fig. 7 shows the simulation results of the main electrical
variables during a grid period. The input voltage, the switching
frequency, and the inductance are the same as that used for
the half-bridge simulation. Comparing the results shown in
Fig. 5 with that in Fig. 7, it can be observed that the threelevel modulation (in /2, 0, in /2) reduces the current ripple
by half.
Following, and in accordance with, the working principle
described earlier, the mean instantaneous value of the inverter
differential-mode voltage 12  is defined. The term mean
instantaneous value refers to the mean value calculated for the
switching period Tsw . The analysis has been made, supposing
that the voltage 2N equals in /2.
During the grid voltages positive half cycle
12  = (in 2N )

ton,S1
in ton,S1

=
.
Tsw
2
Tsw

(10)

During the grid voltage negative half cycle

12  = 2N

ton,S4
in ton,S4

=
.
Tsw
2
Tsw

(11)

Assuming that the mean instantaneous voltage of L1 is

negligible, it is obtained as
12  = g =

in
m
2

where m is the duty ratio defined as

 ton,S
1
if g 0 (positive half cycle)
Tsw ,
m=
ton,S4
Tsw , if g < 0 (negative half cycle).

(12)

(13)

The total common-mode voltage of the single-phase threelevel diode-clamped inverter, considering that L2 = 0, is
tcm = cm + dm

L2 L1
in
= 2N =
= const.
2(L1 + L2 )
2

(14)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 7, JULY 2008

Considering that the total common-mode voltage generated

is constant, the topology guarantees the absence of ground
currents.
With regard to dc, the connection of the diodes at the
midpoint means that (5) is no longer applicable. The new
relationship between the capacitor and grid currents depends
on the configuration of the PV generator. In [6], the midpoint
of the PV generator is connected to the capacitive midpoint
(dotted line in Fig. 6). In this manner, the PV generator fixes
the voltage 2N , and the grid dc is proportional to the offsets of
the measuring elements. Alternatively, this connection need not
be made. In this case, the voltage 2N must be controlled in a
manner that is similar to that described for the half bridge. The
grid current will then be given by
ig = iC1 + iC2 + id = 2 iC2 + id .

(15)

Fig. 8. Mean instantaneous value of current id ,
id . P = 5 kW, Vg =

230 V, and Vin = 700 V.

Thus, the value of the dc injected into the grid will be

1
ig,dc (T ) =
T

T

1
ig dt =
T

T

1
=
T

(2 iC2 + id ) dt
0

T

1
2 iC2 dt +
T

T
id dt.

(16)

The voltage 2N is kept constant during one grid cycle.

Introducing (8) into (16), we obtain
1
ig,dc (T ) =
T

T
id dt.

(17)

The current flowing through the diodes id equals the grid

current when D5 or D6 are conducting and is negligible if the
diodes are switched off. According to (12) and (13), the diodes
switching periods can be calculated as a function of the input
and grid voltages.
During the grid voltage positive half cycle
ton,S1
2 g
ton,D5
=1
=1
.
Tsw
Tsw
in

(18)

During the grid voltage negative half cycle

ton,D6
ton,S4
2 (g )
=1
=1
.
Tsw
Tsw
in

(19)

The mean instantaneous value of the current circulating

through the diodes id  (Fig. 8) is calculated according to (18)
and (19)
1
id  =
Tsw

Tsw
id (t) dt = ig dr

(20)

Fig. 9. (a) Factor dr over one grid period. Vg = 230 V. Vin = 700 V.
(b) Harmonic analysis of the factor dr .

As seen in Fig. 9(a), dr is a periodic wave with a frequency

that is twice that of the grid. Considering that dr is a periodic
signal, it can be expanded into a Fourier series. The series
includes sine terms of frequencies that are the multiples of the
fundamental repetition frequency (2)

dr = dr,dc +

where dr relates the grid and the input voltages so that

dr = 1

2 |g |
.
in

drn sin(n2t + n ).

(22)

n=1

(21)

Fig. 9(b) shows the harmonic decomposition of dr . These

harmonics are multiples of 2. In addition, this figure indicates

GONZLEZ et al.: TRANSFORMERLESS SINGLE-PHASE MULTILEVEL-BASED PHOTOVOLTAIC INVERTER

2699

that the harmonic with the greatest amplitude is that which

occurs at 2.
The grid current ig is controlled to follow the reference current, i.e., a sine wave of the same frequency as the grid voltage
g . However, in practice, this current will present a series of
harmonics due to, among other reasons, the dead time between
same branch switch commutations and the presence of harmonics in the grid voltage. The grid current might be written as
ig =

ign sin(nt + n ).

(23)

n=1

From ig and dr , it is possible to calculate the dc injected into

the grid during one grid cycle ig,dc (T)
1
ig,dc (T ) =
T

T

1
id dt =
T

1
=
T

ig dr dt

Fig. 10. DC injected into the grid ig,dc (A) as a consequence of a second
harmonic in the grid current.

T 

T


igi sin(it + i )

i=1

dr,dc +

drj sin(2 jt + j ) dt

(24)

j=1

by applying
Fig. 11. Proposed topology.

T
sin(it+ i ) sin(jt + j ) dt = 0

i = j.

(25)

This way, from (24) and (25), it is concluded that the grid
current even harmonics can generate a direct component, which
is even if the voltage 2N remains constant during the cycle.
The amplitude of the dc will depend on the order and amplitude
of the even harmonics and the phase difference with respect
to dr . Considering the harmonic spectrum of dr [Fig. 9(b)],
the most troublesome even harmonic will be the second one.
Fig. 10 shows the dc resulting from the second harmonic
of the grid current. The dc is plotted as a function of the
harmonic amplitude and its phase difference that is relative to
the fundamental (n ). Calculations are based on 5-kW power
and an effective grid voltage of 230 V. The phase difference
between the voltage and the fundamental is assumed to be zero
(1 = 0) because, in general, PV inverters work with unity
power factor. As shown in Fig. 10, the presence of a 2% second
harmonic in the grid current, which is 90 out-of-phase with
the fundamental, results in the injection of 120 mA of the dc to
the grid.
V. P ROPOSED T OPOLOGY
The proposed topology is based on the single-phase threelevel diode-clamped inverter. The new topology adds a second capacitive divider to which the neutral grid terminal is
connected (Fig. 11). This way, the voltage at the midpoint of
the additional capacitive divider (MP2) is controlled and the

noninjection of the dc to the grid is topologically guaranteed. At

the same time, the topology retains the positive characteristics
of the single-phase three-level diode-clamped inverter; namely,
the nongeneration of variable total common-mode voltage, the
reduced current ripple, and the efficiency.
Next, the differences between the single-phase three-level
diode-clamped inverter and the proposed topology working
principle are discussed. During the grid voltage positive half
cycle, which is when S1 and S2 are on, the voltage 1MP2 =
in MP2 . When S2 and D5 conduct, 1MP2 = MP1
MP2 . During the negative half-cycle, while S3 and S4 are on,
1MP2 = MP1 in . While S3 and D6 conduct, 1MP2 =
MP1 MP2 .
The mean instantaneous value of the proposed inverter
differential-mode voltage 1MP2  during the positive half
cycle is
1MP2 
=

(in MP2 ) ton,S1 + (MP1 MP2 ) (Tsw ton,S1 )

.
Tsw
(26)

During the negative half cycle

1MP2 
=

MP2 ton,S4 + (MP1 MP2 ) (Tsw ton,S4 )

.
Tsw
(27)

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Fig. 12. Voltage 12 and inductor current in the proposed topology. Vin =
800 V, VMP1 = 350 V, VMP2 = 400 V, Fsw = 5 kHz, and L1 = 3 mH.

Ideally, if MP2 equals MP1 , the converter output voltage

would be similar to the single-phase three-level diode-clamped
inverter (12) and (13). However, asymmetries caused by partial
shading, dirt, or panel manufacturing imperfections are often
present on the PV generators. These asymmetries cause differences between the midpoint voltages MP1 and MP2 . This
difference generates a perturbation on the output voltage that
is obtained from (12), (13), (26), and (27) as
= (MP1 MP2 ) (1 |m|)



 2 g 
 .

= (MP1 MP2 ) 1 
in 

(28)

The amplitude of the perturbation is proportional to the

voltage difference between its midpoints and its frequency to
the grid (5060 Hz). The current control loop compensates the
perturbation. Fig. 12 shows the simulation results of the main
electrical variables during a grid period when Vin = 800 V,
VMP1 = 350 V, and VMP2 = 400 V.
As demonstrated for the half-bridge topology, which is
shown in (5)(9), the noninjection of a dc into the grid is
guaranteed by connecting the neutral grid terminal to the midpoint of the second capacitive divider (MP2), which controls
the average voltage of MP2.
The efficiency of the proposed topology is similar to the
single-phase three-level diode-clamped inverter, considering
that the same semiconductors and operation are used.
VI. C ONTROL OF THE P ROPOSED T OPOLOGY
The control of the new topology is based on cascading loops,
as shown in Fig. 13.
A maximum power point tracking algorithm determines the
reference input voltage that is necessary to maximize the PV
generator output energy [20][23]. After this, a slow control
loop of the input voltage calculates the effective value of the
grid current fundamental. The fundamental thus obtained is
multiplied by a sine wave in phase with the grid voltage in order
to obtain a unity power factor.

Fig. 13.

Control of the proposed topology.

A second slow control loop is used to maintain MP2 that is

equal to in /2; this control loop calculates the current that is
necessary to assure this equivalence (idc ). The idc component
is added to the reference current ig1,ref obtained by means of
the control loop of the input voltage. Finally, a fast current
control loop is used to make sure that the grid current trails
the reference current ig,ref .
In steady state, the component of the reference current calculated by the MP2 control loop idc corresponds to the offset
introduced by the current measurement elements.
VII. E XPERIMENTAL R ESULTS
To validate the operation and efficiency of the proposed
topology, a prototype was built. The prototype specifications are
an input voltage VPV between 700 and 1100 V, a grid voltage
of 230 V, a rated power of 5 kW, a switching frequency of
16 kHz, and an inductance of 3 mH.
International Rectifiers IRG4PSC71UD 600-V fast
insulated-gate bipolar transistors (IGBTs) were chosen for the
switches, and IR HFA 25TB60 600-V diodes were selected
for D5 and D6 . Optocoupled drivers, which are Concept
2SD106AI-17, were used to drive the IGBTs. The prototype
is controlled by means of a DSP1104 from dSPACE. Fig. 14
shows the prototype.
As mentioned in Section III, the half bridge has similar
characteristics to the proposed topology regarding the total
common-mode voltage and noninjection of the dc to the
grid. To compare the efficiency of the proposed topology and
the half bridge, a second prototype (half bridge) has been
constructed. This second prototype has similar specifications,
namely, VPV = 7001100 V, Vg = 230 V, P = 5 kW, Fsw =
16 kHz, and L = 3 mH. The IGBTs used were IRG4PSH71UD,
which are of the same family as the IRG4PSC71UD, but of
1200 V.

GONZLEZ et al.: TRANSFORMERLESS SINGLE-PHASE MULTILEVEL-BASED PHOTOVOLTAIC INVERTER

2701

Fig. 14. Implemented prototype.

Fig. 16. Measured efficiency of the proposed topology and the half bridge.
Vin = 700 V.

Fig. 16 shows the efficiency of the proposed topology and

that of the half bridge as a function of the output power for an
input voltage of 700 V. The maximum efficiency of the proposed topology is 98.16%, which is in comparison with 97.1%
attained by the half bridge, which is an efficiency improvement
of 1.06%.
VIII. C ONCLUSION
This paper proposes a new conversion topology designed
for use in transformerless PV systems. The topology generates
no varying total common-mode voltage, thus improving the
behavior of the inverter in terms of electromagnetic interference, exhibits high efficiency, and guarantees that no dc is
injected to the grid. The behavior of the proposed topology has
been validated on a 5-kW prototype. The maximum efficiency
achieved by the topology is 98.16%. As a conclusion, the proposed topology represents a valuable power-conversion stage
for transformerless grid-connected PV systems.
R EFERENCES

Fig. 15. (a) Grid voltage (100 V/div) and output current (10 A/div) of the
proposed topology. (b) DC injected into the grid by the proposed topology
(5 mA/div).

Fig. 14 shows the experimental results of the proposed inverter. Fig. 15(a) shows the grid voltage and current. Fig. 15(b)
shows the dc injected into the grid over a 2-min period. As it
is shown in Fig. 15(b), the level of dc does not exceed 7 mA at
any instant.

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Roberto Gonzlez received the M.Sc. degree in

industrial engineering from the Public University of
Navarra (UPNA), Pamplona, Spain, in 2003.
Since 2006, he has been with the Electrical and
Electronic Department, UPNA, where he is an Assistant Professor and where he is currently involved
in research projects with the Electrical Engineering,
Power Electronics, and Renewable Energy research
group (INGEPER). His research interests include
power electronics and renewable energies, such as
wind and photovoltaic plants.

Eugenio Guba (M04) received the M.Sc. and

Ph.D. degrees in industrial engineering from the Public University of Navarra (UPNA), Pamplona, Spain,
in 1995 and 2003, respectively.
Since 1996, he has been with the Electrical and
Electronic Department, UPNA, where he is currently
an Assistant Professor and where, in 2002, he joined
the Electrical Engineering, Power Electronics, and
Renewable Energy research group (INGEPER). He
has been involved in several research projects that are
mainly in cooperation with industries. His research
interests are in the fields of power electronics, renewable energy systems, power
system quality, and electromagnetic compatibility.

Jess Lpez (M05) received the M.Sc. degree in

industrial engineering from the Public University of
Navarra (UPNA), Pamplona, Spain, in 2000.
Since 2001, he has been with the Electrical and
Electronic Department, UPNA, where he is an Assistant Professor and where he is currently involved
in research projects with the Electrical Engineering,
Power Electronics, and Renewable Energy research
group (INGEPER). His research interests include
power electronics, power systems quality, and renewable energies, such as wind and photovoltaic plants.

Luis Marroyo (M04) received the M.Sc. degree

in electrical engineering from the University of
Tolouse, Tolouse, France, in 1993, the Ph.D.
degree in electrical engineering from the Public
University of Navarra (UPNA), Pamplona, Spain,
in 1997, and the Ph.D. degree from the Laboratoire
dElectrotechnique et dElectronique Industrielle
Ecole Nationale Suprieure dElectronique,
dInformatique, dHydraulique et des Tlcommunications Institut National Polytechnique de
Toulouse, Toulouse, France, in 1999.
From 1993 to 1998, he was an Assistant Professor with the Department
of Electrical and Electronic Engineering, UPNA, where, since 1998, he has
been an Associate Professor and where he is currently the Head of the Electrical Engineering, Power Electronics, and Renewable Energy research group
(INGEPER). His research interests are in power electronics, grid quality, and
renewable energy.