Arithmetic Logic Unit

FINAL PROJECT REPORT

FOUR BIT ARITHMETIC LOGIC UNIT

COMPUTER ARCHITECTURE

Instructor:
\
Dr.M.yousuf
.
Supervisor:

Sir Fawad Raza

Department of Computing Science and Technology

Iqra University Islamabad Campus

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DEDICATION:

“We dedicate our project to our beloved parents

and our most respected teachers for the
guidance, kindness and dedication they have
showed towards us without which this project
would not have been possible”

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ACKNOWLEDGEMENT

We all are very thankful to Almighty ALLAH for giving us courage for
making this report.
And we are also very thankful to our teacher Dr. Muhammad Yousaf for
giving us this project from which we explored the corporate sector.

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GROUP MEMBERS

Mehboob Nazim Shehzad (BSTN) 1085

Naheeda Mir (BS.CS) 1266

Faizan Ahmad (BSTN) 1081

Ajmal Khan (BSTN) 1080

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TABLE OF CONTENT

Title: ..................................Error! Bookmark not defined.

Dedication: ....................................................................... 2
Introduction: ....................................................................... 6
Purpose:............................................................................ 6
Arithmetic unit: ................................................................... 6
Circuit diagram ................................................................ 7
Circuit Diagram of Full Adder: ........................................ 8
Multiplexer: - ................................................................... 8
Circuit Diagram of Multiplexer: .................................... 9
Block Diagram of AU: ................................................... 10
Circuit Diagram of AU: - ............................................... 11
Logic unit:......................................................................... 12
Circuit Diagram of LU: - ................................................ 13
Operation Of ALU: -......................................................... 14

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INTRODUCTION:

The ALU is a fundamental building block of the central processing unit of a computer.
The ALU is abbreviation for arithmetic-logic unit. The ALU is a combinational logic
device (which basically means it can be constructed from AND, OR, and NOT gates, and
is the implementation of a Boolean function).

PURPOSE:
PURPOSE

The purpose of the ALU is to perform computation on its data inputs, such as adding the
two sets of inputs, or subtracting, or performing bit wise operations. The control bits tell
the ALU which operation to perform.

Components of ALU:

ALU has three components;

• Arithmetic unit
• Logic unit

ARITHMETIC UNIT:

• The arithmetic unit (AU) is a digital circuit that calculates an arithmetic

operation (like an addition, subtraction, etc.)
• In our project we have made an AU that can perform addition as well as
subtraction.

• For addition we need an adder; there are two kinds of adders, half adder and
the full adder. A full adder is made up of two half adders. Half adder is used
to add two bits. But if we want to add more than two bits then we use full
adder.

• Truth table for a half adder is as follow:

Truth table for half adder

Inputs Outputs
A B C (carry) S (sum)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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Ø Block diagram of half adder is as shown below:

A Half S
Adder
B C

Ø Circuit diagram:

Truth table for Full Adder

Inputs Outputs
S(Switch) A B C S (sum)
(carry)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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Ø Block diagram of Full Adder:

A S
Full
B C
Adder
S

Ø Circuit Diagram of Full Adder:

MULTIPLEXER:
MULTIPLEXER:
A multiplexer or mux (occasionally the term muldex is also found, for a
combination multiplexer-demultiplexer) is a device that selects one of many data-sources
and outputs that source into a single channel.

Truth Table of Multiplexer

Inputs Output
SW (Switch) A B D
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

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Ø BLOCK DIAGRAM OF MULTIPLEXER:

A
M
U
D
X
B

SW

Ø CIRCUIT DIAGRAM OF MULTIPLEXER:

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Ø BLOCK DIAGRAM OF AU:

C(I/P)
A0

B0 F0
M F.A
U
X

A1
F1
F.A
B1
M
U
X

A2
B2 F2
M F.A
U
X

A3
F3
F.A
B3 M
U
X

Carry (o/p)

SW

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Ø CIRCUIT DIAGRAM OF AU:

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Ø LOGIC UNIT:

The logic unit (LU) is a digital circuit that performs logic operations (like an
Exclusive or) between two numbers.

SW

A0
G0
MUX
B0

A1

G1

B1
MUX

A2

G2
B2
MUX

A3
G3
MUX
B3

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CIRCUIT DIAGRAM OF LU:

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COMPLETE ALU:

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NOTE:

We use those gates in ALU circuit.

LOGIC GATES

Digital systems are said to be constructed by using logic gates. These gates are
the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic
operations are described below with the aid of truth tables.

Ø AND GATE

 
 


The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in
mind that this dot is sometimes omitted i.e. AB

Ø OR GATE





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The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.

Ø NOT GATE





The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter.If the input variable is A, the
inverted output is known as NOT .This is also shown as A', or A with a bar
over the top, as shown at the outputs. The diagrams below show two ways that
the NAND logic gate can be configured to produce a NOT gate.

Ø EXOR GATE

 



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The 'Exclusive-OR' gate is a circuit which will give a high output if either, but
not both, of its two inputs are high. An encircled plus sign ( ) is used to show
the EOR operation.

OPERATION OF ALU:

A digital arithmetic unit useful in data processing digital circuits comprises a

plurality of stages each having two half-adders combined into a full adder and
a carry logic element. An objective is to shorten the processing time for the
addition and subtraction of binary numbers. For this purpose, the stages are
divided into at least two groups and two separate carry paths are provided
within each group. One of the carry paths is only switched on by means of
selection logic elements. The activation occurs sequentially in group-wise
fashion after simultaneous carry runs in all carry paths. The advantage
particularly consists of the chronological coincidence of the carry runs in all
groups.

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