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Page 1
CMOS TECHNOLOGY
INTRODUCTION
Classification of Silicon Technology
Silicon IC Technologies
Bipolar
Junction
Isolated
Dielectric
Isolated
Silicon031211-01 Germanium
Bipolar/CMOS
Oxide
isolated
Silicon
MOS
PMOS
(Aluminum
Gate)
CMOS
Aluminum
gate
Silicon
gate
NMOS
Aluminum
gate
Silicon
gate
P.E. Allen - 2003
Page 2
n+
n+
Source/drain
extensions
Deep p-well
STI
p+
p+
Source/drain
STI
extensions
Deep n-well
p-substrate
031211-02
Page 3
70
60
NMOS
Slow, 70C
fT (GHz)
50
Typical, 25C
40
30
Slow, 70C
PMOS
20
10
0
100
200
300
|VGS-VT| (mV)
400
500
030901-07
The upper frequency limit is probably around 40 GHz for NMOS with an fT in the vicinity
of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.
Page 5
yy
;;
Gate Ox
Oxide
Substrate
p+
p-
n-
n+
Salicide Polycide
Poly
Metal
031231-13
Page 6
yy
;;
Gate Ox
Oxide
n-well
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-12
Page 7
Shallow
Trench
Isolation
yy
;;
Gate Ox
Oxide
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-11
Page 8
n threshold implant
n threshold implant
Shallow
Trench
Isolation
yy
;;
Gate Ox
Oxide
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-10
Page 9
; ;
Thin Oxide
Shallow
Trench
Isolation
yy
;;
Gate Ox
Oxide
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Salicide Polycide
Poly
Metal
031231-09
Page 10
; ;
Shallow pImplant
Shallow
Trench
Isolation
yy
;;
Gate Ox
Oxide
Shallow pImplant
Shallow nImplant
Shallow nImplant
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-08
Page 11
; ;
Sidewall
Spacers
Shallow
Trench
Isolation
yy
;;
Gate Ox
Oxide
Sidewall
Spacers
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-07
Page 12
; ;
p+
implant
n+
implant
p+
n+
yy
;;
Oxide
n+
implant
n+
implant
p+
implant
n+
n+
p+
p+
p+
Shallow
Trench
Isolation
Gate Ox
Sidewall
p+ Spacers
p+
implant
implant
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-06
Page 13
Step 9 Siliciding
Siliciding and polyciding is used to reduce interconnect resistivity by placing a lowresistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of the diffusions.
; ;
Sidewall
Spacers
Salicide
Salicide
p+
n+
yy
;;
Gate Ox
Oxide
Salicide
p+
p+
Shallow
Trench
Isolation
Polycide
Salicide
n+
n+
p+
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-05
Page 14
Intermediate
Oxide
Layer
Salicide
Salicide
p+
n+
yy
;;
Oxide
Polycide
Salicide
p+
p+
Shallow
Trench
Isolation
Gate Ox
; ;
Sidewall
Spacers
Salicide
n+
n+
p+
Shallow
Trench
Isolation
n-well
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-04
Page 15
Tungsten
Plugs
Salicide
p+
Salicide
n+
yy
;;
Oxide
Polycide
Salicide
Tungsten
Plug
Salicide
p+
p+
Shallow
Trench
Isolation
Gate Ox
; ;
Sidewall
Spacers
n+
n+
p+
Shallow
Trench
Isolation
n-well
First
Level
Metal
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-03
Page 16
Intermediate
Oxide
Layers
Tungsten
Plugs
Tungsten
Plugs
Salicide
p+
Salicide
n+
yy
;;
Oxide
Salicide
p+
p+
Shallow
Trench
Isolation
Gate Ox
; ;
Tungsten Plugs
Polycide
Sidewall
Spacers
Tungsten
Plug
Salicide
n+
n+
p+
Shallow
Trench
Isolation
n-well
Second
Level
Metal
First
Level
Metal
Shallow
Trench
Isolation
p-well
Substrate
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-02
Page 17
Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker toplevel metal and a protective layer to hermetically seal the circuit from the environment.
Note that metal is used for the upper level metal vias. The chip is electrically connected
by removing the protective layer over large bonding pads.
; ;
Metal Vias
Intermediate
Oxide
Layers
Tungsten
Plugs
Salicide
p+
n+
p+
Tungsten
Plug
Salicide
n+
n+
p+
Shallow
Trench
Isolation
n-well
yy
;;
Second
Level
Metal
First
Level
Metal
Tungsten Plugs
Polycide
Salicide
p+
Shallow
Trench
Isolation
Gate Ox
Metal Via
Sidewall
Spacers
Tungsten
Plugs
Salicide
Top
Metal
Shallow
Trench
Isolation
p-well
Substrate
Oxide
p+
p-
n-
n+
Poly
Salicide Polycide
Metal
031231-01
Page 18
Tungsten Plug
TEOS
SOG
Polycide
Sidewall
Spacer
TEOS/BPSG
Poly
Gate
Fig. 2.8-20
Digital Integrated Circuit Design
Page 19
Metal 3
Aluminim
Vias
Metal 2
Tungsten
Plugs
Metal 1
Transistors
Digital Integrated Circuit Design
ECE 4420 CMOS Technology (12/11/03)
Fig.180-11
P.E. Allen - 2003
Page 20
SUMMARY
Fabrication is the means by which the circuit components, both active and passive, are
built as an integrated circuit.
Basic process steps include:
1.) Oxide growth
2.) Thermal diffusion
3.) Ion implantation
4.) Deposition
5.) Etching
6.) Epitaxy
The complexity of a process can be measured in the terms of the number of masking
steps or masks required to implement the process.
Major Processing Steps for DSM CMOS:
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide