UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING

COMPUTER ENGINEERING DEPARTMENT

Digital Logic Design

Introduction to Gate Level Modeling in Verilog

Dated:
04th April, 2016 to 08th April, 2016

Semester:
Spring 2016

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

Objective:At the end of this part of the lab you should be able to:
Write a Verilog code at gate level.
What is Verilog?
Verilog is a programming language that has been developed for describing digital circuits and
systems.
Verilog is case-sensitive.
Verilog is free format |i.e. statements can be written on one line or on multiple lines.
// is used to create a comment line.
Verilog supports two type of operators: Arithmetic operators.
Bit-wise operators
Different Types of Design Models in Verilog:There are four different types of modeling methods in Verilog.

Switch Level Modeling

Gate Level Modeling
Data Flow Modeling
Behavioral Modeling

In Digital Design we mostly use Gate level modeling, Data Flow Modeling, Behavioral Modeling.
It is very rare that we choose switch level modeling using transistors, but Verilog provides us to
model at switch level. Switch level is not mostly used because with the increasing complexity of
circuits it becomes very difficult to manage switches so we switch to higher level of modeling.
Verilog only has well defined states 0, 1, x, z. There is no analog value in Verilog, so the transistors
act as switches here with sates of on or off.
Gate Level Modeling:Verilog has built in primitives like gates, transmission gates, and switches.

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

The gates have one scalar output and multiple scalar inputs. The 1st terminal in the list of gate
terminals is an output and the other terminals are inputs.

Examples: and U1(out,in);

and U2(out,in1,in2,in3,in4);
xor U3(out,in1,in2,in3);

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

Transmission Gate Primitives:-

Examples: bufif0 U1(data_bus,data_drive, data_enable_low);

buf U2(out,in);
not U3(out,in);
Designing Using Primitives:NOT gate using NAND Gate:-

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

AND gate using NAND Gate:-

Implement OR using NAND:-

Implement NOR using NAND:-

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

Implement XOR using NAND:-

Implement NOT using NOR Gate:-

Implement AND using NOR:-

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

Implement OR Using NOR:-

Implement NAND using NOR:-

Implement XOR using NOR:-

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan

UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

FACULTY OF TELECOMMUNICATION AND INFORMATION ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

Verilog code for implementing NOT gate using NAND Gate:-

module nand_and(out,in1);
input in1;
output out;
nand(out,in1,in1);
endmodule
Lab Tasks:Write the Verilog code for all the above circuits and
verify their operation.

Digital Logic Design

Session:-2K15 Computer

Lab Instructor:-Engr. Aamir Arsalan