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Submitted by:
Aditya Mittal (axm144430)
Varsha Vivek (vmv140130)
OVERVIEW:
The block diagram of the entire application is as shown below:
2. InReady
This is a status flag that is set by the MSDAP to indicate to the controller if it is
ready to receive data from the controller.
If InReady is high, the controller transmits data to the MSDAP.
3. Frame (Input)
This signal acts as a means of communication between the controller and the
MSDAP and signifies the beginning of a sample data both input and ouput.
When the first bit of the input data is sampled, Frame is set high for the first DClk
pulse.
The Frame lasts for 16 DClk cycles or 40 SClk clock cycles .
Output data is sampled at the falling edge of Frame after every 40 SClk cycles.
4. OutReady (Output)
This is a status flag that is set to LOW when the MSDAP is transmitting the
output.
It is set low at the falling edge of Frame for 40 Sclk clock cycle when the MSDAP
is transmitting output data.
5. OutputL/R (Output)
This field carries the output data generated by the MSDAP.
It is synchronized with the falling edge of SClk.
It is 40 bits long so as to maintain accuracy and account for overflow during the
calculations.
The MSB is the sign bit and is transmitted first, followed by the remaining 39 bits.
Thoughts:
Optimal number of signals are being used here that maintain the functionality and
accuracy of the system.
Rj and coefficient values are also transmitted to the MSDAP through the
InputuL/InputR field. This reduces the number of pins on the chip.
Status signals InReady and OutReady are necessary to communicate the status
of the MSDAP to the controller. Removal of the status signals will lead to incorrect
synchronization between the controller and the MSDAP.
The Frame is important is synchronizing Data Clock and the System Clock.
(1.2) THE OPERATION MODES
The figure2 depicts the FSM designed in order to achieve the desired MSDAP
application.
State 5 (Waiting for input x): In this state, InReady is set high. The MSDAP enters
State 6 if Frame is detected to be high, or State 7 if Reset_n is detected to be low.
State 6 (Working): In this state, the chip continually reads input samples, does the
convolution computation, and sends out the computed output data; InReady
remains high. If Reset_n is detected low, the chip enters State 7 or if the chip
detects 800 consecutive inputs samples as zero, it enters State 8.
State 7 (Clearing): In this state, InReady is set low. All input and output samples in
memories or registers except for rj and coefficients are cleared to zero. If Reset_n is
detected to be low again during this process, the chip will come back to the
beginning of this process. The chip will go back to State 5 when completed with the
task of reset.
State 8 (Sleeping): In this State, the chip goes into sleeping mode while setting
lnReady high. If any non-zero input sample on either left or right channel is
detected, the chip enters State 6. If Reset_n is detected low, the chip enters State 7.
Thoughts:
The waiting states seem to be redundant. They can be combined with the states
following them.
For example: State 1: Waiting for Rj can be merged with the next state, State 2:
Reading Rj. This could save some clock cycles eventually.
PIN NAME
PIN FUNCTION
1.
SCLK
System Clock
Frequency of
operation: 26.88MHz
This signal provides
timing for the output
signal to be
communicated
between the MSDAP
and the controller.
2.
DCLK
Data Clock
Frequency of
operation: 768KHz
This signal provides
timing for the input
data transmitted by
the controller to the
MSDAP.
3.
VDD
Also: 7,14,19
4.
Power
+1.8V DC
VSS
Ground
RESET
Input signal
Also: 8, 13, 18
5.
NC
No connection
9.
OUTPUTL