MSMW'13, Kharkov, Ukraine, June 23-28

A LOW PHASE-NOISE GaAs FET/BJT VOLTAGE-CONTROLLED OSCILLATOR

FOR MICROWAVE APPLICATIONS
1

Vladimir Ulansky and 2Sally Faisal Ben Suleiman

Department of Electronics, National Aviation University
Kosmonavta Komarova 1, Kiev, 03058, Ukraine
E-mail: vulanskyi@yahoo.com
2
Department of Electronics, Carleton University
1125 Colonel by Drive, Ottawa, Ontario, K1S5B6, Canada,
E-mail: salibensuleiman@cmail.carleton.ca
1

Abstract - This paper presents a novel negative differential resistance (NDR) voltage-controlled oscillator (VCO)
for microwave applications. The VCO circuit comprises a GaAs field-effect transistor (FET) and a bipolar
junction transistor (BJT) current mirror. The VCO has an N-type I-V characteristic with controllable slope of the
NDR region. The mathematical models of the I-V characteristic are developed using three the most frequently
used models of GaAs FET drain current: Curtice, Statz and TOM. The designed VCO uses an n-channel GaAs
metal semiconductor field effect transistor (MESFET) NE722S01 and four p-n-p bipolar junction transistors
(BJTs) MRFC521. The VCO covers a frequency band between 1.233 GHz and 1.679 GHz with maximum
in-band phase-noise of -146 dBc/Hz at 100-kHz offset over the tuning range. Power consumption of the VCO
core is 53 mW from a 6.5 V supply. The implemented prototype of the proposed oscillator draws 4 mA from a
3.2V power supply and generates low-noise low-distortion signal.
Keywords - metal semiconductor field effect transistor, varactor, current mirror, power consumption
1.

INTRODUCTION

The VCOs are critical building blocks in all modern microwave communications systems and satellite
transceivers. The rapid growth of such systems has created a great demand for low phase-noise low power
consumption VCOs. Modern microwave oscillators use the hetero-junction BJTs or low-noise high-electron
mobility transistors (HEMTs) as active devices for achieving low phase-noise performance [1], [2]. A
considerable amount of publications has been devoted to the MESFET oscillators [3] [5]. All above mentioned
oscillators are related to the class of negative impedance oscillators having negative real part in the input
impedance [6]. Another class of microwave oscillators is based on the Gunn and tunnel diodes [7], [8], which have
an NDR region in the N-type current-voltage (I-V) characteristic. Locating the operating point in the NDR region
results in creating a negative resistance induced into the tank circuit for compensating its losses. The N-type I-V
characteristic can be obtained artificially by using an electronic circuit, which generally consists of a FET with
negative gate-to-source voltage and a current mirror [9].
In this paper a GaAs FET VCO with a BJT improved Wilson current mirror (IWCM) is analysed and
designed. The VCO performance characteristics are investigated by SPICE simulation.
2.

ARCHITECTURE

The VCO circuit is shown in Fig. 1. The resistors R1 and R2, transistor Q1, and improved Wilson current
mirror (IWCM) transistors M1-M4 provide an N-type characteristic of the current It versus voltage VCC.
Transistor Q1 can be a MESFET, HEMT or pseudomorphic HEMT. The VCO tank circuit consists of a radio
frequency coil L and two contrary connected varactor diodes VD1 and VD2. Resistor Rctrl isolates the dc control
voltage line, Vctrl, from the VCO tank. Capacitors C1 and C2 are used for reducing the phase-noise and harmonic
distortions. The current mirror supplies almost equal currents IIN and IOUT to the drain of FET Q1 and to ground.
In the circuit of Fig. 1, the current mirror input voltage VIN=2VEB, where VEB is the emitter-base junction voltage
of transistors M1 M4. For the IWCM the input (IIN) and output (IOUT) currents are almost the same.

978-1-4799-1068-7/13/$31.00 2013 IEEE

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Figure 1. The VCO circuit with IWCM

3.

DC ANALYSIS

3.1. Analysis of I-V Characteristic

The negative differential resistance is obtained between points a and b in the circuit of Fig. 1. As
voltage VCC increases from zero, the current mirror and transistor Q1 are cut off. And the terminal current It is
determined by the Ohms law
I t I 2 VCC

R1 R2

(1)

Until VCC equals

VCC1 VIN R1 R2 R2 (2)
transistor Q1 is cut off. This region is indicated by the curve 0A in Fig. 2. At VCC1, transistor Q1 turns ON and
enters ohmic region because the voltage between drain and source of Q1 (VDS) is very small.

Figure 2. Typical I-V characteristic of the VCO circuit

Since Q1 operates in the ohmic region then
V DS VGS V P

(3)

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where VGS is the gate-to-source voltage of Q1 and VP is thepinch-off voltage of Q1.

The drain-to-source and gate-to-source voltages are found by applying the KVL to the circuit of Fig. 1
VDS VCC

VGS

R2
R1 R2
VCC R1
R1 R2

I IN R1 R2 VIN

I IN R1 R2

(4)

(5)

Applying the KCL to the node a in the circuit of Fig. 1, the terminal current It can be found as

It

I IN R2
R1 R2

I OUT

VCC
R1 R2

(6)

It should be noted that in general the current IOUT is a function of the input current IIN.
As VCC is increased further, transistor Q1 enters the saturation region where
V DS VGS V P

(7)

The threshold voltage VCC2 is in the vicinity of the boundary between the ohmic and saturation regions of
Q1, and can be represented as
VCC 2 VIN VP

(8)

Thus, the I-V characteristic has a positive slope between voltages VCC1 and VCC2. From equations (2) and (8)
follows that for reducing the interval of the supply voltages, where the I-V characteristic has a positive slope,
the current mirror input voltage, VIN, must be as small as possible.
As VCC is increased further, the current IIN, which is the drain current of Q1, decreases due to the increasing
negative voltage VGS. And this drop in current IIN exceeds the rise in current I2. Hence, the terminal current It
begins to decrease as the voltage VCC is raised. This is the NDR region shown in Fig. 2 as line BC.
As VCC is increased further, eventually the decrease in currents IIN and IOUT becomes equal to the increase of
current I2, that is
dI t dVCC 0

(9)

The voltage VCC3 is shown as the valley point C in Fig. 2.

Any further increase of VCC results in increasing the terminal current It. For VCC>VCC3, the current It is due
to the current I2 and the decreasing currents IIN and IOUT. The currents IIN and IOUT become zero when the
gate-source voltage of transistor Q1 exceeds its pinch-off voltage, that is
VGS VCC R1

R1 R2 VP

(10)

From (10) finally follows that

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VCC 3 VP R1 R2 R1

(11)

3.2. Analytical Modeling the Drain Current of Q1

Neglecting the difference between currents IIN and IOUT in the first approximation we can assume that
I OUT I IN

(12)

In this case equation (6) is simplified to

I t I IN 1

R2
R1

R2

VCC
R1 R2

(13)

However, the current IIN is the drain current of transistor Q1, IIN=ID. Therefore (13) can be represented as

It

I D 1

R2
R1

R2

VCC
R1 R2

(14)

From (14) follows that the terminal current It depends only on the resistor values, power supply voltage and
drain current of transistor Q1.
For the purpose of nonlinear modeling the microwave FETs, many models are available [10]. The following
three models are the most popular: the Curtice model, the Statz model, and the TOM (TriQuints Own Model).
The Curtice model defines the drain current in the saturation region with respect to the drain-source and
gate-source voltages as follows [10]:
I D VGS VP 1 VDS tanh VDS
2

(15)

where , , and are the model parameters; is the transconductance, is the tanh constant, and is the
channel length modulation coefficient.
Substituting VDS and VGS from (4) and (5) into (15) gives
2

V R
V R
V R

I D CC 1 I D R1 R2 VP 1 CC 2 VIN I D R1 R2 tanh CC 2 VIN I D R1 R2 (16)

R1 R2
R1 R2
R1 R2
As seen from (16), the drain current of Q1 is a nonlinear function of the Curtice model and VCO circuit
parameters.
The Statz static model is a modification of the Curtice model by means of replacing the hyperbolic tangent
function with a polynomial approximation. In the saturation region the Statz drain current equation is given by
[10]

I D VGS VP 1 VDS 1 B VGS VP (17)

2

where B is the doping profile parameter.

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Substituting VDS and VGS from (4) and (5) into (17) finally results in the following equation:
2

V R

CC 1 I D R1 R2 VP
R1 R2
1 VCC R2 I R R V
ID

D
1
2
IN
R R
VCC R1

1
2
1 B
I D R1 R2 VP
R1 R2

(18)

The TOM
is popular because it fits the dc behavior of a FET accurately. The exponent in the
expression (VGS VP)2 is changed from a constant 2 to the variable Q, so that the drain current is represented as
[10]
I D VGS VP

1 V

GS

VP VDS
Q

(19)

The parameter in (19) is used for modeling the decreased drain conductance at low gate-source biases.
Substituting VDS and VGS from (4) and (5) into (19) results in the following equation:

V R
I D CC 1 I D R1 R2 VP

R1 R2

VCC R2
VCC R1
1 R R I D R1 R2 VP R R I D R1 R2 VIN (20)
2
2

1
1

The current ID as a function of VDD can be found numerically by solving the nonlinear equations (16), (18)
and (20). Then, by substituting ID into (14), the terminal current It can be calculated.
4.

SIMULATION RESULTS

The simulation results were obtained using SPICE models of real components. A MESFET NE722S01 was
selected as transistor Q1. Four p-n-p BJTs of MRFC521 type were used for designing the IWCM. The values of
resistors R1 and R2 were chosen to be 0.47k and 3.9k, respectively. Panasonic resistors ERJ1GEJ471 and
ERJ2GEJ392 were selected. The simulated I-V characteristic of the VCO is shown in Fig. 3 by a solid line. As
seen, the NDR region is located between VCC2=4V and VCC3=31.2V. The dc operating point was selected at
VCCQ=6.5V and ItQ=8.2mA. The dot line in the NDR region corresponds to the theoretical approximations made
by using equations (16), (18) and (20). As seen from Fig. 3, a very good agreement exists between the simulated
and the theoretical results in the NDR region of the VCO I-V characteristic. Thus, any of the three obtained
equations (16), (18) and (20) can be used for modeling the drain current of transistor Q1 in the NDR region.
The surface mount varactor diodes SMV1104-34 were selected to change the VCO frequency from 1.233 to
1.679 GHz when a variable dc voltage Vctrl, applied to the diode cathodes, was changed from 2V to 12V. A
3.3-nH chip inductor ELJQF3N3 (Panasonic Semiconductors) was used in the VCO tank circuit. The values of
capacitors C1 and C2 were adjusted providing the following condition:

min LN dB

C1 , C 2

(21)

where LN is the VCO phase noise. The optimized values of C1 and C2 are equal to 1nF and 100nF, respectively.

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Figure 3. The VCO I-V characteristics: solid line corresponds to the simulated characteristic; dot line
corresponds to the theoretical characteristics using the Curtice and Statz models, and the TOM
TDK and Panasonic multilayer chip capacitors C1005X5R1H102K (1nF) and ECJ1VB1C104K (100nF)
were selected as C1 and C2. The plots of simulated phase-noise versus offset frequency at Vctr=6V are shown in
Fig. 4. As seen, the phase-noise is very much dependent on the value of capacitors C1 and C2. The phase-noise
decreases until C1 and C2 reach 1nF and 100nF, respectively. A further increase in capacitance C1 almost does
not reduce the phase-noise. While a further increase in capacitance C2 even increases the phase-noise. The
phase-noise reaches a noise floor near -170dBc/Hz at offset frequency f 600 kHz . It should be noted that the
maximum in-band phase-noise of -146 dBc/Hz at 100-kHz offset is reached at Vctrl=2V. The amplitude of the
output voltage is varied from 2.7V to 3.7V when voltage Vctrl is changed from 2V to 12V.

(a)

(b)

Figure 4. Simulated phase-noise of the proposed VCO at Vctrl=6V: (a) curve 1 C1=1pF, curve 2 - C1=1nF;
(b) curve 1 C2=100pF, curve 2 C2=100nF
For evaluating the overall performance of the proposed VCO, a common FOM is used
FOM LN f 20 log f 0 f 10 logPdiss 1mW

where LN(f) is the phase-noise at a frequency offset f , f0 is the oscillation frequency, and Pdiss is the power
dissipation. In Table 1, the phase-noise and FOM of the proposed VCO and earlier published VCOs are
compared. As can be seen from Table 1, the proposed VCO has very good performance.

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Table 1. Performance comparison of different VCOs

Reference
[11]
[12]
[13]
[14]
This work
5.

Central
frequency
(GHz)
1.95
1.57
2.0
2.44
1.456

Phase-noise
(dBc/Hz)

FOM
(dBc/Hz)

-126@100kHz
-120@1MHz
-103@100kHz
-134.3@1MHz
-146@100kHz

-188.8
-179.1
-182.2
-194.1
-212

EXPERIMENTAL RESULTS

A prototype of the proposed oscillator was designed and implemented as shown in the photograph of Fig. 5
(a). The values of R1 and R2 were selected to be 270 and 2k respectively. Agilents ATF-33143 low noise
PHEMT was used as transistor Q1. The IWCM was constructed using four BFT92 p-n-p BJTs. A 47nH chip
inductor of ELJRF47NJF2 type was selected. Radial silveredmica capacitors of 2.2pF were used instead of
varactors and capacitor C1. The capacitor C2 was set to 0. The oscillator output waveform is illustrated in Fig.
5(b). The measured I-V characteristic is shown in Fig. 5 (c). The operating point was selected in the NDR region
at VCCQ=3.2V with ItQ=4mA. The oscillator was connected to the oscilloscope through the unity gain buffer.

(a)

(b)

(c)
Figure 5. Practical implementation of the NDR oscillator circuit with IWCM: (a) the oscillator printed-circuit
board; (b) the oscillogram of the output voltage ; (c) the oscillator I-V characteristic.
True output voltage amplitude is around 1.2V with 20dB probe attenuation and approximately 18dB connecting
cable loss. The measured oscillation frequency is 230MHz. The measured frequency is less than its theoretical
value because of the parasitic capacitance of the printed circuit board and buffer input capacitance.

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CONCLUSION

A novel NDR VCO has been presented. It consists of a GaAs FET and a p-n-p BJT improved Wilson
current mirror. The mathematical modeling of the N-type I-V characteristic has been conducted using the TOM,
Curtice and Statz models. The designed VCO was simulated with Spice files of real components and showed
maximum in-band phase-noise of -146 dBc/Hz at 100-kHz offset frequency over the tuning range. With power
consumption of 53 mW, the VCO achieves a worst-case FOM of -212dBc/Hz, which is the best FOM at (1 2) GHz band. The operation principle of the proposed oscillator has been verified by implementing a 230 MHz
oscillator.
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