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CPU REGISTERS

CPU R EGISTERS

Registers are faster than other type of memories

• Shorter instructions:

– The number of registers is smaller (e.g. 32 bit registers need 5 bits)

• Minimize the frequency with which data is moved back and forth between the memory and processor registers

INSTRUCTION EXECUTION

I NSTRUCTION E XECUTION

Address

i

i+ 4 i + 8

Contents

Move A,R0

Add

B,R0

Move R0,C

Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C
Contents Move A,R0 Add B,R0 Move R0,C

Begin execution here

A

B

C

3-instruction

program segment

Assumptions:

- One memory operand per instruction

- 32-bit word length

- Memory is byte addressable

- Full memory address can be directly specified in a single-word instruction

can be directly specified in a single-word instruction Data for the program A program for C
can be directly specified in a single-word instruction Data for the program A program for C

Data for the program

A program for C = [A] + [B].

Two-phase procedure -Instruction fetch -Instruction execute

B RANCHING       i Move NUM1,R0   i + 4 Add NUM2,R0  

BRANCHING

     

i

Move

NUM1,R0

 

i + 4

Add

NUM2,R0

 

i + 8

Add

NUM3,R0

   

 

i + 4n- 4

Add

NUMn,R0

i

+ 4n

Move

R0,SUM

A straight-line

   

program for adding n numbers.

 

 

 

SUM

 

NUM1

 

NUM2

 
   

 

NUMn

 

BRANCHING

B RANCHING Move N,R1 Clear R0 LOOP Program Determine address of "Next" number and add "Next"
Move N,R1 Clear R0 LOOP Program Determine address of "Next" number and add "Next" number
Move
N,R1
Clear
R0
LOOP
Program
Determine address of
"Next" number and add
"Next" number to R0
loop
Decrement R1
Branch target
Conditional branch
Branch>0
LOOP
Move
R0,SUM
SUM
N
n
NUM1
Using a loop to add n numbers.
NUM2
NUMn

CONDITION CODES

C ONDITION C ODES

• To describe processor status

• Also called status flags

• Condition codes refer to the information about most recently executed instruction

• Different instructions affect different flags

• Example of flags:

– N (negative)

– Z (zero)

– V (overflow)

– C (carry)

CONDITIONAL BRANCH INSTRUCTION

C ONDITIONAL B RANCH I NSTRUCTION

• Example of condition code flags:

– A: 11110000

– B: 00010100

A:

1 1 1 1 0 0 0 0

+(−B):

1 1

1

0 1 1 0 0

1 1 0

1 1 1 0 0

   

Z = 0

C = 1 N = 1 V = 0

STATUS BITS: BLOCK DIAGRAM

S TATUS B ITS : B LOCK D IAGRAM

Interconnection of an ALU to the status bits

register C n-1 A B ALU C n F V Z S C F n-1
register
C n-1
A
B
ALU
C n
F
V
Z
S
C
F n-1
Zero Check

ADDRESSING MODES

ADDRESSING MODES

A DDRESSING M ODES

A method to specify the location of an operand

• Various addressing modes provided for different purposes and different trade-offs – in terms of instructions length, etc. Effective address – the actual address of the

operand after all address computations of the addressing mode have been performed

computations of the addressing mode have been performed Computer Architecture and Organization (BEC30303) | Chapter

ADDRESSING MODES

A DDRESSING M ODES

Implied:

– AC (accumulator) is implied in “ADD M[AR]” in “One-Address” instruction

– TOS (stack) is implied in “ADD” in “Zero- Address” instruction

Immediate:

– The use of a constant in “MOV R1, 5”

– i.e. R1 5

Direct Address (absolute):

– Use the given address to access a memory location, “MOV R1, 110”

ADDRESSING MODES

A DDRESSING M ODES

Register (or register direct):

Indicate which register holds the operand

Register indirect:

Indicate the register that holds the number of the register that holds the operand

Displacement addressing:

– Relative, indexing, base

Autoincrement/autodecrement:

– Access and update in 1 instruction

REGISTER INDIRECT

R EGISTER I NDIRECT

• Indicate the memory location that holds the address of the memory location that holds the data

AR – address register

AR = 101 100 101 0 1 0 4 102 103 104 1 1 0
AR = 101
100
101
0
1
0
4
102
103
104
1
1
0
A

RELATIVE ADDRESSING

R ELATIVE A DDRESSING

• Relative mode – the effective address is determined by the index mode using the program counter in place of the general- purpose register.

• X(PC) – note that X is a signed number

• This location is computed by specifying it as an offset from the current value of PC.

RELATIVE ADDRESS

R ELATIVE A DDRESS

• Example:

– EA = PC + relative address

PC = 2 + AR = 100 Could be Positive or Negative (2’s Complement)
PC = 2
+
AR = 100
Could be Positive or
Negative
(2’s Complement)

PC – program counter

0 1 2 100 101 102 1 1 0 A 103 104
0
1
2
100
101
102
1
1
0
A
103
104

Computer Architecture and Organization (BEC30303) | Chapter 2: ISA

79

counter 0 1 2 100 101 102 1 1 0 A 103 104 Computer Architecture and

INDEXING (1/2)

I NDEXING (1/2)

• Index mode – the effective address of the operand is generated by adding a constant value to the contents of a register

• Using index register

• X(R i ): EA = X + [R i ]

• The constant X may be given either as an explicit number or as a symbolic name representing a numerical value.

• If X is shorter than a word, sign-extension is needed.

INDEXING (2/2)

I NDEXING (2/2)

• In general, the index mode facilitates access to an operand whose location is defined relative to a reference point within the data structure in which the operand appears.

• Several variations:

– (R i , R j ): EA = [R i ] + [R j ] – X(R i , R j ): EA = X + [R i ] + [R j ]

INDEXED ADDRESS

I NDEXED A DDRESS
• EA = index register + relative address Useful with “Autoincrement” or “Autodecrement” XR =
EA = index register + relative address
Useful with
“Autoincrement” or
“Autodecrement”
XR = 2
+
100
AR = 100
101
Could be Positive or
Negative
(2’s Complement)
102
1
1
0
A
103
104
XR – index register
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
82

BASE ADDRESS

B ASE A DDRESS

• EA = base register + relative address

Could be Positive or Negative (2’s Complement) AR = 2 + BR = 100 Usually
Could be Positive or
Negative
(2’s Complement)
AR = 2
+
BR = 100
Usually points to
the beginning of
an array

BR – base register

 

Memory

  Memory

0

0

5

0

1

2

0

0

A

 

1

0

7

0

0

9

 
0 A   1 0 7 0 0 9   100 0 101 0 102 0

100 0

101 0

102 0

103 0

104 5

AUTOINCREMENT/AUTODECREMENT

A UTOINCREMENT /A UTODECREMENT

• Autoincrement mode – the effective address of the operand is the contents of a register specified in the instruction.

• After accessing the operand, the contents of this register are automatically incremented to point to the next item in a list.

• (R i )+ = the increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit operands.

• Autodecrement mode: -(R i ) – decrement first

AUTOINCREMENT ADDRESS EXAMPLE

A UTOINCREMENT A DDRESS E XAMPLE

LOOP

A UTOINCREMENT A DDRESS E XAMPLE LOOP Move N,R1 Move #NUM1,R2 Clear R0 Add (R2)+,R0

Move

N,R1

Move

#NUM1,R2

Clear

R0

Add

(R2)+,R0

Decrement

R1

Branch>0

LOOP

Move

R0,SUM

Initialization Decrement R1 Branch>0 LOOP Move R0,SUM The Autoincrement addressing mode example Computer
Initialization

The Autoincrement addressing mode example

ADDRESSING MODES SUMMARY

A DDRESSING M ODES S UMMARY
 

Assembly

Addressing

Example in

 

Addressing Mode

Syntax

Function

Assembly

Example in RTN

Immediate

#value

Operand = value

Add R4, #3

R4 <- R4 + 3

Register

Ri

EA = Ri

Add R4, R3

R4 <- R4 + R3

Absolute (direct)

LOC

EA = LOC

Add R4, 1001

R4 <- R4 + M[1001]

Indirect

(Ri), (LOC)

EA = [Ri], EA = [LOC]

Add R4, (R1)

R4 <- R4 + M[R1]

Index

X(Ri)

EA = [Ri] + X

Add R4, 2(R1)

R4 <- R4 + M[R1 + 2]

Based with index

(Ri, Ri)

EA = [Ri] + [Rj]

Add R4, (R1, R2)

R4 <- R4 + M[R1 + R2]

Based with index and offset

X(Ri, Rj)

EA = [Ri] + [Rj] + X

Add R4, 2(R1, R2)

R4 <- R4 + M[R1 + R2 + 2]

Relative

X(PC)

EA = [PC] + X

Add R4, 2(PC)

R4 <- R4 + M[PC + 2]

Autoincrement

(Ri)+

EA = [Ri], Ri + 1

Add R4, (R2)+

R4 <- R4 + M[R2], R2 <- R2 + 1

Autodecrement

-(Ri)

Ri - 1, EA = [Ri]

Add R4, -(R2)

R2 <- R2 - 1, R4 <- R4 + M[R2]

ASSEMBLY LANGUAGE

TYPES OF INSTRUCTION

T YPES OF I NSTRUCTION

Name

Mnemonic

Load

LD

Store

ST

Move

MOV

Exchange

XCH

Input

IN

Output

OUT

Push

PUSH

Pop

POP

Data value is not modified
Data value is
not modified

DATA TRANSFER INSTRUCTIONS

D ATA T RANSFER I NSTRUCTIONS

Mode

Assembly

Register Transfer

Direct address

LD

ADR

AC M[ADR]

Indirect address

LD

@ADR

AC M[M[ADR]]

Relative address

LD

$ADR

AC M[PC+ADR]

Immediate operand

LD

#NBR

AC NBR

Index addressing

LD

ADR(X)

AC M[ADR+XR]

Register

LD

R1

AC R1

Register indirect

LD

(R1)

AC M[R1]

Autoincrement

LD

(R1)+

AC M[R1], R1 R1+1

ARITHMETIC INSTRUCTIONS

A RITHMETIC I NSTRUCTIONS

Name

Mnemonic

Increment

INC

Decrement

DEC

Add

ADD

Subtract

SUB

Multiply

MUL

Divide

DIV

Add with carry

ADDC

Subtract with borrow

SUBB

Negate

NEG

LOGICAL/BIT MANIPULATION

L OGICAL /B IT M ANIPULATION

Name

Mnemonic

Clear

CLR

Complement

COM

AND

AND

OR

OR

Exclusive-OR

XOR

Clear carry

CLRC

Set carry

SETC

Complement carry

COMC

Enable interrupt

EI

Disable interrupt

DI

SHIFT INSTRUCTIONS

S HIFT I NSTRUCTIONS

Name

Mnemonic

Logical shift right

SHR

Logical shift left

SHL

Arithmetic shift right

SHRA

Arithmetic shift left

SHLA

Rotate right

ROR

Rotate left

ROL

Rotate right through carry

RORC

Rotate left through carry

ROLC

PROGRAM CONTROL INSTRUCTIONS

P ROGRAM C ONTROL I NSTRUCTIONS

Name

Branch

Jump

Skip

Call

Return

Compare

(Subtract)

Test (AND)

Mnemonic

BR

JMP

SKP

CALL

RET

CMP

CMP

TST

Subtract A – B but don’t store the result
Subtract A – B but
don’t store the result
1 0 1 1 0 0 0 1 0 0 0 0 1 0 0
1
0 1 1 0 0 0 1
0
0 0 0 1 0 0 0
0
0 0 0 0 0 0 0

Mask

CONDITIONAL BRANCH INSTRUCTIONS

C ONDITIONAL B RANCH I NSTRUCTIONS

Mnemonic

Branch Condition

Tested Condition

BZ

Branch if zero

Z

= 1

BNZ

Branch if not zero

Z

= 0

BC

Branch if carry

C

= 1

BNC

Branch if no carry

C

= 0

BP

Branch if plus

S

= 0

BM

Branch if minus

S

= 1

BV

Branch if overflow

V

= 1

BNV

Branch if no overflow

V

= 0

ADDITIONAL INSTRUCTIONS

LOGICAL SHIFTS

L OGICAL S HIFTS

• Logical shift – shifting left (LSHIFTL) and shifting right (LSHIFTR)

C R0 . . . before: 0 0 1 1 1 0 0 1 1
C
R0
.
.
.
before:
0
0
1
1
1
0
0
1
1
.
.
.
after:
1
1
1 0
0
1
1
0
0
(a) Logical shift left
LShiftL
#2,R0

0

0

before:

after:

R0 C . . . 0 1 1 1 0 0 1 1 0 .
R0
C
.
.
.
0
1
1
1
0
0
1
1
0
.
.
.
0
0
0
1
1
1
0
0
1
(b) Logical shift ightr
LShiftR
#2,R0

ARITHMETIC SHIFT

A RITHMETIC S HIFT
R0 C
R0
C

before:

after:

. . . 1 0 0 1 1 0 1 0 0 . . .
.
.
.
1
0
0
1
1
0
1
0
0
.
.
.
1
1
1
0
0
1
1
0
1
(c) Arithmetic shift right
AShiftR
#2,R0

ROTATE

R OTATE
R OTATE Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 98

MULTIPLICATION/DIVISION

M ULTIPLICATION /D IVISION

• Not very popular (especially division)

• Multiply R i , R j :

– R j [R i ] х [R j ]

• 2n-bit product case: high-order half in R(j+1)

• Divide R i , R j :

– R j [R i ] / [R j ], Quotient is in Rj, remainder may be placed in R(j+1)

ENCODING OF MACHINE

INSTRUCTIONS

MACHINE INSTR. ENCODING (1/5)

M ACHINE I NSTR . E NCODING (1/5)

• Assembly language program needs to be converted into machine instructions (binary format):

– ADD (assembly) = 0100 (in binary) in ARM instruction set

• In the previous section, an assumption was made that all instructions are one word in length.

MACHINE INSTR. ENCODING (2/5)

M ACHINE I NSTR . E NCODING (2/5)

• Suppose 32-bit word length, 8-bit opcode (how many instructions can we have?), 16 registers in total (how many bits?), 3-bit addressing mode indicator.

– Add R1, R2

– Move 24(R0), R5

– LshiftR #2, R0

– Move #$3A, R1

– Branch>0 LOOP

8 7 7 10 OP code Source Dest Other info
8
7
7
10
OP code
Source
Dest
Other info

(a) One-word instruction format

MACHINE INSTR. ENCODING (3/5)

M ACHINE I NSTR . E NCODING (3/5)

• What happens if we want to specify a memory operand using the absolute addressing mode?

• Move R2, LOC

• 14-bit for LOC memory address – insufficient bit to include in the instruction

• Solution – use two words

OP code Source Dest Other info Memory address/Immediate operand (b) Two-word instruction format
OP code
Source
Dest
Other info
Memory address/Immediate operand
(b) Two-word instruction format

MACHINE INSTR. ENCODING (4/5)

M ACHINE I NSTR . E NCODING (4/5)

• Then what if an instruction in which two operands can be specified using the absolute addressing mode?

• Move LOC1, LOC2

• Solution – use two additional words

• This approach results in instructions of variable instruction length. Complex instructions can be implemented, closely resembling operations in high-level programming languages – CISC

MACHINE INSTR. ENCODING (5/5)

M ACHINE I NSTR . E NCODING (5/5)

• If we insist that all instructions must fit into a single 32-bit word, it is not possible to provide a 32-bit address or a 32-bit immediate operand within the instruction.

• It is still possible to define a highly functional instruction set, which makes extensive use of the processor registers.

• Add R1, R2 ----- yes

• Add LOC, R2 ----- no

• Add (R3), R2 ----- yes

EXERCISES

EXERCISE 1

E XERCISE 1

• Produce the following arithmetic expressions into Reverse Polish Notation (RPN):

– A*B+C*D

– (A-B+C)/(G+H)

– A+B+C

EXERCISE 1 – SOLUTION

E XERCISE 1 – S OLUTION

• Solution:

– AB*CD*+

– AB-C+GH+/

– AB+C+

EXERCISE 2

E XERCISE 2

• Write the instructions to compute X=(B+A)*[D*(E-C)+G] using microprocessors that use the following instruction formats. If necessary, use temporary location T to store intermediate results. • Instruction formats:

– Three-address

– Two-address

– Zero-address

– RISC format

EXERCISE 2 – SOLUTION (1/3)

E XERCISE 2 – S OLUTION (1/3)

Three-address instruction:

– SUB R1, E, C

– MUL R1, R1, D

– ADD R1, R1, G

– ADD R2, B, A

– MUL X, R2, R1

EXERCISE 2 – SOLUTION (2/3)

E XERCISE 2 – S OLUTION (2/3)

Two-address instruction:

– MOV R1, E

– SUB R1, C

– MUL R1, D

– ADD R1, G

– MOV R2, B

– ADD R2, A

– MUL R1, R2

– MOV X, R1

EXERCISE 2 – SOLUTION (3/3)

E XERCISE 2 – S OLUTION (3/3)

Zero-address instruction:

– PUSH E

– PUSH C

– SUB

– PUSH D

– MUL

– PUSH G

– ADD

– PUSH B

– PUSH A

– ADD

– MUL

– POP X