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Tishreen University Journal for Research and Scientific Studies - Engineering Sciences Series Vol. (30) No. (2) 2008
VHDL-AMS
2008
Multimedia Systems
CAD
CAD
VHDL-AMS
VHDL-AMS
VHDL-AMS
Tishreen University Journal for Research and Scientific Studies - Engineering Sciences Series Vol. (30) No. (2) 2008
ABSTRACT
Multimedia applications require high-speed networks which enable transferring a
large amount of information in a very short time. Optical communications provide an
important contribution to this field. A large amount of information can be transferred in a
very short time, ensuring a large bandwidth Electronic devices used in transmitting and
receiving circuits of optical communication play great roles in
ensuring speed
responsiveness, low noise, and low cost. A computer-aided design of optoelectronics is not
yet mature as digital and analog CAD. In this research, we present a contribution to
modeling an optical receiver which can be used in CAD tools in order to design and
analyze optoelectronic applications. As is the case in our study, we use VHDL-AMS for
modeling multidiscipline systems for optical and electrical signals.
Keywords: Optoelectronic, modeling, simulation, CAD of optoelectronic, operational
amplifier modeling, optical receivers, and VHDL-AMS
Physical
systems
Modeling
Abstract
form
Model
Simulation
Characteristics
System
VHDL-AMS
CAD
VHDL-AMS
Process Engineering
VHDL-AMS
VHDL-AMS
SystemVision
www.mentor.com/systemvision Mentor Graphics
VHDL-AMS
VHDL-AMS
VHDL-AMS
[2, 3] VHD-AMS
(Very High Speed Integrated Circuit /VHSIC/ Hardware Description Language for
Analog and Mixed-Signal Systems)
VHDL
VHDL-
Mixed-Signal Systems
Analog Systems
AMS
VHDL-AMS
VHDLMulti-
AMS
technology Modeling
VHDL-AMS
thermal
mechanical
Quantity
across
through
Free Quantities
through
Domain
Electrical
Thermal
Mechanical (linear)
Mechanical
(rotational)
Magnetical
Hydraulical
across
ACROSS
Voltage (V)
Temperature (C )
Position (m)
Angle velocity (rad/s)
THROUGH
Current (A)
Power (W)
Force (N)
Torque (N*m)
Flux (Wb)
Fluidic flow (1/s)
VHDL-AMS
Multi-Domain Modeling
Mixed-Signal Modeling
[4, 5] Mechatronics Systems
P-N
[6]
Depletion Region
b
P
valance band
P
conductance band
. (c)
electron hole pair
P-N
h hv Eg
v
drift current
d
e
VHDL-AMS
[6] P-N
R
[7]
Ip = RPin
Responsivity
Quantum efficiency
R
photon incident rate
Pin / h
q
q
h
1 . 24
where
[13]
c
v
CinA
Cdiode
Cnext
CoutA
Diode Detector
Vo
light
Iph
Optical Fiber
Transimedance
Amplifier (TIA)
Vbias
Rf
Vout
CinA
Cdiode
CoutA
Cnext
[9]
v
Z cl out
idiode
1 s(
R
A
R f outA
A1
A1
R f .C inT . RoutA .C outT
RoutA .C outT
) s2
A1
A1
VHDL-AMS
Z cl
vout
idiode
Rf
1 s(
( R f .C inT
A
v out
idiode
Rf
1 s(
( R f .C inT
A
BW transAmp
) (1 s . RoutA .C outT )
1 A
Rf .(C diode C inA )
Vk = Vj
il
+
ikj
ikj = 0
A
ikj
il = arbitrary
Voffset = 0
1
H ( s)
A
(1 s 1 )(1 s 2 )
1
2f g1
1
2f g 2
[11]
.
A v in v outp
dv out
d 2 v out
( 1 2 )
1 2
dt
dt 2
0 v out
dv out
d 2 v out
( 1 2 )
1 2
k (v in v off ) rout ioutp
dt
dt 2
VHDL-AMS
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use ieee.math_real.all;
entity opamp is
generic (f1 : real := 1.0;-- First pole
f2 : real := 2.0e6;-- Second pole
A : real := 1.8e6);-- Open loop gain
port (terminal inp : electrical;
terminal inm : electrical;
terminal output : electrical;
terminal Vss, Vdd : electrical);
end entity opamp;
architecture simple1 of opamp is
constant t1 : real := 1.0 / (f1*math_2_pi);
constant t2 : real := 1.0 / (f2*math_2_pi);
quantity vin across inp to inm;
quantity vout across iout through output to ref;
begin
vin == (t1*t2)*vout'dot'dot/A + (t1+t2)*vout'dot/A + vout/A;
end architecture simple1;
Testbench and simulation results
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use ieee.math_real.all;
entity filter is
end entity filter;
architecture bhv of filter is
quantity VD across ID through vout;
begin
source: Vsource (simple)
generic map (dc_value := 1);
port map (node1, electrical_ref);
resisitor1: resistor (ideal)
generic map (res:= 10000);
VHDL-AMS
Iph
Structural Model
[12]
Idark
CD
reverse-biased capacitance
zero-bias
Cjo
CD
C jo
1
built-in voltage
Leakage
[11] SPICE
vR
vR junction capacitance
RD
RS
Resistance
library ieee;
use ieee.math_real.all;
library ieee_proposed;
use ieee_proposed.energy_systems.all;
use ieee_proposed.electrical_systems.all;
entity photo_diode is
generic (CD : real := 1.0*PICO; -- diffusion capacitance
RLEAK : real := 1.0*MEGA; -- leakage resistance
RESPONSIVITY: real := 0.13; -- diode responsivity
IDARK0 : real := 1.0*NANO; -- dark current at nominal temp);
port (quantity ilight : in real;
terminal tan, tca: electrical);
end entity photo_diode;
architecture bhv of photo_diode is
quantity vd across id through tan to tca;
quantity idark, ip, ic, ir: real;
begin
ir == vd/RLEAK;
idark == IDARK0;
ic == CD*vd'dot;
ip == - RESPONSIVITY *ilight;
id == idark + ip + ic + ir;
end architecture bhv;
Idark
RS Itotal
Iph
CD
RD
Vo
VHDL-AMS
testbench
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use ieee.math_real.all;
entity optical_Receiver is
Vb
RL
end entity optical_Receiver;
architecture optical_network of optical_receiver is
quantity VD acroos ID through node1 to node2;
signal ilight : real:=0.001;
begin
source: Vsource (simple) generic map (dc_value := -20);
port map (node1, electrical_ref);
photpdiode: photo_diode (bhv)
generic map (CD := 1.0*PICO, RLEAK := 1.0*MEGA, RESPONSIVITY:= 0.13;
IDARK0 := 1.0*NANO); port map (ilight, node2, node1);
resisitorRL: resistor (ideal)
generic map (res:= 1000); port map
(node2, electrical_ref);
ID == RESPONSIVITY * ilight;
end architecture optical_network;
Itotal-Vo
V-I
SystemVision
Electronic Workbench MuliSim
VD (V)
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
0.0
Pin = 0 w
-5.0
-10.0
Pin = 30w
-15.0
-20.0
Pin = 50w
ID (A)
P-N
V-Itotal
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
Rf
Diode Detector
use ieee.math_real.all;
Vo
light
entity optical_Receiver2 is
I
end entity optical_Receiver2;
architecture optical_network2 of optical_receiver2 is
quantity VD acroos ID through vout;
Vbias
signal ilight : real:=0.001;
begin
source: Vsource (simple)
generic map (dc_value := -20);
port map (inP, electrical_ref);
photpdiode: photo_diode (bhv)
generic map (CD := 1.0*PICO, RLEAK := 1.0*MEGA, RESPONSIVITY:= 0.13;
IDARK0 := 1.0*NANO);
port map (ilight, inN, electrical_ref);
resisitorRL: resistor (ideal)
generic map (res:= 1000); port map (inN, out);
OpAmp: opamo (simple1)
generic map (f1 := 1.0, f2 := 2.0e6, A := 1.8e6);
port map (inP, inN, out, vss, vdd);
ID == RESPONSIVITY * ilight;
end architecture optical_network2;
ph
VHDL-AMS
SystemVision
1500
30 quantities
quantities
LED
MOSFET
LAW, A. M.; KELTON, W.D., "Simulation Modeling Analysis," 3rd Ed. McGrawHill, 2000, 1-8.
2ASHENDEN, P. J.; PETERSON G.; TEEGARDEN, D. "The System Design's
Guide to VHDL-AMS," Morgen Kaufman Publishers, 2004.
3HERV, H., "VHDL-AMS: Anwendungen und industrieller Einsatz," Oldenbourg
Verlag, 2006.
4MENOR GRAPHICS, "Fundamentals of VHDL-AMS for Automotive Electrical
Systems," www.mentor.com, 11-16.
5COOPER, S., "How to Model Mechatronic Systems Using VHDL-AMS,"
SystemVision Technology Series. www.mentor.com.
6ROGERS, A., "Understanding Optical Fiber Communication," Artech House,
2001,109-125.
7KASAP, S.O., " Optoelectronics and Photonics: Principles and Practices,"
Prentice-Hall, 2001, 217-254.
8MORIKUNI, J.; KANG,S.M., "Computer-Aided Design of Optoelectronic
Integrated Circuits and Systems," Prentice-Hall, 1994, 95-103.
9INGLES, M.; STEYAET, M., "Integrated CMOS Circuit for Optical
Communication." Springer Verlage, 2004, 13-40.
10R. JAEGER and T. BLALOCK, "Microelectronic Circuit Design," McGraw-Hill,
2008, 1068-1100.
11COOPER, R. S., "The Designers Guide to Analog & Mixed-Signal Modeling
Illustrated with VHDL-AMS and MAST," 2004 Synopsys,
12PCHEUX, F.; LALLEMENT, C. "VHDL-AMS and Verilog-AMS as Alternative
Hardware Description Languages for Efficient Modeling of Multi-Discipline Systems,"
IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems,
Vol. 24, No. 2, February 2005.
1-
VHDL-AMS