Documente Academic
Documente Profesional
Documente Cultură
AMF-IND-T1119
Introductory Class on EMC/EFT with a
Focus on Susceptibility
Michael Steffen
Senior Field Applications Engineer EMC Expert
TM
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Who am I?
Freescale Field Apps Engineer 8-bit / Sensor Specialist
EMC/EFT Specialist
Appliance EMC Expert 12+ years
Design Engineer 10+ Years in Applicance and Customer
MCU applications
EMC Global Swat Team Member
Published
Authored Several Application Notes
Consulted / Troubleshoot EMC designs for many MAJOR
appliance companies
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Agenda
EMC
Overview
Standards and Test Methods
System Design Best Practices
Review theory
Guidelines
Hardware design methodology
Customer examples
Software best practices
References
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EMC/EFT Overview
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What is EMC?
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Source (a perpetrator)
Medium
Receiver (a victim)
Noisy
component
Noisy
component
Conducted Emissions
Radiated Emissions
Potentially
susceptible
component
Potentially
susceptible
component
Conducted Susceptibility
Radiated Susceptibility
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the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks
of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2007.
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the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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|
B
-
B=
o |
4R2
wL
- ++++++++ - -
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14
Induced Voltage
50
10% Output
30% Output
40
40% Output
30
50% Output
90% Output
20
10
6.
86
70
4.
16
31
1.
06
.0
3
20
95
.5
4
78
.6
2
63
.2
7
50
.2
7
.6
3
.4
8
38
28
19
.5
7
12
7.
07
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Creative
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GOFSL
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Theory
Electromagnetic theory is well understood
The problem is that not everyone understands it
So, a quick review of Maxwells equations
wikipedia.org
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Guidelines
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MCU Oscillator
Input Filtering & Protection
Iteration Start
Iteration Complete
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Resistors
Inductors
Ferrites
CM chokes
Capacitors
Varistors
Zener Diodes
TVS Devices
The goal is to minimize voltage differences between any pins of the IC and
the reference (typically VSS) during and shortly after a transient event.
Ideally, keep (VDD-VSS) and (VI/O-VSS) less than 8V. Using external
Zener or TVS clamp might help. Keep |VSS-VSSA| less than 0.3V
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Radiated
Conducted
PCB1
PCB2
PCB2
Conducted
Filter
PCB1
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Ground (reference)
Power
Data
Decouple regulated and filtered power routed off the PCB (to sensors,
displays, etc).
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Purpose
Bypassing prevents unwanted communications
between different components (or different power
domains) that share the same power rail. This
effect is called common-impedance coupling.
Bypassing provides a local source of charge to limit
voltage variations on the power and ground rails.
Bypassing improves noise margins and stability.
VDD
0.1uF
Minimal
Loop
MCU
VSS
Criteria
The capacitance must be sufficient to provide the
needed
transient current to the load.
The impedance between the bypass and the load
must be very low.
The loop area of the layout must be as small as
possible.
Caps need to be located close to micro to be
effective
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Bypass capacitor is
between supply and load
effective HF shunt
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Definition
Purpose
Decoupling prevents unwanted communications between different
components (or different power domains) that share the same power rail.
This effect is called common-impedance coupling.
Decoupling provides increased isolation over bypassing.
Decoupling improves noise margins and stability.
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27
Implementation
Place the decoupling circuit at the entry point of the power domain to be
filtered.
Decoupling is not always used.
Examples:
VDD
VDD_ISO
Unfiltered
DC Input
VDD
7805
VDD_ISO
Filtered
DC Output
VSS
VSS_ISO
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VSS
VSS
Voltage regulator
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10k
VDD
VDD
1k
Input
RESET/IRQ
100nF
100nF
VSS
MCU
VSS
MCU
High
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Relay
MCU
Relay
Power
Supply
Outputs
Inputs
Outputs
EMI
Filter
Relay
Floorplan example
Inputs
Analog
Sensors
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Power connections
EMI
Filter
Power
Supply
Domain
Digital DC Power
Domain
DF
Outputs
BP
Analog
BP
Relay
Relay
Relay
AC Power Domain
DF Analog DC Power
BP
MCU
Sensors
LPF
LPF
Outputs
Inputs
Inputs Inputs
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I/O connections
EMI
Filter
Power
Supply
Domain
Digital DC Power
Domain
DF
Outputs
BP
Analog
BP
Relay
Relay
Relay
AC Power Domain
DF Analog DC Power
BP
MCU
Sensors
LPF
LPF
Outputs
Inputs
Inputs Inputs
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Floorplan example
Analog
inputs
Isolation series
impedance
Power supply
& EMI filter
Filter
components
close to MCU
MCU &
Digital I/O
Relays
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Advantages
Disadvantages
Ceramic Resonator
Lower cost
Crystal
Low cost
RC Oscillator
Lowest cost.
Silicon Oscillator
(INTERNAL OSCILLATOR)
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Configuration
Use higher frequency signal source (4MHz vs. 32kHz crystal) for immunity
Use high-gain oscillator option for immunity
Use low power oscillator option for emissions
Use internal oscillator, if possible.
Layout
Highest layout priority after power distribution system and MCU decoupling.
Implementation must be controlled to prevent susceptibility.
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35
VDD is on bottom
layer to show
multiple via layer
transition.
Parallel
VDD and
GND Traces
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VDD is on bottom
layer to show
multiple via layer
transition.
LAYERS:
Red Top
Green Bottom
Orange TOP/Bottom
GND
(PLANE)
VCC
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Ground Planes
Find the ground plane
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Software Techniques
Overview
False Signal Detection The MCU detects a change in an input signal that
was induced by a transient or other noise. The MCU then operates on or
responds to the signal as if it were real.
Code Runaway The MCU software execution flow is disrupted. The MCU
begins to execute code out of sequence or from incorrect areas of memory.
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many)
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Port x1
System clock
CPU Read
1!
1!
CPU Read
1!
Result (polling)
Read_portA_bit0 ()
{
Char True_read =0;
for (char count = 6; count!=0 ; count--)
{ unfiltered_read = porta
If (unfiltered_read&&0x01) true_read++; /* mask off all bits except bit 0
};
If (true_read > 2) return (1) ;
Else return(0);
}
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1"
0!
1!
Polling
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41
Interrupt Pins
In many MCUs external pins have interrupt capability
and in most cases will interrupt the CPU on a specific
rising or falling edge. To avoid a spurious noise glitch
being seen as a rogue interrupt, users should always
read the input signal pin to confirm that the input signal
has maintained its assertive state (eg if the PA0 pin
interrupts the CPU on a negative edge the ISR first
instruction should read the PA0 pin and if clear then
execute the interrupts subroutine, if set then take this as
a rogue interrupt.) Note: in most cases the ISR will take
several CPU clocks cycles after the input event has
occurred providing a delay. Depending on the
environment and the system design software delays can
also be implemented to act a sort of de-bounce circuit.
For pins that have no read access deploying a
redundant digital input pin can provide this read after
event mechanism.
In some cases the interrupt function may provide the
option of edge & level sensitive. In most cases the
hardware will still react to a rogue edge, as the edge&
level sensitive feature really provides an additional
interrupt if the input pin is held asserted after the ISR has
completed.
Port x1
System clock
CPU access
ISR
lpc
lpc
Interrupt latency
Verify read
Identifies bogus interrupt
Back to main program
Verify pin state using BIL BIH for IRQ, READ GPIO for KBI, ETC
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42
Unused pins
In some cases not all the input or I/O pins will be used
the MCU in the end application. Unused Input Only pins
need to be tied to either VDD or VSS. A floating high
impedance input pin will oscillate and provide an easier
coupling path into the MCU circuits for noise, and
additionally will consumer more current. ( If MCU in
STOP mode is consuming more current than expected
max. this indicates a floating input pin or pins)
Unused I/O pins should be made outputs and drive a
logic state out. Software can regularly update the Data
and DDR to ensure the pin remains an output.
Users of MCUs should also consider the package they
are using of the particular MCU as the multiple packages
are often served with the same silicon die, and on
smaller pinout versions some input/output pins are not
bonded out. Thus, the user must force these unused
input/output pads to output a static level.
For non-bonded input pins, the MCU manufacturer
should have deployed a pull-up or pull-down device to
ensure these are not left floating. This might be
programmable via a special control register.
NC
PA6
PA7
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All
Refresh - safely
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Program Flow
Program flow check.
CPU Access
Appl code
Appl code
Appl code
Appl code
Appl code
Periodic interrupt
key measure to ensure correct Program flow is known as time-slot monitoring. Time-slot
monitoring describes the method of periodically checking the current status of where the program
counter is and is it performing as expected.
For
example: Using a simple timer overflow interrupt set at ~100mS will interrupt the CPU and the
TOF ISR will be executed. Within this ISR the user can use a form of Token passing to 1) check
program flow and 2) check other interrupt usage.
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Token Passing
A
F{11}
F{12}
F{13}
Check
flow
COUNTBYTE=0x13;
COUNTBYTE=0x12;
COUNTBYTE=0x11;
.
If (COUNTBYTE < (previousCOUNTBYTE+2)) Error;
If (COUNTBYTE > (previousCOUNTBYTE+6)) Error;
/* prrogram flow OK */
previousCOUNTBYTE = COUNTBYTE;
..
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CPU access
Refresh
mechanism
clock
Counter
Reset on
overflow
basic watchdog
If CPU does not execute the
unique refresh mechanism before
counter times out then a reset to
the CPU and all peripherals occurs.
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At
TM
47
reset
Application code
CPU access
Before
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Store in RAM
TM
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CPU Clock
If
Clock Monitor
LOL, LOC
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Start_addr
If Start_addr
< End_addr
Y
Main
Flash
Array
Start_addr ++
End_addr
System_error()
CRC_HI
CRC_LO
Compare
CRC_16==CRC_HI/LO
golden_signature
Flash OK
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Addr
$E000
$E001
$E002
$E003
$E004
$E005
.
Code
0x9D
0x9D
0xCC
0x9D
0x9D
0xCC
Instruction
NOP
NOP
JMP
Jump to Safe_start
Block fill w/ illegal opcode
forces reset
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51
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Software Techniques
Digital
or Analog Inputs
Boundary checking
Using the input capture function of a Timer module to measure the time
duration of the signal.
The captured value can be compared to the expected value.
The software can then react appropriately.
Example:
Analog
Inputs
For
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Software Techniques
Integrated Protection
Features
Be sure to write these bits even if the default states are not changed. This
prevents accidentally disabling protection due to code runaway.
Disable hardware functions that are not used.
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54
Conclusions
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References
Ronald
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GOFSL
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Software
Set
up I/O
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