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CHAPTER 1
Limited fossil fuel reserves and ever increasing population are posing a challenging
issue of catering the increasing demand of electrical energy. At the same time, environmental
issues such as global warming are also a cause of serious concern to humanity. In response to
these problems, most countries have adopted policies which broadly cover two directives:
process. Hence, an efficient and effective conversion process is needed to reduce the waste of
energy and improve the power quality.
1.1 INTRODUCTION
Power electronics has emerged as a key technology in achieving the aforesaid. It
involves application of solid state electronics for the conversion and control of electric power
in a wide range (mill watts to hundreds of megawatts). Power electronic converters can be
found anywhere wherever there is need to modify a form of electrical energy (i.e. change its
current, voltage or frequency). These can be classified according to the type of input and
output power.
AC to DC (rectifier)
DC to AC (inverters)
DC to DC (DC-to-DC converter)
AC to AC (AC-to-AC converter)
Among the various power electronic converter system listed above, inverters play a
crucial role in utilization of renewable energy resources. Renewable energy systems like
Photovoltaic (PV) or Fuel Cell (FC) and Wind Turbine (WT) systems employ power inverters
to generate AC voltage of desired magnitude and frequency for grid connection. Going by the
need of high efficiency and power quality in these systems, the development of high
performance inverters is the major focus of todays power electronic industry [1].
1.1.1 TWO-LEVEL VOLTAGE SOURCE INVERTER
Switch-mode dc-to-ac inverters used in ac power supplies and ac motor drives where
the objective is to produce a sinusoidal ac output whose magnitude and frequency can both be
controlled. Practically, we use an inverter in both single-phase and three phase ac systems. A
2
half-bridge is the simplest topology, which is used to produce a two level square-wave output
waveform. A center-tapped voltage source supply is needed in such a topology. It may be
possible to use a simple supply with two well-matched capacitors in series to provide the
center tap. The full-bridge topology is used to synthesize a three-level square-wave output
waveform. The half-bridge and full-bridge configurations of the single-phase voltage source
inverter are shown in Fig. 1.1 and 1.2 respectively.
In a single-phase half-bridge inverter, only two switches are needed. To avoid shootthrough fault, both switches are never turned on at the same time. S1 is turned on and S2 is
turned off to give a load voltage, VAO in Fig. 1.1, of +V S/2. To complete one cycle, S1 is
turned off and S2 is turned on to give a load voltage, VAO, of -VS/2. In full bridge
configuration, turning on S1 and S4 and turning off S2 and S3 give a voltage of VS between
point A and B (VAB) in Fig. 1.2, while turning off S1 and S4 and turning on S2 and S3 give a
voltage of VS.
Conducting Switches
S1 , S 4
+VS
S2 , S 3
-VS
S1,S2 or S3, S4
arbitrary internal reference node within the converter. Typically, it is a dc-link node, and it is
usually denoted by N and called neutral. To be called a multilevel converter, each phase of
the converter has to generate at least three different voltage levels. This differentiates the
classic two-level voltage source converter (2L-VSC) from the multilevel family. Some singlephase examples of this concept and their respective waveforms are given Fig.1.5 for different
number of levels. It is worth mention that, generally different voltage levels are equidistant
from each other in multiples of Vdc.
Two-level converters can generate a variable frequency and amplitude voltage
waveform by adjusting a time average of their two voltage levels. This is usually performed
with pulse-width modulation (PWM) techniques [35]. On the other side, multilevel converters
add a new degree of freedom, allowing the use of voltage levels as an additional control
element and giving more alternatives to generate the output waveform. For this reason,
multilevel inverters have intrinsically improved power quality, characterized by: lower
voltage distortion (more sinusoidal waveforms), reduce dv/dt, and lower common-mode
voltages, which reduce or even eliminate the need of output filters.
Fig. 1.5 2-level and 3 level Inverters & output wave forms
Disadvantages of 2- level Inverters
Therefore, the reasons for moving towards multilevel from 2-level concept are listed
below:
Large dv/dt and di/dt ratings of switches.
Static and dynamic voltage sharing problem among devices when connected in
series/parallel, to achieve high voltage and high power capabilities from the same
ratings of available devices.
Switching frequency is very high resulting more switching losses and reduced overall
efficiency.
5
Switches must have very low turn-on and turn-off times for high power applications
due to very high switching frequencies.
Higher order harmonics have been introduced, and
Large common mode voltages have been generated across industrial motor phases,
which results in premature motor bearing failures and shaft leakage currents.
Because of these shortcomings of conventional two-level inverters, recent trend is
now switching towards more number of voltage levels at inverter terminals.
Multilevel inverters are mainly used to achieve high voltage and high power
capabilities with reduced harmonic contents. Power quality is also one issue considered by
researchers working in the field. Main source of power quality problem, i.e. harmonic
distortion, can be reduced by using filter circuits or by employing appropriate pulse width
modulation (PWM) technique within inverter/converter. Filters have to carry large current
from inverter, increasing its cost and size. Therefore, PWM techniques are used in such a
manner so that dominant low order harmonics get suppressed resulting in minimal
requirement of filtering (to eliminate only some of the higher order harmonics). It reduces
cost and rating of the filters. Increased switching frequency can be used to reduce harmonic
contents. But it is limited by switching loss constraint. Therefore, switching frequency cannot
be increased beyond certain limit.
To achieve high voltage, high power output from conventional two-level inverter,
series/parallel connections of switching devices are required. Due to series connection,
voltage levels across each device may differ and during switching intervals the rate of change
of voltages and voltage sharing among devices will be difficult. In parallel connection of
switching devices, current sharing during switching intervals may create unbalancing problem
across load and through devices. Thus dynamic voltage and current sharing is difficult in
series/parallel connections of switching devices in two-level inverters.
Because of above limitations and shortcomings of conventional 2-level inverters, need
arose to develop an alternative which can produce high voltage, high power output efficiently
with improved power quality. After significant research around the world, now a days
multilevel inverters have been found better counterpart to the conventional two-level inverters
in medium and high voltage applications.
1.1.3 MULTILEVEL INVERTERS FEATURES, ADVANTAGES & APPLICATIONS
The elementary concept of multilevel inverter involves the use of a number of power
semiconductor switches with several lower voltage DC source to synthesize a stepped AC
waveform at the output which is closer to a sinusoid. Using this concept, Nabae et al in 1981
proposed a new three-level inverter topology which was called neutral-point-clamped PWM
inverter (NPC-PWM) [10]. This topology had the potential to be extended to N-levels.
Features of Multi-Level Inverters
Multilevel inverters have a number of advantages over the conventional two-level high
switching frequency PWM inverter [2-7]. Some of these are listed below.
1. less switching stress on devices
2. high voltage & high power capability
3. reduced harmonic contents without increasing switching frequency or decreasing the
inverter power output
4. no need of extending the device rating
5. reduced switching losses
6. reduced dv/dt
7. reduced (or even eliminated) common mode voltages
8. good electromagnetic compatibility (EMC)
9. elimination of the problem of unequal device ratings
10. Capacitor voltage balancing along with significant reduction in Device Count.
Limitations of Multi-Level Inverters
Multilevel inverters do have some disadvantages also [57]. Some of them in particular
are listed below:
Related gate drive circuit for each switch causing the overall system to be expensive
and complicated.
Carrier-based PWM
Space-vector PWM
A Texas Instruments TMS320F28335 device with a Digital Signal Controller and can
be operated up to 150 MHz frequency
8K x 16 Boot ROM
16 Channel ADC
A CPU for generating data- and program-memory addresses; decoding and executing
instructions; performing arithmetic, logical, and shift operations; and controlling data
transfers among CPU registers, data memory, and program memory
Emulation logic for monitoring and controlling various parts and functionalities of the
DSP and for testing device operation
Signals for interfacing with memory and peripherals, clocking and controlling the
CPU and the emulation logic, showing the status of the CPU and the emulation logic,
and using interrupts
Data Writes (Simultaneous data and program writes cannot occur on the memory bus)
Program Writes (Simultaneous data and program writes cannot occur on the memory
bus)
Data Reads Program (Simultaneous program reads and fetches cannot occur on the
Reads memory bus)
Fetches (Simultaneous program reads and fetches cannot occur on the memory bus)
11
Data-read address bus (DRAB): The 32-bit DRAB carries addresses for reads from
data space.
Data-write address bus (DWAB): The 32-bit DWAB carries addresses for writes to
data space. The memory interface also has three data buses:
Program-read data bus (PRDB): The PRDB carries instructions or data during reads
from program space. PRDB is a 32-bit bus.
Data-read data bus (DRDB): The DRDB carries data during reads from data space.
PRDB is a 32-bit bus.
Data-/Program-write data bus (DWDB): The 32-bit DWDB carries data during writes
to data space or program space.
TABLE 1.2 BUS USE DURING DATA-SPACE AND PROGRAM-SPACE ACCESSES
Address type
Read for program space
Read for data space
Write to program space
Write to data space
Address Bus
Data Bus
PAB
PRDB
DRAB
DRDB
PAB
DWDB
DWAB
DWDB
1.2.6 PERIPHERALS
The F28335 device supports the following peripherals which are used for embedded
control and communication:
ePWM:The PWM peripheral supports independent/complementary PWM generation,
adjustable
12
eQEP: The QEP peripheral uses a 32-bit position counter, supports low-speed measurement
using capture unit and high-speed measurement using a 32-bit unit timer. This
peripheral has a watchdog timer to detect motor booth and input error detection logic
to identify simultaneous edge transition in QEP signals.
ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and hold units for simultaneous sampling.
A complete survey and comparison of different PWM techniques for 2-level voltage
source inverter is presented by Holtz J. [14]. These PWM techniques includes feed-forward
schemes (i.e. SPWM, SVPWM, optimized PWM, optical sub-cycle PWM etc.) and feedback
schemes (i.e. hysteresis current control, sub-oscillation current control, predictive current
control, trajectory tracking control etc.). Several performance criteria are used to find suitable
PWM technique for particular applications. Different multilevel inverter control techniques
have been compared in [15, 13, 16] on the basis of THD, distortion factor, fundamental and
rms line voltages.
To achieve accurate controller output performance, the dynamic model of the system
is necessary. Steinke Jurgen k.,[17] described the basic principle of generating the control
signals for three-level diode clamped inverter using SPWM technique. It explains switching
frequency optimal PWM with NPP control to obtain balanced output voltage across inverter.
Analysis of SPWM control technique for induction motor drives to compare voltage
harmonics, stator harmonic losses, rotor harmonic losses, loss factor has been presented.
13
Sinusoidal PWM, Space Vector PWM and SHEPWM techniques are commonly used
for multilevel inverter control. A very useful PWM technique to eliminate specific lower
order harmonics was proposed first time by Bhagwat in 1983. Sirisukprasert Siriroj [19]
presented the optimized PWM technique that switches the main power devices only once per
cycle with wide range of modulation indexes. The basic concept is to swap the polarity of
some levels to achieve low modulation index. For 7-level cascaded inverter, the lowest
modulation index achievable is 0.1 against 0.5 in traditional techniques.
The very basic operating principle of SVPWM for two level inverters was presented
by Holtz J [14] for induction motor control. The main drawback of SVPWM technique is its
14
complex implementation. Wang Fei and McGrath Brendan Peter [21, 22] presented a
simple SVPWM technique for three-level inverter which is based on two-level SVPWM
technique. The problems of determining sector location and calculating the dwelling times
have been much simplified by using co-ordinate transformations. However the redundancy
control and complexity in implementation still remains. The co-relation between SPWM and
SVWM techniques is required to appropriate design the offset signal to be added to match the
performance of SPWM with SVPWM technique.
In MLI the redundant vectors are more than that in 2-level inverter, so the inverter
performance can be much improved. The inherent relations between two technique is given
in[21] which uses common mode injections in SPWM technique and dwell time calculations
in SVPWM for equivalence. But this work employed constant time ratio of Active
redundancies.
A review and comparison has been made for DCMI, FCMI and Cascaded MLI by
Newton C. and Summer M. [29, 30]. It is also described the basic operation of these three
topologies in a very nice manner. Use of multi-pulse rectifiers at input side of the inverter can
improve the supply as well as load side performance. A very good tour on multilevel inverters
can be seen in [31, 32]. These papers give different topologies, control techniques and
applications of multilevel inverters. Topologies without and with regenerative front end
converters and back-to-back connection of multilevel converters are also presented. At high
power levels, the common mode voltage level and distance between controller and power
module is large which can produce additional noise and upset the system. So, a future trend is
to use fiber optic technologies for sensors, gate drive controllers and communications.
Due to availability of advanced optimization tools such as genetic algorithm (GA) and
particle swarm optimization (PSO) etc, the problem of solving the non-linear transcendental
equations have been rectified up to some extent. Genetic algorithm does not need extensive
derivations and analytical expressions. GA is a search method to find the maximum of
15
2)
Simullink implementation of NPC-MLI inverter for 3 level & 5 levels using SPWM.
3)
compare the results of the multilevel inverter for single pulse width modulation and
SPWM various levels.
4) Hardware implementation of single pulse width modulated NPC-MLI for a 3 level using
DSPf28335
1.5 METHODOLOGY
The Methodology for implementation of the Neutral point Multi Level Inverter can be
achieved by the following steps.
1. Simulink Implementation:
Implement the Proposed model of NPC in MATLAB/SIMULINK environment. The
implementation consists of the following steps
a. Connect the MOSFET switches in the proposed model.
b. Generate the Gate control signals by any of the control strategies suitable for the NPC
inverter.
c. Design the parameters of protection circuits for the switches.
d. To connect a DC supply for the NPC
e. Check results for the 3-Level and 5-Level
16
17
CHAPTER 2
MULTILEVEL INVERTER TOPOLOGIES
&
MODULATION TECHNIQUES
18
CHAPTER 2
1 2
-Vdc
-2Vdc
-(N-1)/2
phase to neutral voltage levels, NL = 2N-1 levels can be found in the line-to-line voltage (a
zero-level is redundant). Something similar happens in the three-phase load voltage, where
combinations of the line voltages are produced, obtaining NLoad = 2NL-1 voltage levels.
However, only NP is used to refer to the number of levels of the converter, since these are the
levels generated by the converter independently of the number of phases or the load
connection type [4].
20
2.3 shows the power circuit of a 5-level diode-clamped inverter. For clarity of the figure, only
one phase is shown. It requires four complementary pairs of switch (S1, S1), (S2, S2), (S3, S3)
and (S4, S4) which are defined such that turning ON one pair of switch prohibits other switch
pairs to get activated. For a 5-level inverter, a set of four switches are ON at any given time.
C1, C2, C3 and C4 are DC-link capacitors which sustain equal voltage. If they are being fed by
a DC link voltage of Vdc, the capacitors voltages will be Vdc/4. Clamping diodes are used to
limit the voltage stress across the power switch to one capacitor voltage level. For increasing
number of levels in the output, the number of clamping diodes increases quadratically with
number of output levels although this quadratic increase in number of clamping diodes is
justified so that each diode has the same rating as the active switches.
S1
Vdc /4
C1
S2
S3
Vdc /4
C2
S4
Vdc
Va
,
S1
Vdc /4
C3
,
S2
S3
Vdc /4
C4
,
S4
Output
VAO
V5 = Vdc
V4 = 3dc/4
V3= Vdc/2
V2 = Vdc/4
V1=0
Sa1
1
0
0
0
0
Sa2
1
1
0
0
0
Sa3
1
1
1
0
0
Switch State
Sa4
Sa'1
1
0
1
1
1
1
1
1
0
1
21
Sa'2
0
0
1
1
1
Sa'3
0
0
0
1
1
Sa'4
0
0
0
0
1
indicates that the switch is ON and state 0 indicates that the switch is OFF. It is obvious
from this table that in each cycle just four switches should be ON. It is evident from the table
that a diode-clamped multilevel inverter does not possess phase redundancies. Instead it has
only line-line redundancies [2, 7]
From the application point of view, multilevel diode-clamped inverter can act as an
interface between a high-voltage dc transmission line and an ac transmission line [2]. Another
application would be as a variable speed drive for high-power medium-voltage (2.4 kV to
13.8 kV) motors as proposed in [2, 7, 18, 19]. Static var compensation is an additional
function for which several authors have proposed for the diode-clamped converter. The
advantages and disadvantages of diode-clamped multilevel inverter are listed below [2, 3, 4,
6].
Advantages:
All the phases share a common DC bus, which minimizes the capacitance requirement
of the inverter.
Disadvantages:
Voltage sharing between the DC-link capacitors becomes an issue as the number of
output levels increases.
Requirement of large number of clamping diodes for number of output levels greater
than 3.
22
flying-capacitor multilevel inverter. It can be observed that the flying-capacitor inverter does
not require all of the switches that are active to be in a consecutive series as in a diodeclamped inverter.
As evident from Table 2.2, flying-capacitor multilevel inverter possesses phase
redundancies. In other words, there can be more than a single switching combination to
generate the same voltage level. These redundancies can be incorporated in the control
strategy which ultimately helps in regulating the voltage across the dc-link capacitors. The
main advantages and disadvantages of flying-capacitor multilevel inverter are listed below [2,
3, 4, 6].
S1
Vdc /4
C1
S2
Cc
S3
Vdc /4
Cb
C2
S4
Vdc
Cc
Ca
Va
,
S1
Vdc /4
C3
Cb
,
S2
Cc
,
S3
Vdc /4
C4
,
S4
Output
VAO
V5 = Vdc
V4 = 3Vdc/4
V3= Vdc/2
V2 = Vdc/4
V1=0
Sa1
1
1
1
1
0
Sa2
1
1
1
0
0
Sam-1
1
1
0
0
0
Switch State
Sam
Sa'1
Sa'2
1
1
0
0
1
0
0
1
1
0
1
1
0
1
1
Sa'm-1
0
0
0
1
1
Advantages:
Ability to ride through short duration outages and deep voltage sags.
23
Sa'm
0
0
0
0
1
Disadvantages:
Complex control strategy is needed to track the voltage across all the capacitors. Also
pre charging of all the capacitors to the same voltage level thus making the start up
process complicated.
Switching utilization and efficiency are poor for real power transmission.
S1a
S1b
Vdc
Va1
S1a
S1b
Vo
S2a
S2b
Vdc
Va2
S2a
S 2b
24
Output
VAO
V5 = Vdc
V4 = 2Vdc
V3=- Vdc
V2 =-2 Vdc
V1=0
Sa1
1
1
0
0
1
Sa2
0
0
1
1
1
Sa3
1
1
1
0
1
Switch State
Sa4
Sa'1
Sa'2
1
0
1
0
0
1
1
1
0
1
1
0
1
0
0
Sa'3
0
0
0
1
0
Sa'4
0
1
0
0
0
Due to its structure and modularity, it has been proposed for such applications as static
var generation, an interface with renewable energy sources, and for battery-based
applications. Three-phase cascaded inverters can be connected in wye or in delta. Peng has
demonstrated a prototype multilevel cascaded static var generator connected in parallel with
the electrical system that could supply or draw reactive current from an electrical system [2225]. Peng [23] and Joos [26] have also shown that a cascade inverter can be directly
connected in series with the electrical system for static var compensation. Cascaded inverters
are ideal for connecting renewable energy sources with an ac grid, because of the need for
separate dc sources, which is the case in applications such as photovoltaic or fuel cells.
Cascaded inverters have also been proposed for use as the main traction drive in
electric vehicles, where several batteries or ultra capacitors are well suited to serve as separate
DC sources [27, 28]. The cascaded inverter could also serve as a rectifier/charger for the
batteries of an electric vehicle while the vehicle was connected to an ac supply. Additionally,
the cascade inverter can act as a rectifier in a vehicle that uses regenerative braking.
Major advantages and disadvantages of cascaded H-bridge inverter are listed below
[2, 3, 4, 6].
Advantages:
The number of possible output voltage levels is more than twice the number of dc
sources.
The series of H-bridges makes for modularized layout and packaging. This will enable
the manufacturing process to be done more quickly and cheaply.
Disadvantages:
Isolated dc sources are required for each H-bridge. This will limit its application to
areas where there is availability of multiple dc sources.
25
=2
+ 1
(2.1)
=1
where k denotes the number of DC voltage sources and Vdi denotes the normalized dc
voltage of each cell with respect to the dc link capacitor voltage. Thus for the asymmetric
configuration shown in Fig. 2.10, the number of output voltage levels is 2(1+3)+1 = 9.
Although the number of power switches and associated gate driver circuits are reduce
greatly in asymmetric multilevel inverters, this may lead to following compromises and
challenges:
Loss of modularity
26
Diode
Flying
Cascaded
Clamped
Capacitor
H-Bridge
Clamping Diodes
12
(N-1)(N-2)
Floating Capacitors
(N-1)(N-2)/2
(N-1)
(N-1)
(N-1)/2
2(N-1)
2(N-1)
18
(N2+3N-4)/2
10
5(N-1)/2
Topology
DC-link Capacitors/Isolated
4
supplies
Main Switches(with diodes)
24
2(N-1)
N2-1
1000
Diode Clamped
Flying Capcitor
Cascaded H-Bridge
900
800
700
600
500
400
300
200
100
0
10
15
20
Number of levels
25
Fig. 2.9 Number of components required for classical multilevel inverter topologies
27
30
Low
Switching
Frequency
Selective
Harmonic
Elimination
High
Switching
Frequency
Hybrid
Modulation
Multicarrier
PWM
Space Vector
Modulation
Carrier based PWM: This method includes the comparison of a reference sinusoidal
signal with triangular carrier signals which are modified either horizontally or
vertically to reduce the harmonic content in the output.
Space Vector PWM (SVM): The space vector modulation (SVM) algorithm is
basically also a PWM strategy with the difference that the switching times are
28
computed based on the three-phase space vector representation of the reference and
the inverter switching states rather than the per-phase in time representation of the
reference and the output levels.
Hybrid modulation is a method which basically works on both low and high switching
frequency. It is used for the modulation of CHB inverter with asymmetric configuration. The
main purpose is to reduce the switching losses of the power switches present in higher power
cells. Therefore, instead of using high frequency carrier-based PWM methods in all the cells,
the high-power cells are operated with square waveform patterns, switched at low frequency,
while only the small power cell is controlled with unipolar PWM [4].
Due to simplicity and popularity of carrier based PWM; this method is analyzed in
detail in this chapter and will be applied for modulation in the proposed work.
1 + 2 =
(2.2)
(2.3)
where T1 is the switching time where the reference signal is lower than the carrier. V1
is the minimum voltage and is generated by subtraction of reference and carrier signals when
the reference is lower than carrier. T2 is the switching time where the reference signal is
higher than the carrier and V2 is the maximum voltage and is generated by subtraction of
reference and carrier signals when the reference is higher than carrier.
29
D1
D2
V2
Vavg
Reference
Carrier
V1
0
T1
T2
Ts
( 2 )
(2 1 )
(2.4)
2 =
( 1 )
(2 1 )
(2.5)
The equation (2.2) shows a linear relation between switching times and average of output
voltage. The previous equations can be rewritten based on duty cycles (Dk), i.e. the ratio of
conduction times (Tk) and total switching period (Ts):
=
And
, = 1, 2
(2.6)
1 1 + 2 2 =
(2.7)
1 + 2 = 1
(2.8)
From equation (2.5), it can be concluded that duty cycles can be stated as normalized
form of average voltages. For example, duty cycle D2 corresponds to average voltage Vavg for
mapping [V1, V2] [0, 1]. Also, according to equation (2.2) switching times can be
calculated. In addition, desired output voltage can be compared with a linear ramp wave in
the switching period. Thus, if desired voltage is higher than ramp, higher level of output
voltage is selected; otherwise lower level is selected.
There are different methods to generate modulation signals [40]. All these methods
can be presented by similar graphic diagrams: a reference signal is compared to a carrier
signal and output state is selected based on which signal is higher at any moment. In selection
of carrier and reference signals there are some points which are mentioned below:
30
Carrier signal is usually a symmetric triangular wave, but a saw tooth wave can be
used either. Important fact is that the symmetric signal generates fewer harmonic [40].
The reference signal can be continuous or sampled synchronous with carrier signal.
The second method usually generates fewer harmonics. Since today digital controllers
are used, this method is preferred [42].Fig. 2.12 shows an example of 2-level PWM.
1
-1
10
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
-1
( 1)
(2.9)
31
(2.10)
A number of varieties of multilevel PWM are present which are mostly based upon
the variation of either the carrier or the reference signal. These are shown in the Fig. 2.13 [45,
49]
Multilevel
PWM
Variation in
Reference Signal
Variation in Carrier
Signal
Pure Sinusoidal
Level Shifted
Third Harmonic
Injection
Phase Shifted
Switching Frequency
Optimal
Dead Band
Super Imposed
Carrier
Other Techniques
Phase Disposition (PD-PWM): wherein all the carrier signals are in same phase.
Phase Opposition Disposition (POD-PWM): wherein the carrier signals above the
zero are out of phase with those below the zero by 180.
32
Examples of these methods for a 5-level inverter are shown in Fig. 2.14 to Fig. 2.16.
1
-1
1 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
-1
-1
1 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
-1
-1
1 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
-1
33
the modulation of an N-level inverter where the phase shift s between the adjacent carrier
signals is given by,
=
360
( 1)
(2.11)
180
( 1)
(2.12)
Equation 2.10 and 2.11 are applicable for flying-capacitor and cascaded H-bridge
inverter respectively.
1
-1
1 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
-1
-1
1 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
-1
0.018
This phase shift depends upon the number of levels in output i.e. 180 for a 5-level
inverter, 120 for a seven-level inverter, 90 for a nine-level inverter and so on [45, 46, 49].
With the increase in the number of levels, more carrier signals are included. In general, N-1
carrier signals will be required for an N-level inverter. Fig2.18. shows the LPS-PWM method
for a five level inverter.
2.3.2.4 Super Imposed Carrier PWM (SIC-PWM)
This technique of modulation uses a single carrier signal which is symmetrical with
respect to zero. This carrier signal is then superimposed with the sinusoidal reference signal
as shown in the Fig. 2.19.
1
0
-1
1 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0
-1
1 0
0
-1
-1
10
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
-1
35
region. The DC utilization means the ratio of the output fundamental voltage to the DC link
voltage. Methods like THIPWM, SFOPWM, Dead Band control etc. belong to this category.
Of various such methods, THIPWM and SFOPWM will be discussed in the next subsection.
It should be noted that carrier orientation for these methods can be either level-shifted or
phase-shifted.
2.3.2.6 Third Harmonic Injection PWM (THI-PWM)
In this method, the sinusoidal reference signal is injected by a third harmonic with a
magnitude of 25% of the fundamental [45, 47, 49]. The resulting signal is a flat topped
waveform which is shown in Fig. 2.21.
1
0
-1
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.5
0
1
0
-1
Fig. 2.21 Third harmonic signal superimposed with the reference signal
This resultant is then compared with N-1 carrier signals to generate the N-level output.
It should be noted that this scheme introduces third harmonic in the line to neutral waveform.
However, for a balanced load with floating neutral point, third harmonic current cannot flow
and hence third harmonic voltage is absent in line to line waveform. The flat topped
waveform allows for over modulation while maintaining excellent ac term and dc term
spectra. Thus this scheme acts as an alternative to improve the output voltage without
entering the over-modulation range. So any carriers employed for this reference will enhance
the output voltage by 15% without increasing the harmonics [47, 57].
1
-1
10
0.002
0.004
0.006
0.008
0.01
0.012
0.014
-1
36
0.016
0.018
During the dead band interval the power devices of one of the three-phases are not
switched. This results in a 33% reduction in the average switching frequency compared to
conventional carrier based techniques thereby reducing the associated switching losses. On
the other hand, use of this scheme gives rise to larger harmonic losses. The reference curve
can not only be superimposed by third harmonic but also by a dc offset
7th
9th
5th
harmonic harmonic harmonic
(%)
(%)
(%)
Modulation
Scheme
THD(%)
3rd
harmonic
(%)
2-level PWM
133.02
0.03
0.04
0.01
0.04
PD-PWM
35.99
0.00
0.01
0.01
0.01
POD-PWM
35.89
0.30
0.01
0.33
0.20
APOD-PWM
36.09
0.02
0.01
0.01
0.02
PS-PWM
36.15
0.06
0.04
0.02
0.04
LPS-PWM
36.09
0.02
0.02
0.01
0.02
SIC-PWM
26.91
0.01
0.02
0.02
0.01
THI-PWM
32.98
12.51
0.02
0.00
0.02
SFO-PWM
38.04
20.68
0.03
0.01
2.06
37
Table 2.5 also shows that the lower order harmonic profile in PD-PWM, POD-PWM,
APOD-PWM, PS-PWM and CSI-PWM method is significantly improved. LPS-PWM
incorporates the advantages of both LS-PWM and PS-PWM methods thus allowing for lower
THD as well as even distribution of switch device usage. Also the overall THD is quite less
than the 2-level PWM method which verifies the advantages of using multicarrier PWM.
Modulation schemes like THIPWM and SFOPWM are optimized PWM methods in
which the third harmonic content is significantly higher. Thus these methods are used for
three-phase systems in which the third harmonic is absent. However, the injection of third
harmonic in these optimized PWM methods increases the available linear modulation region
to reduce the THD in three-phase systems.
2.5 SUMMARY
In this chapter, conventional topologies of multilevel inverters have been investigated.
First, different topologies of multilevel inverters, their advantages and disadvantages have
been discussed. A comparison has been made between the three major multilevel inverter
topologies and it was shown for drives applications implementation of NPC topology is easy.
In this chapter classification for multilevel modulation techniques was shown. The focus was
then shifted on the carrier based PWM techniques in which the principle of 2-level PWM was
discussed. After this, multilevel or multicarrier PWM was discussed under which modulation
schemes which are either based on variation of carrier signal or reference signal were
covered. A comparison between these modulation schemes was done on the basis of overall
THD and presence of lower order harmonics. Finally, the effect of modulation index on the
level utilization for a multilevel inverter was discussed.
38
CHAPTER 3
NEUTRAL POINT CLAMPED MULTI- LEVEL
INVERTER
39
CHAPTER 3
Different multilevel topologies discussed in previous chapter among them neutral point
clamped multilevel inverter is easily implemented for 3 phase circuits. For drives applications
performance of 3 phase 3 level neutral clamped multi level inverter is better than others. This
topology gives the better voltage, current harmonic spectrum for connect the motor drive.
3.1 INRODUCTION
The most commonly used multilevel topology is the diode clamped inverter, in which the
diode is used as the clamping device to clamp the dc bus voltage so as to achieve steps in the
output voltage. Fig. 3.1 shows the circuit for a diode clamped inverter for a three-level and a
four-level inverter. The key difference between the two-level inverter and the three-level
inverter are the diodes D1 and D2. These two devices clamp the switch voltage to half the
level of the dc-bus voltage. In general the voltage across each capacitor for an N level diode
clamped inverter at steady state is V dc/n-1. Although each active switching device is only
required to block V, the clamping devices have different ratings. The diode-clamped inverter
provides multiple voltage levels through connection of the phases to a series of capacitors.
According to the original invention, the concept can be extended to any number of levels by
increasing the number of capacitors. Early descriptions of this topology were limited to threelevels [4] where two capacitors are connected across the dc bus resulting in one additional
level. The additional level was the neutral point of the dc bus, so the terminology neutral
point clamped (NPC) inverter was introduced [4]. However, with an even number of voltage
levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is
sometimes applied [5]. Due to capacitor voltage balancing issues, the diode-clamped inverter
implementation has been limited to the three levels. Because of industrial developments over
the past several years, the three level inverter is now used extensively in industry
applications.
3.2 ANALYSIS OF NPC
In general for a N level diode clamped inverter, for each leg 2 (N-1) switching devices,
(N-1) * (N-2) clamping diodes and (N-1) dc link capacitors are required. When N is
sufficiently high, the number of diodes and the number of switching devices will increase and
make the system impracticable to implement. If the inverter runs under pulse width
modulation (PWM), the diode reverse recovery of these clamping diodes becomes the major
40
design challenge. Though the structure is more complicated than the two-level inverter, the
operation is straightforward and well known [5]. In summary, each phase node (a, b, or c) can
be connected to any node in the capacitor bank (V3, V2, V1). Connection of the a-phase to
positive node, V3 occurs when S1ap and S2ap are turned on and to the neutral point voltage,
When S2ap and S1an are turned on and the negative node V1 is connected when S1an and S2an
are turned on. There are some complementary switches and in a practical implementation,
some dead time is inserted between the gating signals and their complements meaning that
both switches in a complementary pair may be switched off for a small amount of time
during a transition. However, for the discussion herein, the dead time will be ignored. From
Fig. 3.1, it can be seen that, with this switching state, the a-phase current Ia will flow into the
junction through diode D1a if the current is negative or out of the junction through diode D2a if
the current is positive. The dc currents I3, I2, and I1 are the node currents of the inverter.
(3.1)
Vb0=HbNVN0+HbN-1VN-10+.....+Hb1V10
(3.2)
Vc0=HcNVN0+HcN-1VN-10+.....+Hc1V10
(3.3)
41
(3.4)
IN-1= HaN-1Ia+HbN-1Ib+HcN-1Ic
(3.5)
I1= Ha1Ia+Hb1Ib+Hc1Ic
(3.6)
The above relationships may be programmed into simulation software to form a block
that simulates one phase of a diode-clamped inverter. A number of blocks can be connected
together for a multiphase system. For more simulation details, the transistor and diode KVL
and KCL equations may be implemented. This allows inclusion of the device voltage drops
(as well as conduction losses) and also the individual device voltages and currents. To express
this relationship, consider the general N-level diode-clamped structure. Therein, only the
upper half of the inverter is considered since the lower half contains complementary
transistors and may be analyzed in a similar way. Through the clamping action of the diodes,
the blocking voltage of each transistor is the corresponding capacitor voltage in the series
bank. The inner diodes of the multilevel inverter must block a higher voltage. For example, in
the four-level topology the inner diodes must block two-thirds of the dc voltage while the
outer diodes block one-third. This is a well-known disadvantage of the diode-clamped
topology. For this reason, some authors represent the higher voltage diodes with lower
voltage diodes in series [6] or alter the structure of the topology so that each diode blocks the
same voltage [7].
Finally, the capacitor junction currents may be expressed as the difference of two
clamping diode currents. In case of a three-level inverter, the expression reduces to
C1pVc1=-Idc+Ha3Ia+Hb3Ib+Hc3Ic
(3.7)
C1pVc2=-(Idc+Ha1Ia+Hb1Ib+Hc1Ic)
(3.8)
42
S1 and S2 on. A simple gate signal, repeated zero-level patterns, is shown in Fig. 3.2. All
zero levels are generated by turning on S1 and S2.
Output
waveform
-VDC/2
S1
S2
S1
S2
43
CHAPTER 4
SIMULATION STUDIES
44
CHAPTER 4
SIMULATION STUDIES
In previous chapter discussed the neutral point clamped multi level inverter operation
based on that operation to simulate the neutral point clamped inverter by using
MATLAB/Simlink with different modulation techniques.
The simulation for 3-level single-phase and five-phase inverter is performed using Sim
Power electronics toolbox in MATLAB/SIMULINK environment. The simulation model is
shown in Fig. 4.1 &. Modulation index M is defined as,
=
2
( 1)
(4.1)
45
Value
0.01 , 105
V dc
24 volts
Load
R = 78 , L = 36 mH
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
Fig. 4.2 Line Voltage & Current waveforms of 3-level NPC-MLI with R-load
46
Fig. 4.3 Line Voltage & Current waveforms of 3-level NPC-MLI with RL-load
Value
0.01 , 105
V dc
200 volts
Load
R = 78 , L = 36 mH
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
Fig. 4.6 Phase Voltage & Current waveforms of 3-level NPC-MLI with R L-load
(a)
(b)
(c)
(d)
Fig 4.7 Harmonic spectrum of a phase voltage (a)PD (b)POD (c)APOD (d)LS
48
The voltage THD Of a PD, POD, APOD & LS are 37.63%, 39.91%, 42.57% and
37.59% respectively. The harmonic spectrum of phase voltage with a different modulation
techniques are show in Fig. 4.7. The %THD of a voltage is better with the PD, LS
modulations techniques because of more modulation index. While using PD, LS modulation
schemes less stress on switches.
4.2.2 3phase3-Level Inverter:
The simulink model of a 3 level 3 phase NPC multilevel inverter is shown in the Fig.
4.8. The input voltage of 100 volts is separated by DC link. To give a gate pulse to the
respective IGBTs having parameters are shown in Table 4.3 and the line voltage& line
current waveforms and phase voltage & phase current with a simple R-L load of 78, 36mh
is shown in the Fig. 4.9 & 4.10 respectively.
Value
0.01 , 105
V dc
100 volts
Load
R = 78 , L = 36 mH
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
49
Fig. 4.9 Line voltage & line current of a 3 phase 3 level NPC- MLI
The line voltage and line currents are 50v & 2.3A. The voltage and current THD are
shown in the Fig. 4.11& 4.12 respectively. The voltage THD is of a 3phase 3level NPC is
23.65% and current THD is 1.68%.
Fig. 4.10 Phase voltage & phase current of a 3 phase 3 level NPC- MLI
Using single pulse width modulation the harmonic spectrum of a 3 level is more than
sinusoidal pulse width modulation because it is having better duty ratio
50
Value
0.01 , 105
V dc
100 volts
Load
R = 78 , L = 36 mH
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
51
(a)
(b)
(c)
(d)
Fig 4.14 Harmonic spectrum of a phase voltage (a)PD (b)POD (c)APOD (d)LS
Fig. 4.15 Phase voltage & phase current of a 3 phase 5 level NPC- MLI
Fig. 4.16 Line voltage & line current of a 3 phase 5 level NPC- MLI
The %THD of a 3 level is better than 5 level inverter because incensing number of
levels there is problem with a dc link. While increasing the number of levels number of dc
link capacitors also increased so that difficult to balancing the voltage level.
53
4.3 COMPARISON
A Comparison made between 3 level and 5 level with a different modulation techniques
as PD,POD,APOD & PS of a %THD of current and voltage as show in Table 4.5.
TABLE 4.5 COMPARISON OF 3 & 5 LEVEL INVERTER WITH DIFFERENT
MODULATION TECHNIQUES
3 LEVEL
5 LEVEL
PD
POD
APOD
PS
PD
POD
APOD
PS
Voltage
37.63
39.91
42.57
37.59
36.89
39.41
41.69
35.81
Current
12.25
13.82
17.12
14.89
11.23
13.56
16.14
11.34
5.3 SUMMARY
This chapter shows the simulation results for both single-phase and three-phase NPC
inverters with a Single pulse and sinusoidal pulse width modulation. Simulink models of both
the cases are developed in MATLAB/SIMULINK environment. Waveforms for output
voltage and current in both the cases are shown and analyzed. In comparison of 3 level and 5
level NPC MLI with a different modulation techniques. The phase disposition (PD) and phase
shift (PS) having a better harmonic spectrum because of more modulation index. 3 level 3
phase inverter is a better for motor drives applications because of 5 level having a problem
with a voltage balancing of dc link it is rectified by closed loop so that increasing the number
of levels with the difficulty with the voltage balancing.
54
CHAPTER 5
55
CHAPTER 5
The Design of three-level inverter is divided into two parts. One is hardware design
and other is software design. Hardware design includes component-rating selection and power
circuit. Software design includes the Core algorithms for three-level Neutral point clamped
(NPC) inverter operations. The block diagram of the proposed inverter scheme is shown Fig.
5.1. Here TMS320f28335 processor is used to generate the gate pulses. An ePWM module is
used to generate the gate pulses and is driven through gate driver circuit to give the pulses to
the switches.
DC
Source
3- level
NPC
Inverter
Load
Gate
Driver
TMS320f28335
Fig. 5.1 Block Diagram for Hard ware Implementation
56
device.The ePWM modules are chained together via a clock synchronization scheme that
allows them to operate as a single system when required. Additionally, this synchronization
scheme can be extended to capture peripheral modules (eCAP). The number of modules is
device-dependent and based on target application needs. Modules can also operate standalone.
Each ePWM module supports the following features:
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following
configurations
Two independent PWM outputs with single-edge operation
Two independent PWM outputs with dual-edge symmetric operation
One independent PWM output with dual-edge asymmetric operation
Programmable phase-control support for lag or lead operation relative to other ePWM
modules.
57
Dead-band generation with independent rising and falling edge delay control.
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault
A trip condition can force either high, low, or high-impedance state logic levels at PWM
Outputs
All events can trigger both CPU interrupts and ADC start of conversion (SOC)
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
In DSPf28335 there are 6 ePWM peripherals which are connected as shown in the
Fig.. 5.2. Seven sub modules are included in every ePWM peripheral. Each of these sub
modules performs specific tasks that can be configured by software. The block diagram
showing the sub modules of an ePWM module is shown in the Fig.. 5.3.
58
Configure the rate of the time-base clock; a prescaled version of the CPU system
clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a
slower rate.
Register
Address offset
Shadowed
Description
TBCTL
0x0000
No
TBSTS
0x0001
No
TBPHSHR
0x0002
No
TBPHS
0x0003
No
TBCTR
0x0004
No
TBPRD
0x0005
Yes
59
Generates events based on programmable time stamps using the CMPA and CMPB
registers
CTR = CMPA: Time-base counter equals counter-compare A register (TBCTR =
CMPA).
CTR = CMPB: Time-base counter equals counter-compare B register (TBCTR =
CMPB)
Controls the PWM duty cycle if the action-qualifier sub module is configured
appropriately
Shadows compare values to prevent corruption or glitches during the active PWM
cycle
60
Register Name
Address Offset
Shadowed
Description
CMPCTL
0x0007
No
CMPAHR
0x0008
Yes
CMPA
0x0009
Yes
Counter-Compare A Register.
CMPB
0x000A
Yes
Counter-Compare B Register.
Qualifying and generating actions (set, clear, toggle) based on the following events:
CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
CTR = CMPA: Time-base counter equal to the counter-compare A register
(TBCTR = CMPA)
CTR = CMPB: Time-base counter equal to the counter-compare B register
(TBCTR = CMPB)
Providing independent control of events when the time-base counter is increasing and
when it is decreasing.
Register
Address
offset
Shadowed
Description
AQCTLA
0x000B
No
AQCTLB
0x000C
No
AQSFRC
0x000D
No
AQCSFRC
0x000E
Yes
The action-qualifier submodule controls how the two outputs EPWMxA and
EPWMxB behave when a particular event occurs. The event inputs to the action-qualifier
submodule are further qualified by the counter direction (up or down). This allows for
independent action on outputs on both the count-up and count-down phases. Actions are
61
specified independently for either output (EPWMxA or EPWMxB). Any or all events can be
configured to generate actions on a given output. For example, both CTR = CMPA and CTR
= CMPB can operate on output EPWMxA. For clarity, the drawings in this document use a
set of symbolic actions. These symbols are summarized in Fig. 5. Each symbol represents an
action as a marker in time. Some actions are fixed in time (zero and period) while the CMPA
and CMPB actions are moveable and their time positions are programmed via the countercompare A and B registers, respectively. To turn off or disable an action, use "Do Nothing
option"; it is the default at reset. The possible Action-Qualifier Actions for EPWMxA and
EPWMxB are shown in the Fig. 5.6.
Fig. 5.6 Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
62
Can be totally bypassed from the signal path (note dotted lines in diagram)
Register
Address
offset
Shadowed
Description
DBCTL
0x000F
No
DBRED
0x0010
No
DBFED
0x0011
No
mnemonic
Address offset
Shadowed
Description
PCCTL
0x001E
No
Trip inputs TZ1 to TZ6 can be flexibly mapped to any ePWM module.
Upon a fault condition, outputs EPWMxA and EPWMxB can be forced to one of the
following:
Support for one-shot trip (OSHT) for major short circuits or over-current conditions.
Register
Address offset
Shadowed
Description
TZSEL
0x0012
No
Reserved
0x0013
--
---
TZCTL
0x0014
No
TZEINT
0x0015
No
TZFLG
0x0016
No
TZCLR
0x0017
No
TZFRC
0x0018
No
Uses prescaling logic to issue interrupt requests and ADC start of conversion at:
Every event
Every second event
64
Provides full visibility of event generation via event counters and flags
Register Name
Address offset
Shadowed
Description
ETSEL
0x0019
No
ETPS
0x001A
No
ETFLG
0x001B
No
ETCLR
0x001C
No
ETFRC
0x001D
No
65
START
END
Value
0.01 , 105
V dc
10 volts
Load
R = 94
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
The Phase voltage & current waveforms of a NPC 3-level inverter with resistive load
of R= 76 ohm is shown in the Fig. 5.10 are 5.36 volts, 68.5mA respectively. The harmonic
spectrums of phase voltage& phase currents are shown in the Fig.5.11 (a) & (b) respectively.
The % THD of a voltage is 26.5% and %THD of a current is 26% which is nearly equal to
simulation results as shown in Fig 4.2 discussed in chapter 4.
The %THD is better for NPC MLI while connect the motor this is no harm to the
circuit.
Fig. 5.10 phase voltage & current wave forms of a NPC 3-level inverter with R-load
67
(a)
(b)
Fig. 5.11 Harmonic spectrum of (a) Phase voltage (b) phase current
Value
0.01 , 105
V dc
10 volts
Load
R = 61 ,L=0.01
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
The Phase voltage& current waveforms of a NPC 3-level inverter with R-L load of R=
61 , L= 0.1 mH is shown in the Fig. 5.12. Form this wave forms the phase voltage is 5.31v
and current is 147mA. Here small inductance value is taken because of that theirs is no phase
difference between current and voltage the power factor is 0.93.And harmonic spectrums of
phase voltage& phase currents are shown in the Fig.. 5.13(a) & (b) respectively. The values
of voltage & current harmonic spectrum are 26.5% and 26.1% respectively.
Fig. 5.12 phase voltage & current wave forms of a NPC 3-level inverter with R-load
68
(a)
(b)
Fig. 5.13 Harmonic spectrum of (a) Phase voltage (b) phase current
R= 30 , L=76.835 mH
To give 10 volts dc voltage form dc source, capacitor link separate the dc voltage. By
using DSP the generated gate pulse to required switches will get a rms ac output voltage as
5.24v by using the parameters as show in Table 5.10
TABLE 5.10 PARAMETERS OF THE HARDWARE MODEL FOR RL LOAD
Parameters
Value
0.01 , 105
V dc
10 volts
Load
R = 30 ,L=76.85mH
Modulation Index M
f carrier
0.85
1 kHz
f ref
50 Hz
2200F, 200 m
The Phase voltage& current waveforms of a NPC 3-level inverter with R-L load of R=
30 , L= 76.85 mH is shown in the Fig. 5.14. Form this wave forms the phase voltage is
5.31v and current is 147mA. Because of inductance value form the Fig 5.14 clearly observes
that the phase displacement between current and voltage and the power factor is 0.77. The
harmonic spectrums of phase voltage& phase currents are shown in the Fig. 5.15(a) & (b)
respectively. The values of voltage & current harmonic spectrum are 27.9% and 10.7%
respectively. Clearly observe form the %THD of current is less than to connect the R load. It
is nearly equal to the simulation results as show in Fig 4.3 discussed in chapter 4.
69
Fig. 5.14 phase voltage & current wave forms of a NPC 3-level inverter with R-load
(a)
(b)
Fig. 5.15 Harmonic spectrum of (a) Phase voltage (b) phase current
5.5 SUMMARY
This chapter analyze the experimental results of a 3 level neutral point clamped multi
level inverter with an R and RL load. While observing the experimental results the voltage
and current waveforms having less number of even harmonics and better harmonic spectrum.
When connected the R L load the phase different between voltage and current also observed
and the harmonics spectrum of the current is decreased so that to connect a induction motor
which is also a R L Load
70
CHAPTER 6
CONCLUSION & FEATURE SCOPE
71
CHAPTER 6
6.1 CONCLUSION
The multilevel inverter topology can overcome some of the limitations of the Standard
two-level inverter. Output voltage and power increase with number of levels. Harmonics
decrease as the number of levels increase. In addition, increasing output voltage does not
require an increase in voltage rating of individual devices. In the thesis, several multilevel
voltage source inverters and their modulation topologies are introduced and the Neutral point
clamped multilevel inverter for drives applications.
This work presents the different modulation techniques i,e PD,POD,APOD,PS. For
NPC-MLI used different modulation techniques among these modulation techniques PD, LS
has a better %THD because of more duty ratio.
The NPC-MLI for 3-level with single pulse modulation and 3 phase 3-level & 3 phase
5 level with SPWM also simulated and the voltage& current harmonic spectrum is compared
for R-L load. The hardware is implemented for single pulse modulated NPC-MLI inverter
using DSPf28335. DSP& FPGA processors are the effective solution for controlling the gate
signals of the multilevel inverters. The THD of voltage& current for R& R-L loads are
observed. This 3 level inverter has the better harmonic profile comparing with a conventional
two level inverter. From the simulation and experimental results NPC-MLI has a better
harmonic spectrum than other MLI topologies. 3 phase-3 level NPC- MLI is easy to
implement and this topologies can be applicable for the Drives application& Renewable
energy applications.
72
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78
APPENDEX
**********************************************************************
* File: NPC.c
* Devices: TMS320F2833x
**********************************************************************
#include "DSP28x_Project.h"
EPwm1Regs.TBPHS.half.TBPHS = 0x0000;
EPwm1Regs.TBCTR = 0x0000;
// Phase is 0
// Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
79
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV8;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
// Setup compare
EPwm1Regs.CMPA.half.CMPA = 4687;
EPwm1Regs.CMPB = 42188;
// Set actions
EPwm1Regs.AQCTLA.bit.CBU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;
// Active Low complementary PWMs - setup the deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
EPwm1Regs.DBFED = 100;
EPwm1Regs.DBRED = 100;
// Interrupt where we will modify the deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
EPwm1Regs.ETSEL.bit.INTEN = 1;
// Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;
}
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 46875;
EPwm2Regs.TBPHS.half.TBPHS = 0x0000;
EPwm2Regs.TBCTR = 0x0000;
// Phase is 0
// Clear counter
// Setup TBCLK
80
EPwm1Regs.TBCTL.bit.SYNCOSEL =TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV8;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4;
// Setup compare
EPwm2Regs.CMPA.half.CMPA = 4687;
EPwm2Regs.CMPB = 42188;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.CBD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET;
// Active Low complementary PWMs - setup the deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED = EPWM2_MIN_DB;
EPwm2_DB_Direction = DB_UP;
EPwm2Regs.DBFED = 100;
EPwm2Regs.DBRED = 100;
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
EPwm2Regs.ETSEL.bit.INTEN = 1;
// Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;
81