Documente Academic
Documente Profesional
Documente Cultură
Presented By
Siddhartha Sen, IIT Kharagpur
Under the Guidance of :
Prof. A. Dasgupta
Topics
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Packaging - 2
Types of Packages
z Though a wide variety of packages can be used for VLSI
devices, they can be broadly divided into two basic types:
{ Hermetic Ceramic Packages: The chip resides in an environment
decoupled from the external environment by a vacuum tight
enclosure. The packages are usually designed for high
performance applications that allow some cost penalties
{ Plastic Packages: The chip is not completely decoupled from the
external environment because it is encapsulated with resin
materials, typically epoxy based resins. They are extremely cost
competitive and their popularity persists because of rapid
advances in plastic technology
Packaging - 3
Molding
Material
Chip
Support
Paddle
Spot Plate
Bond Wires
Packaging - 6
Rents Rule
Prediction
z Rents Rule is an
empirical relationship
between the gate
count and the I/O
(Terminal) Count in a
Chip.
Microprocessors
Logic Array
DRAM
(Number of gates)
Typically:
= 4.5
= 0.5
Wafer Preparation
Wafer Backgrinding
Die Preparation
Die Bonding
Al wire / Au wire
Die Interconnection
Conformal Coating
Molding
Transfer molding
Polymer Adhesive
Metal Preform
Polymer Seal
Molding Compound
Flip Chip
Package Seal
Marking
DTFS
Packaging - 8
Ink Marking
Laser Marking
Deflash-Trim-FormSingulate
Wafer Backgrinding
z Wafer Backgrind is the process of grinding the backside
of the wafer to the correct wafer thickness prior to
assembly.
z Wafers normally undergo a cleaning and surface
lamination process prior to the actual backgrinding
process.
z The grinding wheel parameters are: speed, spindle
coolant water temperature and flow rate, initial and final
wafer thickness, and feed speeds.
z Continuous washing of the wafer is also done during the
backgrinding process to remove debris.
Packaging - 9
Die Preparation
z Wafer Mounting:
frame loading, wafer
loading, application of
tape to the wafer and
wafer frame, cutting of
the excess tape and
unloading of the
mounted wafer
z Wafer Saw:
alignment, cutting by
resin-bonded diamond
wheel, cleaning
Packaging - 10
Wafer Films
Die Bonding
z Die Bonding is the process of
attaching the silicon chip to the
die pad or die cavity of the
support structure.
z Adhesive Die Attach:
Uses adhesives such as
polyimide, epoxy and silver-filled
glass as die attach material
z Eutectic Die Attach:
Uses a eutectic alloy to attach
the die to the cavity. The Au-Si
eutectic alloy is the most
commonly used
Packaging - 11
Wire Bonds
Packaging - 12
Aluminum wires
wedge-bonded
z Highest Performance
{ reduces the delaying inductance and capacitance of the
connection by a factor of 10
{ highest speed electrical performance of any assembly method
z Most Rugged
z Lowest Cost
Packaging - 16
Molding
z Molding is the process of encapsulating
the device in plastic material.
z Transfer molding is one of the most
widely used molding processes in the
semiconductor industry.
z The cavities are filled up in a 'Christmas
tree' fashion - The highest filling velocity
is experienced by the first cavity.
z Subsequent cavities are filled with
increasing velocities until the last cavity,
which ends up with the second highest
filling velocity.
z Wiresweeping and die paddle
Packaging - 18
Mold Chases
Examples of Molds
Package Sealing
z Sealing is the process of encapsulating a hermetic
package, usually by capping or putting a lid over the
base or body of the package. The method of sealing is
generally dependent on the type of package.
z Ceramic DIPs, or cerdips, are sealed by topping the
base of the package with a cap using seal glass.
z Seal glass, like any glass, is a supercooled liquid which
exhibits tremendous viscosity when cooled below its
glass transition temperature. A seal glass may be
classified as vitreous or Devitrifying.
Packaging - 19
Marking
z Marking is the process of putting identification,
traceability, and distinguishing marks on the package of
an IC.
z The most common Ink marking process for semiconductor
products is Pad printing. Pad printing consists of
transferring an ink pattern from the plate, which is a flat
block with pattern depressions that are filled with ink, to
the package, using a silicone rubber stamp pad.
z Laser marking refers to the process of engraving marks
on the marking surface using a laser beam. There are
many types of lasers, but the ones used or in use in the
semiconductor industry include the CO2 laser, the YAG
laser, and diode lasers.
Packaging - 20
Deflash/Trim/Form/Singulation (DTFS)
1. Deflash - removal of flashes from the package of the
newly molded parts. Flashes are the excess plastic
material sticking out of the package edges right after
molding.
2. Trim - cutting of the dambars that short the leads
together.
3. Form - forming of the leads into the correct shape and
position.
4. Singulation - cutting of the tie bars that attach the
individual units to the leadframe, resulting in the
individual separation of each unit from the leadframe.
Packaging - 21
SiP Categories
Packaging - 23
3D Packaging: Introduction
z The driving forces are the significant
size and weight reductions, higher
performance, small delay, higher
reliability and reduced power.
z 3 D Packages score over
conventional packages in:
{ Size and Weight
{ Silicon Efficiency
{ Interconnect Usability and
Accessibility
{ Delay
{ Noise
{ Power Consumption
{ Speed
Packaging - 24
3 D Packaging: Advantages - I
z The shift from conventional single chip packages to 3D
technology, leads to substantial size and weight
reductions:
Volume ( in cm3 / Gbit )
Type
Capacity
Discrete
Planar
3D
Discrete/3D
Planar/3D
SRAM
1 Mbit
1678
783
133
12.6
5.9
DRAM
1 Mbit
1357
441
88
15.4
5.0
Capacity
Discrete
Planar
3D
Discrete/3D
Planar/3D
SRAM
1 Mbit
3538
2540
195
18.1
13.0
DRAM
1 Mbit
2313
1542
132
17.5
11.6
Packaging - 26
3 D Packaging: Advantages - II
z Increase in Silicon
Efficiency.
z Interconnect
Usability and
Accessibility.
Packaging - 27
z Delay Reduction
z Noise Reduction
z Power Reduction
z Speed Increase
Packaging - 28
3 D Packaging: Limitations
Packaging - 29
Packaging - 32
l<
c
v0 r
Packaging - 33
Stripline conductor
Microstrip conductor
Tx Line
Simultaneous
Switching
Noise
Packaging - 35
Electrical Considerations
z The Desirable Electrical Characteristics:
{ Low ground resistance (minimum power supply voltage drop)
{ Minimum Self Inductance of signal leads (short signal leads)
{ Minimum power supply spiking due to simultaneous switching of
signal lines.
{ Minimum Mutual Inductance and Cross Talk (short paralleled
signal runs)
{ Minimum Capacitive loading (short signal runs near a ground
plane)
{ Maximum use of Matched Impedances (avoid signal reflection)
Packaging - 36
Thermal Management
z Efficient and cost-effective removal of dissipated thermal
energy from the device to assure its reliable performance
over the long term.
z Effects of Increasing Temperatures:
{ Device physics is strongly influenced by the junction temperature
{ Corrosion and interfacial diffusion mechanisms
{ Approximately a 10C increase in temperature reduces the mean
time to failure by a factor of two
Packaging - 37
Packaging - 38
Thermal Management
z A Simplified Heat transfer model:
Heat is transferred from the chip
to the surface of the package by
conduction and from the
package to the ambient by
convection and radiation:
Ta
Thermal Convection
& Radiation
Tc
Conduction
Tj
JA = JC + CA
= ((Tj-Tc) + (Tc-Ta))/P
Chip
PWB
Thermal Considerations
z Conduction dominates heat transfer from chip to package surface.
One Dimensional Fouriers equation gives:
Q = (T1 T2)**(S/L)
In the actual package:
P = (Tj Tc)**(S/L)
Thus we have:
JC = (Tj Tc)/P = L/(*S)
z VLSI packages have a high packing density (small S) so high
thermal conductivity components such as Cu alloys lead frames, AlN
substrates and thermo-conductive molding compounds are
particularly important as they increase overall package value.
z Thinner packages (low L) are also important.
Packaging - 40
Thermal Considerations
z Convection: Heat transfer from the package surface to the ambient
results mostly from convection, given by Newtons Cooling Law:
Q = h*A*(Tc Ta)
Therefore:
CA = (Tc Ta)/P = 1/(h*A)
CA is reduced through increased conduction and larger package
surface area. The application system constructions are forced air
convections, liquid coolants in place of air coolings and additional
heat sinks attached to the package surface.
Packaging - 41
Thermal Considerations
z Radiation helps transfer some heat from the package surface to the
ambient, but usually the contribution is small.
According to Stefan-Boltzmann Law: Eb = **T4
The heat radiated is:
Q = *f*A*(T14 T24)
Where f is given by:
f = 1/((1/1)+(1/2)-1)
When T1-T2<<T1 & T1-T2<<T2, then with Tm=(T1+T2)/2, we can obtain:
Q = 4**f*Tm3*A*(T1-T2) = h*r*A*(T1-T2)
Therefore: rad = (T1-T2)/Q = 1/(h*r*A)
In actual applications black dyed packages and external heat sinks are
preferred since they increase hr values
Packaging - 42
Packaging - 43
Packaging - 44
Packaging - 46
Future Trends
z Package Pin Count will undoubtedly continue to increase with IC
complexity.
z Alumina Ceramic Packages will continue to dominate high
performance VLSI packaging technologies until their high dielectric
constant,modest thermal conductivity or cost force a change.
z Plastic Packages, specially posttransfer-mold plastic packages will
continue to dominate low cost VLSI packaging.
z Higher Packaging density on the PWB level will drive towards
smaller lead pitches, to approximately 0.3 mm spacings.
z Wire Bonding will be seriously challenged and will be replaced by
TAB and Flip Chip.
z System design will increasingly depend on systematically optimizing
the entire interconnection scheme to achieve the potential benefits
of improved silicon capability. The approach for MultiChip Modules
verifies this trend.
Packaging - 48
Packaging - 49