Documente Academic
Documente Profesional
Documente Cultură
FPGA
FPGA Design
Design Course
with
(by Atif Raza Jafri, Ph.D)
Modern EDA Tools
Theory
(A Course Series)
By:
Dr. Atif Raza Jafri, (Ph.D Embedded Systems)
Module II
FPGA Based SoC Design
C, C++
Entry
Embedded
IP-Based
Entry
RTL
Entry
Target Audience
Pre-Requisites
Objectives
Lab Work
ModelBased
Entry
Session 1
Sessions 2
Theory
Lab Work
GPIO Project
Single Interrupt Handling with Microblaze.
Interrupt Controller for multiple-Interrupt handling with
Microblaze.
Session 3
Theory
Course Duration:
Session 4
5 Sessions
3 Hour/ Session (may take longer during lab work)
20% Theory, 80% Lab work.
Course Detail
Lab Work
Creating Dual Port BRAM interface with Microblze.
Importing Microblaze based Embedded System in ISE
for creating bigger project.
Lab Work
Connecting Hardware Accelerator with Microblaze through FSL.
Connecting Hardware Accelerator with Microblaze through IPIF
Session 5
Experience
Theory
Lab Work
Using XMD Debug mode.
Enabling Cache Memory
DMA project.
Flash with FAT-32 System for PC compatible File operations.
Professionals
PKR. 20,000/- per person.
Faculty members
PKR. 15,000/- per person.
Student
PKR 7,500/- per person
Minimum 12, Maximum 20 participants.
Publications
Book Chapter
A.R. Jafri, A. Baghdadi, and M. Jezequel, ASIP Design and
Prototyping for Wireless Communication Applications, In
Advanced Applications Of Rapid Prototyping Technology In
Modern Engineering book, InTech Open Access Publisher,
2011, ISBN ISBN 978-953-307-698-0.
Journals
[1] A.R. Jafri, A. Baghdadi, and M. Jezequel, ASIP-based
Universal Demapper for Multiwireless Standards,
The inauguration issue of IEEE Embedded Systems Letters,
vol. 1, no. 1, pp. 9-13, May 2009.
[2] A.R. Jafri, A. Baghdadi, and M. Jezequel, Parallel MIMO
Turbo Equalization, IEEE Communication Letters, VOL. 15,
NO. 3, MARCH 2011.
Conferences
[3] A.R. Jafri, D. Karakolah, A. Baghdadi, and M. Jezequel,
ASIP-based Flexible MMSE-IC Linear Equalizer for MIMO
Turbo-Equalization Applications, In Proc. IEEE/ACM
Design, Automation and Test in Europe Conference &
Exhibition, DATE09, Nice, France, 21-23 April 2009.
[4] H.Moussa, O. Muller, A.R. Jafri,A. Baghdadi, J. Le Mestre,
and M. Jezequel, FPGA Prototypes For Turbo
[5]
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Islamabad, Pakistan.