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Based

FPGA
FPGA Design
Design Course
with
(by Atif Raza Jafri, Ph.D)
Modern EDA Tools

The objective of this module is to train the participants on


creating FPGA Based System on Chip using Embedded
Development Kit and ISE 14.2 Tool Suite from Xilinx.

Theory

(A Course Series)

By:
Dr. Atif Raza Jafri, (Ph.D Embedded Systems)

Module II
FPGA Based SoC Design
C, C++
Entry

Embedded
IP-Based
Entry

RTL
Entry

Project Managers responsible for the Medium complexity


Embedded System projects.
Faculty members willing to design Embedded System
course and conduct labs to the students on FPGA.
Fresh graduate engineers interested/tasked to work on
Embedded System application development.
The pre-requisite of this course is the knowledge of basic
digital design, HDL (VHDL/Verilog), fundamental knowledge of
processor architecture and C language for software application
development.

Outcome of the course

FPGA Based System On Chip

Project Creation in XPS


Hardware Generation.
Design Migration to SDK.
Software Application Development.
FPGA configuration for validation.

Target Audience

Pre-Requisites

Objectives

Overview of MicroBlaze Processor


Typical Usage of Microblaze
Overview of Xilinx Embedded Development Kit (EDK).
o
Xilinx Platform studio (XPS)
o
Software Development Kit (SDK)

Lab Work

A course series by,

ModelBased
Entry

Session 1

Sessions 2
Theory

GPIO with Microblaze.


Single/Multiple Interrupt handling.

Lab Work

GPIO Project
Single Interrupt Handling with Microblaze.
Interrupt Controller for multiple-Interrupt handling with
Microblaze.

Session 3

As the gate per unit silicon is increasing exponentially, a


designer can implement complex Systems on Single Chip (SoC).
If SoC is implemented on FPGA, additional margin of flexibility
is added to the advantage basket. This course is designed to
enable the participants in making SoC applications on FPGA in a
very short duration of time. The practical projects are created
in such a way that the trainees should be productive to
produce multi-I/O data recorders, system level testers and
application needing hardware accelerators with RISC
processor.

Theory

Course Duration:

Session 4

5 Sessions
3 Hour/ Session (may take longer during lab work)
20% Theory, 80% Lab work.

Course Detail

Connecting Microblaze with Hardware Accelerator through


o
Dual Port BRAM.
o
FSL
o
PLB

Lab Work
Creating Dual Port BRAM interface with Microblze.
Importing Microblaze based Embedded System in ISE
for creating bigger project.

Lab Work
Connecting Hardware Accelerator with Microblaze through FSL.
Connecting Hardware Accelerator with Microblaze through IPIF

Session 5

Experience

Theory

16 years in the field of Embedded Systems while working with


academia and industry in France, Italy, South Africa and China.
FPGA Based Projects Experience:
Design and Implementation of Application Specific
Instruction-set Processor (ASIP) based MIMO Equalizer [3].
Multi-Standard Demapper Design and prototyping [1].
FPGA Implementation of multi-ASIP and NoC based Turbo
Decoder [4].
FPGA based Heterogeneous multi-ASIP and Network on
Chip (NoC) based Unified Turbo Receiver for Multi
Wireless Standards comprised of 9 ASIPS and 3 NoCs [9].
Many small FPGA projects such as multi- serial port data
loggers, small SoCs comprised of Microblaze, hardware
accelerators, buses, memories and peripherals.
Texas Instrument DSP Processor and FPGA Based
Embedded System Design for Aviation Industry.

Options of Program Execution from External Memory.


o
Direct Execution
o
Cache Memory
DMA

Lab Work
Using XMD Debug mode.
Enabling Cache Memory
DMA project.
Flash with FAT-32 System for PC compatible File operations.

Course Fee Structure

Professionals
PKR. 20,000/- per person.
Faculty members
PKR. 15,000/- per person.
Student
PKR 7,500/- per person
Minimum 12, Maximum 20 participants.

For the above fee structure, facility equipped with PCs,

development software and FPGA boards shall be arranged


by the organizers.
Please request a price quotation if the course is to be
managed at clients premises.

For a group of student separate package can be offered.


Infrastructure and Lab Requirements
01 Personal Computer per 02 participants
01 Xilinx Spartan3A/E Starter FPGA Board per 02 students
Projector and white marker board.
Helping material e.g Videos and pdf files shall be provided on
DVDs along with solutions to the projects.

Resource Person Profile


Dr. Atif Raza Jafri
Ph.D in Embedded Systems
Contacts:
(+92) 323 8528929
Email: atifjafri@hotmail.com

Publications
Book Chapter
A.R. Jafri, A. Baghdadi, and M. Jezequel, ASIP Design and
Prototyping for Wireless Communication Applications, In
Advanced Applications Of Rapid Prototyping Technology In
Modern Engineering book, InTech Open Access Publisher,
2011, ISBN ISBN 978-953-307-698-0.
Journals
[1] A.R. Jafri, A. Baghdadi, and M. Jezequel, ASIP-based
Universal Demapper for Multiwireless Standards,
The inauguration issue of IEEE Embedded Systems Letters,
vol. 1, no. 1, pp. 9-13, May 2009.
[2] A.R. Jafri, A. Baghdadi, and M. Jezequel, Parallel MIMO
Turbo Equalization, IEEE Communication Letters, VOL. 15,
NO. 3, MARCH 2011.
Conferences
[3] A.R. Jafri, D. Karakolah, A. Baghdadi, and M. Jezequel,
ASIP-based Flexible MMSE-IC Linear Equalizer for MIMO
Turbo-Equalization Applications, In Proc. IEEE/ACM
Design, Automation and Test in Europe Conference &
Exhibition, DATE09, Nice, France, 21-23 April 2009.
[4] H.Moussa, O. Muller, A.R. Jafri,A. Baghdadi, J. Le Mestre,
and M. Jezequel, FPGA Prototypes For Turbo

[5]

[6]

[7]

[8]

[9]

[10]

[11]

Communication Applications, Poster and Demonstration


at the University Booth of the IEEE/ACM Design,
Automation and Test in Europe Conference & Exhibition,
DATE09, Nice, France, 21-23 April 2009.
A.R. Jafri, A. Baghdadi, and M. Jezequel, Rapid
Prototyping of ASIP-based flexible MMSE-IC Linear
Equalizer, In Proc. IEEE/IFIP 20th International
Symposium on Rapid System Prototyping, RSP09, Paris,
France, 23-26 June 2009.
A.R. Jafri, A. Baghdadi, and M. Jezequel, Rapid Design
and Prototyping of Universal Soft Demapper, In Proc. IEEE
International Symposium on Circuits and Systems,
ISCAS10, Paris, France, 30 May - 2 June 2010.
A.R. Jafri, A. Baghdadi, and M. Jezequel, DemASIP :
Universal Demapper for Multiwireless Standards, In GDR
SoC-SiP: Groupe de recherche System on Chip - System in
Package, Colloque National, Paris, France, 9-11 June 2010.
A.R. Jafri, A. Baghdadi, and M. Jezequel, Exploring
Parallel Processing Levels in Turbo Demodulation, In Proc.
IEEE 6th International Symposium on Turbo Codes and
Iterative Information Processing, Brest, France, 6-10 Sept
2010.
A.R. Jafri, A. Baghdadi, and M. Jezequel, FPGA Prototypes
of Heterogeneous multi-ASIP and NoC based Unified Turbo
Receiver for Multi Wireless Standards, Poster and
Demonstration at the University Booth of the IEEE/ACM
Design, Automation and Test in Europe Conference &
Exhibition, DATE11, Grenoble, France, 14-18 March 2011.
A.R. Jafri, and A. Baghdadi, Conversion Throughput Gain
in Parallel Turbo Receiver, In Proc. IEEE IBCAST13 ,
Islamabad ,Pakistan, 15-19 Jan 2013.
Yusra Mehmood, Umar Mujahid, M.Najam-ul-islam, A.R.
Jafri, Efficient Hardware Implementation of lightweight
Pseudo-random number generators, The Second
International Conference on Computer Science, Computer
Engineering, and Education Technologies (CSCEET2015),
Kuala Lumpur, Malaysia, September 8-10, 2015
(Accepted).

ATIF RAZA JAFRI, 2015

Islamabad, Pakistan.

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