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Frequency Ratios for DSP Measurements

By Eric Rosenfeld, former staff scientist for LTX Corporation (now LTX-Credence)
Abstract
DSP waveform instruments offer higher test performance through coherent measurements based on
using precise frequency ratios which are obtained by solving a set of integer constraints. This paper
presents analysis tools used to solve these constraints.
Introduction
Modern ATE systems include capabilities for precisely controlling the ratios of all key source and
measurement rates within the test system. This capability allows use of coherent synchronous source and
measurement techniques which yield faster and more precise testing.
However, this capability can be a double edged sword. Coherent techniques combine tester, device
and test technique constraints in a unified set of constraints. These constraints require integer (whole
number) frequency ratios1. Finding the precise combination of integers for a given application that
gives a particular ratio can be a daunting task. The traditional mathematical techniques taught in
engineering school do not apply to problems that must have integer solutions.
This paper presents a flow-graph method of modeling the frequency rate constraints of a specific test
application. Several different types of system components are examined to show how they are
modeled in a flow graph. Two specific mathematical techniques, continued fractions and prime number
factorization, are presented which are particularly useful for solving the constraints of flow graphs.
These techniques are introduced by working a series of example problems.
Examining a PLL
Test systems sometimes use Phase Locked Loops as a mechanism for generating one frequency from
another.

Figure 1 Block Diagram of a Phase Locked Loop

Figure 1 shows a simple block diagram for such a PLL. The PLL divides the reference frequency input
through a digital frequency divider which divides the reference frequency by an integer, D. The
divided frequency is used as the reference input to a phase comparator which receives the output of a
frequency divider (divide by N) driven from the VCO output. This PLL can be modeled by a simpler block
diagram shown in Figure 2. In this simplified block diagram the phase comparator, filter, VCO and second
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Frequency Ratios for DSP Measurements

divider are replaced with a frequency multiplier. While this equivalent diagram does not describe the
behavior of the PLL under all conditions, it is a useful description of the PLL when the PLL is in lock.
Programming the PLL in Figure 2 requires choosing values for D and N that produce the desired
frequency output. Simple algebraic techniques cannot yield the best values for D and N. The reason is
that algebra used for most engineering computation is based on real numbers which can have
either whole number or fractional values. Standard algebraic techniques do not offer methods for
imposing the integer constraint, when the solution to a set of equations must all be whole numbers.

Figure 2 Frequency Flow Graph of PLL

To illustrate the problem, consider what happens when the PLL in Figure 2 is used to create an output
frequency that is times the reference frequency. is not a rational number. It cannot be expressed
as the ratio of two whole numbers. Consequently, D and N must be chosen to, at best, approximate the
value of .
Continued Fractions
One very powerful method of approximating any number with a ratio is the method of continued
fractions. This technique is a simple algorithm that can be performed using a scientific or engineering
calculator. The version of the technique the author uses has two parts. First a sequence of integers,
{i1,i2...in},is computed as follows:

Compute an integer, i1, equal to the desired or target ratio, r0, rounded to the nearest whole
number.
Subtract i1 from the target ratio, r0. This difference,d1=r0-i1, should be a fractional part in the range
between -.5 and +.5.
Compute the reciprocal r1 of d1 (r1=1/d1).
Compute an integer, i2, equal to the reciprocal r1, rounded to the nearest whole number.
Subtract i2 from r1. This difference, d2=r1-i2, should be a fractional part in the range between -.5
and +.5.
Compute the reciprocal r2 of d2 (r2=1/d2).
and so on.

Once the sequence of integers {i1,i2...in} has been computed, the numerator Nn corresponding to the
integer sequence can be generated recursively2,3 from the numerators Nn-1 and Nn-2 by the recursive
equation:
Nn=in * Nn-1 + Nn-2 where N0=1 and N-1=0.
Similarly, the denominator Dn can be generated by the recursion:
Dn=in * Dn-1 + Dn-2 where D0=0 and D-1=1.
It should be noted that some of the pairs Nn/Dn generated by the recursion will contain integers that
are both negative. Since the minus sign will appear in both the numerator and denominator, the ratio
still has the correct sign. However, care must be exercised to use the signed value of numerator and
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Frequency Ratios for DSP Measurements

denominator in the recursion.

This recursion will yield an infinite sequence of i's if the original ratio, r0, is irrational. However,
regardless of the length of the sequence, the sequence can be terminated at any stage to obtain a
ratio that approximates the target ratio.
In the case of that was presented in the PLL example above, the sequence of {in}={3,7,16,-294,...}
results. This sequence generates the following integer ratio approximations of , any one of which
could be used, depending upon the constraints on the integer values used in the PLL:
Sequence

Ratio

Error

{3}

3/1

0.141592654

{3,7}

22/7

-0.001264489

{3,7,16}

355/113

-2.66764E-07

{3,7,16,-294}

104348/33215

-3.31628E-10

Table 1 First four approximations of

Continued Fractions Extended
In many applications, the integer used to program a register must fall within some numerical range. For
example, additional constraints could be added to the PLL in Figure 2. One such set of constraints is
shown in Figure 3. The two additional constraints are a reference frequency of 10MHz, and a phase
detector frequency range of 10kHz to 20kHz. If the ratio of the output frequency to input frequency is
still approximately' then the output frequency will be approximately 31.4...MHz. Given these
additional constraints, what is the best choice for D and N?

Figure 3 PLL Flow Diagram with phase comparator frequency constraint

To obtain a phase comparator frequency within the constrained range, D must be in the range
500<=D<=1000. Examining the list of ratios in the previous section, it is apparent that the third ratio has a
D (113) that is too small, and the fourth ratio has a D (33215) that is too large. It would seem reasonable
that there must be intermediate ratios that also give good accuracy.
One way to obtain an integer ratio with a denominator within the desired range is to multiply the
numerator and denominator by a common integer factor. For example, multiplying 355/113 by integers
between 5 and 8 yields the values for N and D shown in Table 2.

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Frequency Ratios for DSP Measurements

Factor

355

113

1775

565

2130

678

2485

791

2840

904

Table 2 Derived ratios

Integer ratios that may produce a better approximation error than the closest denominator that is less
than the desired range can sometimes be obtained by reducing the absolute value of the last integer (294 in the approximation for ) used to generate the denominate that is higher than the desired range.
This can be done using the recursions presented in the previous section to generate intermediate
integer ratios that have accuracy that is intermediate between two ratios generated by the continued
fraction method.
The third integer ratio is the result of using a sequence {in}={3,7,16}. The fourth ratio is generated from
the sequence {in}={3,7,16,-294}. A sequence of intermediate ratios can be computed as follows:
Integer Series

Error

{3,7,16,-146}

51808

16491

2.699E-07

{3,7,16,-146}

51808

16491

2.699E-07

{3,7,16,-147}

52163

16604

2.662E-07

{3,7,16,-148}

52518

16717

2.626E-07

{3,7,16,-149}

52873

16830

2.591E-07

{3,7,16,-150}

53228

16943

2.555E-07

Note that the table jumps from a ratio of 355/113 to a ratio of 51808/16491. This is because all
intermediate ratios have no better error than the ratio 355/113. Since all the ratios that have errors
better than the ratio 355/113 are in the range of 52163/16604 or higher, none of them are useful for
the specific PLL constraints in this example. However, with other conditions, intermediate ratios such
as these could be useful.

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Frequency Ratios for DSP Measurements

Flow Graphs
A flow graph is a graphical means of representing the frequency constraints within a tester's
instruments as well as within a DUT and the intended test technique. Each component within a given
test setup can be represented by zero or more inputs and one or more outputs. The flow diagram
shows the source of each input, as well as the relationship between the inputs and each output. Figure 2
and Figure 3 are examples of flow graphs for a PLL.

Figure 4 One reference with multiple dividers

Another example is shown in Figure 4. This flow graph shows a setup in which one frequency reference is
used to derive several different rates within a tester. The reference frequency is divided by different
integers to generate each of the necessary rates.
The only parameter of interest in this type flow diagram is the frequency of each signal and relationships
between frequencies enforced by the blocks in the flow diagram. Other characteristics of the generator
such as its power requirements, waveform shape, signal amplitude, etc. are of no concern in this
representation. (Certain characteristics such as waveform shape may be important in certain situations if
the signal is applied to a function which can respond to the individual frequency components, such as an
FFT.)
Modeling Common Test System Components
There are many components within a large automatic test system that can be modeled using a
frequency flow graph. In the following sections some of these are discussed.
Modeling a DSP Synthesizers
A DSP synthesizer generates analog waveform by reading sample values from a memory and applying
them at a regular sample rate to a D/A converter. The output signal from the D/A converter is further
conditioned by analog filtering and attenuation/amplification.
When a repetitive signal is generated with DSP synthesizer, it can be done using one of two methods:

Store a sample sequence equal in length to the total sample set needed to generate the signal for
the required duration of time.
Store a shorter sample set sufficient to create one or more complete cycles of the signal. During
playback of the sample sequence. When the sample set playback is completed and the last
sample is applied to the D/A, the memory address is looped back to the beginning of the stored
sequence, and the stored sequence is repeated.

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The first technique is useful for generating non-repetitive signals that have a finite duration. Generally,
this type of operation does not place any precise constraints on sample rate. Generally, the sample rate
will be selected to reproduce the desired waveform with a minimum of undesired artifact, or to allow
easy computation of the sample sequence.
The second technique is useful whenever a repetitive signal is needed. It is especially appropriate
when the signal must be of long or indefinite duration . To successfully apply this technique, the
sample rate and number of samples in the sample set must be carefully selected. If the number of
samples in the sample set times the sampling period (the reciprocal of the sampling rate) is not exactly
equal to the duration of a whole number of repetitions of the desired signal, a discontinuity will occur at
the point during signal generation where the memory loops back from the last sample to the first.

Figure 5 Flow diagram for DSP synthesizer or digitizer

The flow graph for a DSP synthesizer creating a multitone periodic signal is shown in Figure 5. The
integer 'n' is the number of samples stored in waveform memory for the signal sample set. Each of the
integers 'b1,b2,b3' is the number of complete signal repetitions within the n-sample sequence for each
tone. It also corresponds to the "bin" number of the location where the signal component would lie in the
result of the signal's FFT.
Modeling for a DSP Digitizer
The flow graph for a digitizer is exactly the same as for a DSP synthesizer (Figure 5). At first
this may seem strange, since it is normal to think of a digitizer as receiving signals, rather than generating
frequencies. However, the analysis frequencies that can be measured are strictly a function of the sample
rate and number of samples collected. If a frequency is applied to a digitizer's signal input that does not
fall exactly at one of the analysis frequencies, unpredictable measurements may result (depending upon
whether or not DSP windowing is used).
Modeling a Balanced Modulator
The flow graph for a balanced modulator (Figure 6) has two inputs and two outputs. The outputs are the
sum and differences of the input frequencies. It should be noted that if both input frequencies are integer
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multiples of a single Fourier frequency (reciprocal of UTP), the output frequencies will also be integer
multiples of the same frequency.

Figure 6 Flow diagram of Balanced Modulator

Modeling a Sample & Hold

A sample and hold circuit is similar to a balanced modulator in which one input is replaced by the
sampling frequency as well as all its harmonics. As a consequence, the output of the sample and hold
circuit not only contains the signal frequency (f1) plus or minus the sample frequency, it also includes the
signal frequency as well as the signal frequency plus or minus all the harmonics of the sample frequency.
Each frequency component at the output of the sample and hold circuit is a separate output of the sample
and hold circuit in its flow graph representation.

Figure 7 Flow diagram for sample and hold

Application Constraints
In many test applications, the settings of various integer values within the tester's timing generation
system are not governed by internal instrument constraints alone. In fact, device, test technique, and
instrument constraints must all be considered together to obtain an acceptable set of integer values.
To illustrate how all these constraints can work together, the specific case of coherent testing is
examined.
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Frequency Ratios for DSP Measurements

Coherent Test Requirements

Coherent testing offers significant advantages in test time and measurement precision. It operates by
tightly synchronizing both stimuli and measurements so that measurements are taken over one or an
integer number of unit periods, during which all test inputs and outputs exactly repeat one or more
times. Because the measurement interval always spans a whole number of signal repetitions, each
measurement never contains a fraction of a cycle residue beyond the complete cycles of the signal.
This is important because different devices may delay signals differently, causing unpredictable effects on
measured values. The effect of unsynchronized stimuli and measurements can often be eliminated
through the use of DSP window functions. However, to obtain the same level of precision, as much as
four times as many samples must be collected and analyzed. This results in longer data collection and
more time spent on computation.

Figure 8 Flow Graph for a coherent measurement

To achieve coherence between stimuli and measurements, additional constraints must be met. Figure
6 shows the flow graph for a synthesizer and digitizer being used to make a coherent gain
measurement. There is one characteristic of this flow graph that warrants additional discussion. All the
previous figures showed flow graphs which had a unique path from any point to any other point on the
graph. However, Figure 8 has closed loops with two paths from the reference frequency to the unit test
frequency, and two paths from the unit test frequency to the signal frequency.
In Figure 8, the constants are as follows:

n1 number of samples in DSP synthesizer memory

n2 number of times stimulus pattern is repeated during measurement interval
n3 number of samples collected in waveform digitizer
b1 bin number of source signal
b2 bin number of measured signal

As has been shown in the preceding sections, most elements in the timing architecture of a test are
either rate multipliers or dividers. As a result, the relationship between the input and output of any one
path in the graph will usually be a ratio of integers. When there are multiple paths from one frequency to
another in a flow graph, then the frequency ratios must be the same through each path.
If two pairs of numbers are in the same ratio, need the numbers themselves be the same? No.
However, when all common factors from the numerator and denominator of each ratio are removed,
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both ratios should contain exactly the same integers. Often times it is difficult spotting the common
factors in the numerator and denominator of a ratio. There is a very simple technique for removing
common factors from the numerator and denominator. Perform the division indicated by the ratio to
obtain a single number with fractional part. Then use the method of continued fractions to convert it
back to a ratio of integers. The resulting ratio will have no common factors shared in the numerator and
denominator.
From a design perspective this yields a strong constraint between the paths in the flow graph of a
coherent test:

The numerator of the reduced frequency ratio of one path must equal the numerator of the
reduced frequency ratio of a parallel path in a flow graph in parallel paths in a flow graph and

the denominator of the reduced frequency ratio of one path must equal the denominator of the
reduced frequency ratio of a parallel path in a flow graph in parallel paths in a flow graph

Prime Factors and Their Application

As indicated in the previous section, it is important that parallel paths contain specific factors in the
numerator and in the denominator. However, each block in a path may have its own set of constraints
that must be met. How can one be sure that the necessary factors are present in each path?
For example, if the numerator in one path were 41769, it would be difficult breaking this up so that it fit
into two cascaded registers that each could contain a value no greater than 1000. However, if you know
the prime factors, you could distribute them so that some of them were in each register, but the product of
all the factors assigned to any one register still met its constraints. In the case of 41769, the prime
factors are 17*13*7*3*3*3. These could be grouped in a variety of ways to yield two numbers both of
which are less than 1000. For example, each of the groupings in the table below fits the constraints of
two factors, each less than 1000, with a product equal to 41769.
Grouping 1

(17*13*3) or 663

(7*3*3) or 63

Grouping 2

(17*13) or 221

(7*3*3*3) or 189

Grouping 3

(17*7*3) or 359

(13*3*3) or 117

It would be very difficult identifying these factors directly. Only through the use of prime factors is it
easy to spot these alternative combinations.
Conclusions
Through the application of several different techniques, including flow graphs, continued fraction
expansion, and prime number factorization, the integer selection process for DSP testing applications
can be greatly simplified.
1 Matthew Mahoney, "DSP-Based Testing of Analog and Mixed-Signal Circuits", The Computer Society of
the IEEE, ISBN 0-8186-0785-8
2 Stark,

Numerical Analysis Introduction , MIT Press, Cambridge MA, 1978

3 G.

Moraes, In-House Paper:"Digital Signal Processing: Calculating Floating Point Rates for DSP Tester
Architectures"

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